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phoenix |
/* $Id: dbri.c,v 1.1.1.1 2004-04-15 02:07:26 phoenix Exp $
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* drivers/sbus/audio/dbri.c
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*
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* Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
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* Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
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*
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* This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
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* on Sun SPARCstation 10, 20, LX and Voyager models.
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*
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* - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
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* data time multiplexer with ISDN support (aka T7259)
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* Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
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* CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
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* Documentation:
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* - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
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* Sparc Technology Business (courtesy of Sun Support)
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* - Data sheet of the T7903, a newer but very similar ISA bus equivalent
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* available from the Lucent (formarly AT&T microelectronics) home
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* page.
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* - http://www.freesoft.org/Linux/DBRI/
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* - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
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* Interfaces: CHI, Audio In & Out, 2 bits parallel
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* Documentation: from the Crystal Semiconductor home page.
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*
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* The DBRI is a 32 pipe machine, each pipe can transfer some bits between
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* memory and a serial device (long pipes, nr 0-15) or between two serial
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* devices (short pipes, nr 16-31), or simply send a fixed data to a serial
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* device (short pipes).
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* A timeslot defines the bit-offset and nr of bits read from a serial device.
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* The timeslots are linked to 6 circular lists, one for each direction for
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* each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
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* (the second one is a monitor/tee pipe, valid only for serial input).
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*
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* The mmcodec is connected via the CHI bus and needs the data & some
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* parameters (volume, balance, output selection) timemultiplexed in 8 byte
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* chunks. It also has a control mode, which serves for audio format setting.
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*
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* Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
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* the same CHI bus, so I thought perhaps it is possible to use the onboard
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* & the speakerbox codec simultanously, giving 2 (not very independent :-)
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* audio devices. But the SUN HW group decided against it, at least on my
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* LX the speakerbox connector has at least 1 pin missing and 1 wrongly
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* connected.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <linux/delay.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sbus.h>
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#include <asm/pgtable.h>
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#include <asm/audioio.h>
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#include "dbri.h"
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#if defined(DBRI_ISDN)
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#include "../../isdn/hisax/hisax.h"
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#include "../../isdn/hisax/isdnl1.h"
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#include "../../isdn/hisax/foreign.h"
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#endif
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#define DBRI_DEBUG
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#ifdef DBRI_DEBUG
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#define dprintk(a, x) if(dbri_debug & a) printk x
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#define D_GEN (1<<0)
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#define D_INT (1<<1)
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#define D_CMD (1<<2)
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#define D_MM (1<<3)
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#define D_USR (1<<4)
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#define D_DESC (1<<5)
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static int dbri_debug = 0;
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MODULE_PARM(dbri_debug, "i");
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static int dbri_trace = 0;
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MODULE_PARM(dbri_trace, "i");
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#define tprintk(x) if(dbri_trace) printk x
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static char *cmds[] = {
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"WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
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"SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
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};
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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value)
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#else
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#define dprintk(a, x)
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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value)
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#endif /* DBRI_DEBUG */
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#define MAX_DRIVERS 2 /* Increase this if need more than 2 DBRI's */
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static struct sparcaudio_driver drivers[MAX_DRIVERS];
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static int num_drivers = 0;
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/*
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****************************************************************************
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************** DBRI initialization and command synchronization *************
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****************************************************************************
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Commands are sent to the DBRI by building a list of them in memory,
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then writing the address of the first list item to DBRI register 8.
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The list is terminated with a WAIT command, which can generate a
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CPU interrupt if required.
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Since the DBRI can run in parallel with the CPU, several means of
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synchronization present themselves. The original scheme (Rudolf's)
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was to set a flag when we "cmdlock"ed the DBRI, clear the flag when
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an interrupt signaled completion, and wait on a wait_queue if a routine
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attempted to cmdlock while the flag was set. The problems arose when
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we tried to cmdlock from inside an interrupt handler, which might
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cause scheduling in an interrupt (if we waited), etc, etc
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A more sophisticated scheme might involve a circular command buffer
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or an array of command buffers. A routine could fill one with
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commands and link it onto a list. When a interrupt signaled
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completion of the current command buffer, look on the list for
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the next one.
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I've decided to implement something much simpler - after each command,
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the CPU waits for the DBRI to finish the command by polling the P bit
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in DBRI register 0. I've tried to implement this in such a way
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that might make implementing a more sophisticated scheme easier.
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Every time a routine wants to write commands to the DBRI, it must
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first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
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in return. After the commands have been writen, dbri_cmdsend() is
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called with the final pointer value.
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Something a little more clever is required if this code is ever run
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on an SMP machine.
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*/
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static int dbri_locked = 0;
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static volatile s32 *dbri_cmdlock(struct dbri *dbri)
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{
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if (dbri_locked)
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printk("DBRI: Command buffer locked! (bug in driver)\n");
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dbri_locked++;
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return &dbri->dma->cmd[0];
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}
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static void dbri_process_interrupt_buffer(struct dbri *);
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static void dbri_cmdsend(struct dbri *dbri, volatile s32 *cmd)
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{
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int MAXLOOPS = 1000000;
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int maxloops = MAXLOOPS;
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unsigned long flags;
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volatile s32 *ptr;
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for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
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dprintk(D_CMD, ("DBRI cmd: %lx:%08x\n",
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(unsigned long) ptr, *ptr));
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}
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save_and_cli(flags);
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dbri_locked--;
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if (dbri_locked != 0) {
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printk("DBRI: Command buffer improperly locked! (bug in driver)\n");
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} else if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS-1) {
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printk("DBRI: Command buffer overflow! (bug in driver)\n");
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} else {
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*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
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*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
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dbri->wait_seen = 0;
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sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
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while ((--maxloops) > 0 &&
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(sbus_readl(dbri->regs + REG0) & D_P))
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barrier();
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if (maxloops == 0) {
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printk("DBRI: Chip never completed command buffer\n");
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} else {
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while ((--maxloops) > 0 && (! dbri->wait_seen))
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dbri_process_interrupt_buffer(dbri);
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if (maxloops == 0) {
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printk("DBRI: Chip never acked WAIT\n");
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} else {
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dprintk(D_INT, ("DBRI: Chip completed command "
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"buffer (%d)\n",
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MAXLOOPS - maxloops));
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}
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}
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}
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restore_flags(flags);
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}
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static void dbri_reset(struct dbri *dbri)
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{
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int i;
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dprintk(D_GEN, ("DBRI: reset 0:%x 2:%x 8:%x 9:%x\n",
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sbus_readl(dbri->regs + REG0),
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sbus_readl(dbri->regs + REG2),
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sbus_readl(dbri->regs + REG8),
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sbus_readl(dbri->regs + REG9)));
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sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
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for(i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
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udelay(10);
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}
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static void dbri_detach(struct dbri *dbri)
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{
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dbri_reset(dbri);
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free_irq(dbri->irq, dbri);
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sbus_iounmap(dbri->regs, dbri->regs_size);
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sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
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(void *)dbri->dma, dbri->dma_dvma);
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kfree(dbri);
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}
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static void dbri_initialize(struct dbri *dbri)
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{
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volatile s32 *cmd;
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u32 dma_addr, tmp;
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int n;
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dbri_reset(dbri);
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dprintk(D_GEN, ("DBRI: init: cmd: %p, int: %p\n",
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&dbri->dma->cmd[0], &dbri->dma->intr[0]));
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/*
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* Initialize the interrupt ringbuffer.
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*/
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for(n = 0; n < DBRI_NO_INTS-1; n++) {
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dma_addr = dbri->dma_dvma;
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dma_addr += dbri_dma_off(intr, ((n+1) & DBRI_INT_BLK));
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dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
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}
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dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
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dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
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dbri->dbri_irqp = 1;
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257 |
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/* We should query the openprom to see what burst sizes this
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258 |
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* SBus supports. For now, just disable all SBus bursts */
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tmp = sbus_readl(dbri->regs + REG0);
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tmp &= ~(D_G | D_S | D_E);
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261 |
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sbus_writel(tmp, dbri->regs + REG0);
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262 |
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263 |
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/*
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264 |
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* Set up the interrupt queue
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265 |
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*/
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266 |
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cmd = dbri_cmdlock(dbri);
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267 |
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dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
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268 |
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*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
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*(cmd++) = dma_addr;
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270 |
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271 |
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dbri_cmdsend(dbri, cmd);
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272 |
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}
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273 |
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274 |
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275 |
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/*
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276 |
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****************************************************************************
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277 |
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*************************** DBRI interrupt handler *************************
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278 |
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****************************************************************************
|
279 |
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|
280 |
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The DBRI communicates with the CPU mainly via a circular interrupt
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281 |
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buffer. When an interrupt is signaled, the CPU walks through the
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282 |
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buffer and calls dbri_process_one_interrupt() for each interrupt word.
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283 |
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Complicated interrupts are handled by dedicated functions (which
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284 |
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appear first in this file). Any pending interrupts can be serviced by
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285 |
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calling dbri_process_interrupt_buffer(), which works even if the CPU's
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286 |
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interrupts are disabled. This function is used by dbri_cmdsend()
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287 |
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to make sure we're synced up with the chip after each command sequence,
|
288 |
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even if we're running cli'ed.
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289 |
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|
290 |
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*/
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291 |
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|
292 |
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|
293 |
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/*
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294 |
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* Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
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295 |
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* So we have to reverse the bits. Note: not all bit lengths are supported
|
296 |
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*/
|
297 |
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static __u32 reverse_bytes(__u32 b, int len)
|
298 |
|
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{
|
299 |
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switch(len) {
|
300 |
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case 32:
|
301 |
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b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
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302 |
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case 16:
|
303 |
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b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
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304 |
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case 8:
|
305 |
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b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
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306 |
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case 4:
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307 |
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b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
|
308 |
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case 2:
|
309 |
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b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
|
310 |
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case 1:
|
311 |
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case 0:
|
312 |
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break;
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313 |
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default:
|
314 |
|
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printk("DBRI reverse_bytes: unsupported length\n");
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315 |
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};
|
316 |
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|
317 |
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return b;
|
318 |
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}
|
319 |
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|
320 |
|
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/* transmission_complete_intr()
|
321 |
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*
|
322 |
|
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* Called by main interrupt handler when DBRI signals transmission complete
|
323 |
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* on a pipe (interrupt triggered by the B bit in a transmit descriptor).
|
324 |
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*
|
325 |
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* Walks through the pipe's list of transmit buffer descriptors, releasing
|
326 |
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* each one's DMA buffer (if present), flagging the descriptor available,
|
327 |
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* and signaling its callback routine (if present), before proceeding
|
328 |
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* to the next one. Stops when the first descriptor is found without
|
329 |
|
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* TBC (Transmit Buffer Complete) set, or we've run through them all.
|
330 |
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*/
|
331 |
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|
332 |
|
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static void transmission_complete_intr(struct dbri *dbri, int pipe)
|
333 |
|
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{
|
334 |
|
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int td;
|
335 |
|
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int status;
|
336 |
|
|
void *buffer;
|
337 |
|
|
void (*callback)(void *, int);
|
338 |
|
|
void *callback_arg;
|
339 |
|
|
|
340 |
|
|
td = dbri->pipes[pipe].desc;
|
341 |
|
|
|
342 |
|
|
while (td >= 0) {
|
343 |
|
|
if (td >= DBRI_NO_DESCS) {
|
344 |
|
|
printk("DBRI: invalid td on pipe %d\n", pipe);
|
345 |
|
|
return;
|
346 |
|
|
}
|
347 |
|
|
|
348 |
|
|
status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
|
349 |
|
|
|
350 |
|
|
if (! (status & DBRI_TD_TBC)) {
|
351 |
|
|
break;
|
352 |
|
|
}
|
353 |
|
|
|
354 |
|
|
dprintk(D_INT, ("DBRI: TD %d, status 0x%02x\n", td, status));
|
355 |
|
|
|
356 |
|
|
buffer = dbri->descs[td].buffer;
|
357 |
|
|
if (buffer)
|
358 |
|
|
sbus_unmap_single(dbri->sdev,
|
359 |
|
|
dbri->descs[td].buffer_dvma,
|
360 |
|
|
dbri->descs[td].len,
|
361 |
|
|
SBUS_DMA_TODEVICE);
|
362 |
|
|
|
363 |
|
|
callback = dbri->descs[td].output_callback;
|
364 |
|
|
callback_arg = dbri->descs[td].output_callback_arg;
|
365 |
|
|
|
366 |
|
|
dbri->descs[td].inuse = 0;
|
367 |
|
|
|
368 |
|
|
td = dbri->descs[td].next;
|
369 |
|
|
dbri->pipes[pipe].desc = td;
|
370 |
|
|
|
371 |
|
|
if (callback != NULL)
|
372 |
|
|
callback(callback_arg, status & 0xe);
|
373 |
|
|
}
|
374 |
|
|
}
|
375 |
|
|
|
376 |
|
|
static void reception_complete_intr(struct dbri *dbri, int pipe)
|
377 |
|
|
{
|
378 |
|
|
int rd = dbri->pipes[pipe].desc;
|
379 |
|
|
s32 status;
|
380 |
|
|
void *buffer;
|
381 |
|
|
void (*callback)(void *, int, unsigned int);
|
382 |
|
|
|
383 |
|
|
if (rd < 0 || rd >= DBRI_NO_DESCS) {
|
384 |
|
|
printk("DBRI: invalid rd on pipe %d\n", pipe);
|
385 |
|
|
return;
|
386 |
|
|
}
|
387 |
|
|
|
388 |
|
|
dbri->descs[rd].inuse = 0;
|
389 |
|
|
dbri->pipes[pipe].desc = dbri->descs[rd].next;
|
390 |
|
|
status = dbri->dma->desc[rd].word1;
|
391 |
|
|
|
392 |
|
|
buffer = dbri->descs[rd].buffer;
|
393 |
|
|
if (buffer)
|
394 |
|
|
sbus_unmap_single(dbri->sdev,
|
395 |
|
|
dbri->descs[rd].buffer_dvma,
|
396 |
|
|
dbri->descs[rd].len,
|
397 |
|
|
SBUS_DMA_FROMDEVICE);
|
398 |
|
|
|
399 |
|
|
callback = dbri->descs[rd].input_callback;
|
400 |
|
|
if (callback != NULL)
|
401 |
|
|
callback(dbri->descs[rd].input_callback_arg,
|
402 |
|
|
DBRI_RD_STATUS(status),
|
403 |
|
|
DBRI_RD_CNT(status)-2);
|
404 |
|
|
|
405 |
|
|
dprintk(D_INT, ("DBRI: Recv RD %d, status 0x%02x, len %d\n",
|
406 |
|
|
rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)));
|
407 |
|
|
}
|
408 |
|
|
|
409 |
|
|
static void dbri_process_one_interrupt(struct dbri *dbri, int x)
|
410 |
|
|
{
|
411 |
|
|
int val = D_INTR_GETVAL(x);
|
412 |
|
|
int channel = D_INTR_GETCHAN(x);
|
413 |
|
|
int command = D_INTR_GETCMD(x);
|
414 |
|
|
int code = D_INTR_GETCODE(x);
|
415 |
|
|
int rval = D_INTR_GETRVAL(x);
|
416 |
|
|
|
417 |
|
|
if (channel == D_INTR_CMD) {
|
418 |
|
|
dprintk(D_INT,("DBRI: INTR: Command: %-5s Value:%d\n",
|
419 |
|
|
cmds[command], val));
|
420 |
|
|
} else {
|
421 |
|
|
dprintk(D_INT,("DBRI: INTR: Chan:%d Code:%d Val:%#x\n",
|
422 |
|
|
channel, code, rval));
|
423 |
|
|
}
|
424 |
|
|
|
425 |
|
|
if (channel == D_INTR_CMD && command == D_WAIT)
|
426 |
|
|
dbri->wait_seen++;
|
427 |
|
|
|
428 |
|
|
if (code == D_INTR_SBRI) {
|
429 |
|
|
/* SBRI - BRI status change */
|
430 |
|
|
const int liu_states[] = {1, 0, 8, 3, 4, 5, 6, 7};
|
431 |
|
|
|
432 |
|
|
dbri->liu_state = liu_states[val & 0x7];
|
433 |
|
|
if (dbri->liu_callback)
|
434 |
|
|
dbri->liu_callback(dbri->liu_callback_arg);
|
435 |
|
|
}
|
436 |
|
|
|
437 |
|
|
if (code == D_INTR_BRDY)
|
438 |
|
|
reception_complete_intr(dbri, channel);
|
439 |
|
|
|
440 |
|
|
if (code == D_INTR_XCMP)
|
441 |
|
|
transmission_complete_intr(dbri, channel);
|
442 |
|
|
|
443 |
|
|
if (code == D_INTR_UNDR) {
|
444 |
|
|
/* UNDR - Transmission underrun
|
445 |
|
|
* resend SDP command with clear pipe bit (C) set
|
446 |
|
|
*/
|
447 |
|
|
volatile s32 *cmd;
|
448 |
|
|
int pipe = channel;
|
449 |
|
|
int td = dbri->pipes[pipe].desc;
|
450 |
|
|
|
451 |
|
|
dbri->dma->desc[td].word4 = 0;
|
452 |
|
|
|
453 |
|
|
cmd = dbri_cmdlock(dbri);
|
454 |
|
|
*(cmd++) = DBRI_CMD(D_SDP, 0,
|
455 |
|
|
dbri->pipes[pipe].sdp
|
456 |
|
|
| D_SDP_P | D_SDP_C | D_SDP_2SAME);
|
457 |
|
|
*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
|
458 |
|
|
dbri_cmdsend(dbri, cmd);
|
459 |
|
|
}
|
460 |
|
|
|
461 |
|
|
if (code == D_INTR_FXDT) {
|
462 |
|
|
/* FXDT - Fixed data change */
|
463 |
|
|
if (dbri->pipes[channel].sdp & D_SDP_MSB)
|
464 |
|
|
val = reverse_bytes(val, dbri->pipes[channel].length);
|
465 |
|
|
|
466 |
|
|
if (dbri->pipes[channel].recv_fixed_ptr)
|
467 |
|
|
*(dbri->pipes[channel].recv_fixed_ptr) = val;
|
468 |
|
|
}
|
469 |
|
|
}
|
470 |
|
|
|
471 |
|
|
/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
|
472 |
|
|
* buffer until it finds a zero word (indicating nothing more to do
|
473 |
|
|
* right now). Non-zero words require processing and are handed off
|
474 |
|
|
* to dbri_process_one_interrupt AFTER advancing the pointer. This
|
475 |
|
|
* order is important since we might recurse back into this function
|
476 |
|
|
* and need to make sure the pointer has been advanced first.
|
477 |
|
|
*/
|
478 |
|
|
static void dbri_process_interrupt_buffer(struct dbri *dbri)
|
479 |
|
|
{
|
480 |
|
|
s32 x;
|
481 |
|
|
|
482 |
|
|
while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
|
483 |
|
|
dbri->dma->intr[dbri->dbri_irqp] = 0;
|
484 |
|
|
dbri->dbri_irqp++;
|
485 |
|
|
if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK))
|
486 |
|
|
dbri->dbri_irqp = 1;
|
487 |
|
|
else if ((dbri->dbri_irqp & (DBRI_INT_BLK-1)) == 0)
|
488 |
|
|
dbri->dbri_irqp++;
|
489 |
|
|
|
490 |
|
|
tprintk(("dbri->dbri_irqp == %d\n", dbri->dbri_irqp));
|
491 |
|
|
dbri_process_one_interrupt(dbri, x);
|
492 |
|
|
}
|
493 |
|
|
}
|
494 |
|
|
|
495 |
|
|
static void dbri_intr(int irq, void *opaque, struct pt_regs *regs)
|
496 |
|
|
{
|
497 |
|
|
struct dbri *dbri = (struct dbri *) opaque;
|
498 |
|
|
int x;
|
499 |
|
|
|
500 |
|
|
/*
|
501 |
|
|
* Read it, so the interrupt goes away.
|
502 |
|
|
*/
|
503 |
|
|
x = sbus_readl(dbri->regs + REG1);
|
504 |
|
|
|
505 |
|
|
dprintk(D_INT, ("DBRI: Interrupt! (reg1=0x%08x)\n", x));
|
506 |
|
|
|
507 |
|
|
if (x & (D_MRR|D_MLE|D_LBG|D_MBE)) {
|
508 |
|
|
u32 tmp;
|
509 |
|
|
|
510 |
|
|
if(x & D_MRR) printk("DBRI: Multiple Error Ack on SBus\n");
|
511 |
|
|
if(x & D_MLE) printk("DBRI: Multiple Late Error on SBus\n");
|
512 |
|
|
if(x & D_LBG) printk("DBRI: Lost Bus Grant on SBus\n");
|
513 |
|
|
if(x & D_MBE) printk("DBRI: Burst Error on SBus\n");
|
514 |
|
|
|
515 |
|
|
/* Some of these SBus errors cause the chip's SBus circuitry
|
516 |
|
|
* to be disabled, so just re-enable and try to keep going.
|
517 |
|
|
*
|
518 |
|
|
* The only one I've seen is MRR, which will be triggered
|
519 |
|
|
* if you let a transmit pipe underrun, then try to CDP it.
|
520 |
|
|
*
|
521 |
|
|
* If these things persist, we should probably reset
|
522 |
|
|
* and re-init the chip.
|
523 |
|
|
*/
|
524 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
525 |
|
|
tmp &= ~(D_D);
|
526 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
527 |
|
|
}
|
528 |
|
|
|
529 |
|
|
#if 0
|
530 |
|
|
if (!(x & D_IR)) /* Not for us */
|
531 |
|
|
return;
|
532 |
|
|
#endif
|
533 |
|
|
|
534 |
|
|
dbri_process_interrupt_buffer(dbri);
|
535 |
|
|
}
|
536 |
|
|
|
537 |
|
|
|
538 |
|
|
/*
|
539 |
|
|
****************************************************************************
|
540 |
|
|
************************** DBRI data pipe management ***********************
|
541 |
|
|
****************************************************************************
|
542 |
|
|
|
543 |
|
|
While DBRI control functions use the command and interrupt buffers, the
|
544 |
|
|
main data path takes the form of data pipes, which can be short (command
|
545 |
|
|
and interrupt driven), or long (attached to DMA buffers). These functions
|
546 |
|
|
provide a rudimentary means of setting up and managing the DBRI's pipes,
|
547 |
|
|
but the calling functions have to make sure they respect the pipes' linked
|
548 |
|
|
list ordering, among other things. The transmit and receive functions
|
549 |
|
|
here interface closely with the transmit and receive interrupt code.
|
550 |
|
|
|
551 |
|
|
*/
|
552 |
|
|
static int pipe_active(struct dbri *dbri, int pipe)
|
553 |
|
|
{
|
554 |
|
|
return (dbri->pipes[pipe].desc != -1);
|
555 |
|
|
}
|
556 |
|
|
|
557 |
|
|
|
558 |
|
|
/* reset_pipe(dbri, pipe)
|
559 |
|
|
*
|
560 |
|
|
* Called on an in-use pipe to clear anything being transmitted or received
|
561 |
|
|
*/
|
562 |
|
|
static void reset_pipe(struct dbri *dbri, int pipe)
|
563 |
|
|
{
|
564 |
|
|
int sdp;
|
565 |
|
|
int desc;
|
566 |
|
|
volatile int *cmd;
|
567 |
|
|
|
568 |
|
|
if (pipe < 0 || pipe > 31) {
|
569 |
|
|
printk("DBRI: reset_pipe called with illegal pipe number\n");
|
570 |
|
|
return;
|
571 |
|
|
}
|
572 |
|
|
|
573 |
|
|
sdp = dbri->pipes[pipe].sdp;
|
574 |
|
|
if (sdp == 0) {
|
575 |
|
|
printk("DBRI: reset_pipe called on uninitialized pipe\n");
|
576 |
|
|
return;
|
577 |
|
|
}
|
578 |
|
|
|
579 |
|
|
cmd = dbri_cmdlock(dbri);
|
580 |
|
|
*(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
|
581 |
|
|
*(cmd++) = 0;
|
582 |
|
|
dbri_cmdsend(dbri, cmd);
|
583 |
|
|
|
584 |
|
|
desc = dbri->pipes[pipe].desc;
|
585 |
|
|
while (desc != -1) {
|
586 |
|
|
void *buffer = dbri->descs[desc].buffer;
|
587 |
|
|
void (*output_callback) (void *, int)
|
588 |
|
|
= dbri->descs[desc].output_callback;
|
589 |
|
|
void *output_callback_arg
|
590 |
|
|
= dbri->descs[desc].output_callback_arg;
|
591 |
|
|
void (*input_callback) (void *, int, unsigned int)
|
592 |
|
|
= dbri->descs[desc].input_callback;
|
593 |
|
|
void *input_callback_arg
|
594 |
|
|
= dbri->descs[desc].input_callback_arg;
|
595 |
|
|
|
596 |
|
|
if (buffer)
|
597 |
|
|
sbus_unmap_single(dbri->sdev,
|
598 |
|
|
dbri->descs[desc].buffer_dvma,
|
599 |
|
|
dbri->descs[desc].len,
|
600 |
|
|
output_callback != NULL ? SBUS_DMA_TODEVICE
|
601 |
|
|
: SBUS_DMA_FROMDEVICE);
|
602 |
|
|
|
603 |
|
|
dbri->descs[desc].inuse = 0;
|
604 |
|
|
desc = dbri->descs[desc].next;
|
605 |
|
|
|
606 |
|
|
if (output_callback)
|
607 |
|
|
output_callback(output_callback_arg, -1);
|
608 |
|
|
|
609 |
|
|
if (input_callback)
|
610 |
|
|
input_callback(input_callback_arg, -1, 0);
|
611 |
|
|
}
|
612 |
|
|
|
613 |
|
|
dbri->pipes[pipe].desc = -1;
|
614 |
|
|
}
|
615 |
|
|
|
616 |
|
|
static void setup_pipe(struct dbri *dbri, int pipe, int sdp)
|
617 |
|
|
{
|
618 |
|
|
if (pipe < 0 || pipe > 31) {
|
619 |
|
|
printk("DBRI: setup_pipe called with illegal pipe number\n");
|
620 |
|
|
return;
|
621 |
|
|
}
|
622 |
|
|
|
623 |
|
|
if ((sdp & 0xf800) != sdp) {
|
624 |
|
|
printk("DBRI: setup_pipe called with strange SDP value\n");
|
625 |
|
|
/* sdp &= 0xf800; */
|
626 |
|
|
}
|
627 |
|
|
|
628 |
|
|
/* If this is a fixed receive pipe, arrange for an interrupt
|
629 |
|
|
* every time its data changes
|
630 |
|
|
*/
|
631 |
|
|
if (D_SDP_MODE(sdp) == D_SDP_FIXED && ! (sdp & D_SDP_TO_SER))
|
632 |
|
|
sdp |= D_SDP_CHANGE;
|
633 |
|
|
|
634 |
|
|
sdp |= D_PIPE(pipe);
|
635 |
|
|
dbri->pipes[pipe].sdp = sdp;
|
636 |
|
|
dbri->pipes[pipe].desc = -1;
|
637 |
|
|
|
638 |
|
|
reset_pipe(dbri, pipe);
|
639 |
|
|
}
|
640 |
|
|
|
641 |
|
|
static void link_time_slot(struct dbri *dbri, int pipe,
|
642 |
|
|
enum in_or_out direction, int basepipe,
|
643 |
|
|
int length, int cycle)
|
644 |
|
|
{
|
645 |
|
|
volatile s32 *cmd;
|
646 |
|
|
int val;
|
647 |
|
|
int prevpipe;
|
648 |
|
|
int nextpipe;
|
649 |
|
|
|
650 |
|
|
if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
|
651 |
|
|
printk("DBRI: link_time_slot called with illegal pipe number\n");
|
652 |
|
|
return;
|
653 |
|
|
}
|
654 |
|
|
|
655 |
|
|
if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
|
656 |
|
|
printk("DBRI: link_time_slot called on uninitialized pipe\n");
|
657 |
|
|
return;
|
658 |
|
|
}
|
659 |
|
|
|
660 |
|
|
/* Deal with CHI special case:
|
661 |
|
|
* "If transmission on edges 0 or 1 is desired, then cycle n
|
662 |
|
|
* (where n = # of bit times per frame...) must be used."
|
663 |
|
|
* - DBRI data sheet, page 11
|
664 |
|
|
*/
|
665 |
|
|
if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
|
666 |
|
|
cycle = dbri->chi_bpf;
|
667 |
|
|
|
668 |
|
|
if (basepipe == pipe) {
|
669 |
|
|
prevpipe = pipe;
|
670 |
|
|
nextpipe = pipe;
|
671 |
|
|
} else {
|
672 |
|
|
/* We're not initializing a new linked list (basepipe != pipe),
|
673 |
|
|
* so run through the linked list and find where this pipe
|
674 |
|
|
* should be sloted in, based on its cycle. CHI confuses
|
675 |
|
|
* things a bit, since it has a single anchor for both its
|
676 |
|
|
* transmit and receive lists.
|
677 |
|
|
*/
|
678 |
|
|
if (basepipe == 16) {
|
679 |
|
|
if (direction == PIPEinput) {
|
680 |
|
|
prevpipe = dbri->chi_in_pipe;
|
681 |
|
|
} else {
|
682 |
|
|
prevpipe = dbri->chi_out_pipe;
|
683 |
|
|
}
|
684 |
|
|
} else {
|
685 |
|
|
prevpipe = basepipe;
|
686 |
|
|
}
|
687 |
|
|
|
688 |
|
|
nextpipe = dbri->pipes[prevpipe].nextpipe;
|
689 |
|
|
|
690 |
|
|
while (dbri->pipes[nextpipe].cycle < cycle
|
691 |
|
|
&& dbri->pipes[nextpipe].nextpipe != basepipe) {
|
692 |
|
|
prevpipe = nextpipe;
|
693 |
|
|
nextpipe = dbri->pipes[nextpipe].nextpipe;
|
694 |
|
|
}
|
695 |
|
|
}
|
696 |
|
|
|
697 |
|
|
if (prevpipe == 16) {
|
698 |
|
|
if (direction == PIPEinput) {
|
699 |
|
|
dbri->chi_in_pipe = pipe;
|
700 |
|
|
} else {
|
701 |
|
|
dbri->chi_out_pipe = pipe;
|
702 |
|
|
}
|
703 |
|
|
} else {
|
704 |
|
|
dbri->pipes[prevpipe].nextpipe = pipe;
|
705 |
|
|
}
|
706 |
|
|
|
707 |
|
|
dbri->pipes[pipe].nextpipe = nextpipe;
|
708 |
|
|
dbri->pipes[pipe].cycle = cycle;
|
709 |
|
|
dbri->pipes[pipe].length = length;
|
710 |
|
|
|
711 |
|
|
cmd = dbri_cmdlock(dbri);
|
712 |
|
|
|
713 |
|
|
if (direction == PIPEinput) {
|
714 |
|
|
val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
|
715 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
716 |
|
|
*(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
|
717 |
|
|
*(cmd++) = 0;
|
718 |
|
|
} else {
|
719 |
|
|
val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
|
720 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
721 |
|
|
*(cmd++) = 0;
|
722 |
|
|
*(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
|
723 |
|
|
}
|
724 |
|
|
|
725 |
|
|
dbri_cmdsend(dbri, cmd);
|
726 |
|
|
}
|
727 |
|
|
|
728 |
|
|
/* I don't use this function, so it's basically untested. */
|
729 |
|
|
static void unlink_time_slot(struct dbri *dbri, int pipe,
|
730 |
|
|
enum in_or_out direction, int prevpipe,
|
731 |
|
|
int nextpipe)
|
732 |
|
|
{
|
733 |
|
|
volatile s32 *cmd;
|
734 |
|
|
int val;
|
735 |
|
|
|
736 |
|
|
if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
|
737 |
|
|
printk("DBRI: unlink_time_slot called with illegal pipe number\n");
|
738 |
|
|
return;
|
739 |
|
|
}
|
740 |
|
|
|
741 |
|
|
cmd = dbri_cmdlock(dbri);
|
742 |
|
|
|
743 |
|
|
if (direction == PIPEinput) {
|
744 |
|
|
val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
|
745 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
746 |
|
|
*(cmd++) = D_TS_NEXT(nextpipe);
|
747 |
|
|
*(cmd++) = 0;
|
748 |
|
|
} else {
|
749 |
|
|
val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
|
750 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
751 |
|
|
*(cmd++) = 0;
|
752 |
|
|
*(cmd++) = D_TS_NEXT(nextpipe);
|
753 |
|
|
}
|
754 |
|
|
|
755 |
|
|
dbri_cmdsend(dbri, cmd);
|
756 |
|
|
}
|
757 |
|
|
|
758 |
|
|
/* xmit_fixed() / recv_fixed()
|
759 |
|
|
*
|
760 |
|
|
* Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
|
761 |
|
|
* expected to change much, and which we don't need to buffer.
|
762 |
|
|
* The DBRI only interrupts us when the data changes (receive pipes),
|
763 |
|
|
* or only changes the data when this function is called (transmit pipes).
|
764 |
|
|
* Only short pipes (numbers 16-31) can be used in fixed data mode.
|
765 |
|
|
*
|
766 |
|
|
* These function operate on a 32-bit field, no matter how large
|
767 |
|
|
* the actual time slot is. The interrupt handler takes care of bit
|
768 |
|
|
* ordering and alignment. An 8-bit time slot will always end up
|
769 |
|
|
* in the low-order 8 bits, filled either MSB-first or LSB-first,
|
770 |
|
|
* depending on the settings passed to setup_pipe()
|
771 |
|
|
*/
|
772 |
|
|
static void xmit_fixed(struct dbri *dbri, int pipe, unsigned int data)
|
773 |
|
|
{
|
774 |
|
|
volatile s32 *cmd;
|
775 |
|
|
|
776 |
|
|
if (pipe < 16 || pipe > 31) {
|
777 |
|
|
printk("DBRI: xmit_fixed: Illegal pipe number\n");
|
778 |
|
|
return;
|
779 |
|
|
}
|
780 |
|
|
|
781 |
|
|
if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
|
782 |
|
|
printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
|
783 |
|
|
return;
|
784 |
|
|
}
|
785 |
|
|
|
786 |
|
|
if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
|
787 |
|
|
printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
|
788 |
|
|
return;
|
789 |
|
|
}
|
790 |
|
|
|
791 |
|
|
if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
|
792 |
|
|
printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
|
793 |
|
|
return;
|
794 |
|
|
}
|
795 |
|
|
|
796 |
|
|
/* DBRI short pipes always transmit LSB first */
|
797 |
|
|
|
798 |
|
|
if (dbri->pipes[pipe].sdp & D_SDP_MSB)
|
799 |
|
|
data = reverse_bytes(data, dbri->pipes[pipe].length);
|
800 |
|
|
|
801 |
|
|
cmd = dbri_cmdlock(dbri);
|
802 |
|
|
|
803 |
|
|
*(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
|
804 |
|
|
*(cmd++) = data;
|
805 |
|
|
|
806 |
|
|
dbri_cmdsend(dbri, cmd);
|
807 |
|
|
}
|
808 |
|
|
|
809 |
|
|
static void recv_fixed(struct dbri *dbri, int pipe, volatile __u32 *ptr)
|
810 |
|
|
{
|
811 |
|
|
if (pipe < 16 || pipe > 31) {
|
812 |
|
|
printk("DBRI: recv_fixed called with illegal pipe number\n");
|
813 |
|
|
return;
|
814 |
|
|
}
|
815 |
|
|
|
816 |
|
|
if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
|
817 |
|
|
printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
|
818 |
|
|
return;
|
819 |
|
|
}
|
820 |
|
|
|
821 |
|
|
if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
|
822 |
|
|
printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe);
|
823 |
|
|
return;
|
824 |
|
|
}
|
825 |
|
|
|
826 |
|
|
dbri->pipes[pipe].recv_fixed_ptr = ptr;
|
827 |
|
|
}
|
828 |
|
|
|
829 |
|
|
|
830 |
|
|
/* xmit_on_pipe() / recv_on_pipe()
|
831 |
|
|
*
|
832 |
|
|
* Transmit/receive data on a "long" pipe - i.e, one associated
|
833 |
|
|
* with a DMA buffer.
|
834 |
|
|
*
|
835 |
|
|
* Only pipe numbers 0-15 can be used in this mode.
|
836 |
|
|
*
|
837 |
|
|
* Both functions take pointer/len arguments pointing to a data buffer,
|
838 |
|
|
* and both provide callback functions (may be NULL) to notify higher
|
839 |
|
|
* level code when transmission/reception is complete.
|
840 |
|
|
*
|
841 |
|
|
* Both work by building chains of descriptors which identify the
|
842 |
|
|
* data buffers. Buffers too large for a single descriptor will
|
843 |
|
|
* be spread across multiple descriptors.
|
844 |
|
|
*/
|
845 |
|
|
static void xmit_on_pipe(struct dbri *dbri, int pipe,
|
846 |
|
|
void * buffer, unsigned int len,
|
847 |
|
|
void (*callback)(void *, int), void * callback_arg)
|
848 |
|
|
{
|
849 |
|
|
volatile s32 *cmd;
|
850 |
|
|
unsigned long flags;
|
851 |
|
|
int td = 0;
|
852 |
|
|
int first_td = -1;
|
853 |
|
|
int last_td = -1;
|
854 |
|
|
__u32 dvma_buffer, dvma_buffer_base;
|
855 |
|
|
|
856 |
|
|
if (pipe < 0 || pipe > 15) {
|
857 |
|
|
printk("DBRI: xmit_on_pipe: Illegal pipe number\n");
|
858 |
|
|
return;
|
859 |
|
|
}
|
860 |
|
|
|
861 |
|
|
if (dbri->pipes[pipe].sdp == 0) {
|
862 |
|
|
printk("DBRI: xmit_on_pipe: Uninitialized pipe %d\n", pipe);
|
863 |
|
|
return;
|
864 |
|
|
}
|
865 |
|
|
|
866 |
|
|
if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
|
867 |
|
|
printk("DBRI: xmit_on_pipe: Called on receive pipe %d\n",
|
868 |
|
|
pipe);
|
869 |
|
|
return;
|
870 |
|
|
}
|
871 |
|
|
|
872 |
|
|
dvma_buffer_base = dvma_buffer = sbus_map_single(dbri->sdev, buffer, len,
|
873 |
|
|
SBUS_DMA_TODEVICE);
|
874 |
|
|
while (len > 0) {
|
875 |
|
|
int mylen;
|
876 |
|
|
|
877 |
|
|
for (; td < DBRI_NO_DESCS; td ++) {
|
878 |
|
|
if (! dbri->descs[td].inuse)
|
879 |
|
|
break;
|
880 |
|
|
}
|
881 |
|
|
if (td == DBRI_NO_DESCS) {
|
882 |
|
|
printk("DBRI: xmit_on_pipe: No descriptors\n");
|
883 |
|
|
break;
|
884 |
|
|
}
|
885 |
|
|
|
886 |
|
|
if (len > ((1 << 13) - 1)) {
|
887 |
|
|
mylen = (1 << 13) - 1;
|
888 |
|
|
} else {
|
889 |
|
|
mylen = len;
|
890 |
|
|
}
|
891 |
|
|
|
892 |
|
|
dbri->descs[td].inuse = 1;
|
893 |
|
|
dbri->descs[td].next = -1;
|
894 |
|
|
dbri->descs[td].buffer = NULL;
|
895 |
|
|
dbri->descs[td].output_callback = NULL;
|
896 |
|
|
dbri->descs[td].input_callback = NULL;
|
897 |
|
|
|
898 |
|
|
dbri->dma->desc[td].word1 = DBRI_TD_CNT(mylen);
|
899 |
|
|
dbri->dma->desc[td].ba = dvma_buffer;
|
900 |
|
|
dbri->dma->desc[td].nda = 0;
|
901 |
|
|
dbri->dma->desc[td].word4 = 0;
|
902 |
|
|
|
903 |
|
|
if (first_td == -1) {
|
904 |
|
|
first_td = td;
|
905 |
|
|
} else {
|
906 |
|
|
dbri->descs[last_td].next = td;
|
907 |
|
|
dbri->dma->desc[last_td].nda =
|
908 |
|
|
dbri->dma_dvma + dbri_dma_off(desc, td);
|
909 |
|
|
}
|
910 |
|
|
|
911 |
|
|
last_td = td;
|
912 |
|
|
dvma_buffer += mylen;
|
913 |
|
|
len -= mylen;
|
914 |
|
|
}
|
915 |
|
|
|
916 |
|
|
if (first_td == -1 || last_td == -1) {
|
917 |
|
|
sbus_unmap_single(dbri->sdev, dvma_buffer_base,
|
918 |
|
|
dvma_buffer - dvma_buffer_base + len,
|
919 |
|
|
SBUS_DMA_TODEVICE);
|
920 |
|
|
return;
|
921 |
|
|
}
|
922 |
|
|
|
923 |
|
|
dbri->dma->desc[last_td].word1 |= DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
|
924 |
|
|
|
925 |
|
|
dbri->descs[last_td].buffer = buffer;
|
926 |
|
|
dbri->descs[last_td].buffer_dvma = dvma_buffer_base;
|
927 |
|
|
dbri->descs[last_td].len = dvma_buffer - dvma_buffer_base + len;
|
928 |
|
|
dbri->descs[last_td].output_callback = callback;
|
929 |
|
|
dbri->descs[last_td].output_callback_arg = callback_arg;
|
930 |
|
|
|
931 |
|
|
for (td=first_td; td != -1; td = dbri->descs[td].next) {
|
932 |
|
|
dprintk(D_DESC, ("DBRI TD %d: %08x %08x %08x %08x\n",
|
933 |
|
|
td,
|
934 |
|
|
dbri->dma->desc[td].word1,
|
935 |
|
|
dbri->dma->desc[td].ba,
|
936 |
|
|
dbri->dma->desc[td].nda,
|
937 |
|
|
dbri->dma->desc[td].word4));
|
938 |
|
|
}
|
939 |
|
|
|
940 |
|
|
save_and_cli(flags);
|
941 |
|
|
|
942 |
|
|
if (pipe_active(dbri, pipe)) {
|
943 |
|
|
/* Pipe is already active - find last TD in use
|
944 |
|
|
* and link our first TD onto its end. Then issue
|
945 |
|
|
* a CDP command to let the DBRI know there's more data.
|
946 |
|
|
*/
|
947 |
|
|
last_td = dbri->pipes[pipe].desc;
|
948 |
|
|
while (dbri->descs[last_td].next != -1)
|
949 |
|
|
last_td = dbri->descs[last_td].next;
|
950 |
|
|
|
951 |
|
|
dbri->descs[last_td].next = first_td;
|
952 |
|
|
dbri->dma->desc[last_td].nda =
|
953 |
|
|
dbri->dma_dvma + dbri_dma_off(desc, first_td);
|
954 |
|
|
|
955 |
|
|
cmd = dbri_cmdlock(dbri);
|
956 |
|
|
*(cmd++) = DBRI_CMD(D_CDP, 0, pipe);
|
957 |
|
|
dbri_cmdsend(dbri,cmd);
|
958 |
|
|
} else {
|
959 |
|
|
/* Pipe isn't active - issue an SDP command to start
|
960 |
|
|
* our chain of TDs running.
|
961 |
|
|
*/
|
962 |
|
|
dbri->pipes[pipe].desc = first_td;
|
963 |
|
|
cmd = dbri_cmdlock(dbri);
|
964 |
|
|
*(cmd++) = DBRI_CMD(D_SDP, 0,
|
965 |
|
|
dbri->pipes[pipe].sdp
|
966 |
|
|
| D_SDP_P | D_SDP_EVERY | D_SDP_C);
|
967 |
|
|
*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
|
968 |
|
|
dbri_cmdsend(dbri, cmd);
|
969 |
|
|
}
|
970 |
|
|
|
971 |
|
|
restore_flags(flags);
|
972 |
|
|
}
|
973 |
|
|
|
974 |
|
|
static void recv_on_pipe(struct dbri *dbri, int pipe,
|
975 |
|
|
void * buffer, unsigned int len,
|
976 |
|
|
void (*callback)(void *, int, unsigned int),
|
977 |
|
|
void * callback_arg)
|
978 |
|
|
{
|
979 |
|
|
volatile s32 *cmd;
|
980 |
|
|
int first_rd = -1;
|
981 |
|
|
int last_rd = -1;
|
982 |
|
|
int rd;
|
983 |
|
|
__u32 bus_buffer, bus_buffer_base;
|
984 |
|
|
|
985 |
|
|
if (pipe < 0 || pipe > 15) {
|
986 |
|
|
printk("DBRI: recv_on_pipe: Illegal pipe number\n");
|
987 |
|
|
return;
|
988 |
|
|
}
|
989 |
|
|
|
990 |
|
|
if (dbri->pipes[pipe].sdp == 0) {
|
991 |
|
|
printk("DBRI: recv_on_pipe: Uninitialized pipe %d\n", pipe);
|
992 |
|
|
return;
|
993 |
|
|
}
|
994 |
|
|
|
995 |
|
|
if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
|
996 |
|
|
printk("DBRI: recv_on_pipe: Called on transmit pipe %d\n",
|
997 |
|
|
pipe);
|
998 |
|
|
return;
|
999 |
|
|
}
|
1000 |
|
|
|
1001 |
|
|
/* XXX Fix this XXX
|
1002 |
|
|
* Should be able to queue multiple buffers to receive on a pipe
|
1003 |
|
|
*/
|
1004 |
|
|
if (dbri->pipes[pipe].desc != -1) {
|
1005 |
|
|
printk("DBRI: recv_on_pipe: Called on active pipe %d\n", pipe);
|
1006 |
|
|
return;
|
1007 |
|
|
}
|
1008 |
|
|
|
1009 |
|
|
/* Make sure buffer size is multiple of four */
|
1010 |
|
|
len &= ~3;
|
1011 |
|
|
|
1012 |
|
|
bus_buffer_base = bus_buffer = sbus_map_single(dbri->sdev, buffer, len,
|
1013 |
|
|
SBUS_DMA_FROMDEVICE);
|
1014 |
|
|
|
1015 |
|
|
while (len > 0) {
|
1016 |
|
|
int rd, mylen;
|
1017 |
|
|
|
1018 |
|
|
if (len > ((1 << 13) - 4)) {
|
1019 |
|
|
mylen = (1 << 13) - 4;
|
1020 |
|
|
} else {
|
1021 |
|
|
mylen = len;
|
1022 |
|
|
}
|
1023 |
|
|
|
1024 |
|
|
for (rd = 0; rd < DBRI_NO_DESCS; rd ++) {
|
1025 |
|
|
if (! dbri->descs[rd].inuse)
|
1026 |
|
|
break;
|
1027 |
|
|
}
|
1028 |
|
|
if (rd == DBRI_NO_DESCS) {
|
1029 |
|
|
printk("DBRI recv_on_pipe: No descriptors\n");
|
1030 |
|
|
break;
|
1031 |
|
|
}
|
1032 |
|
|
|
1033 |
|
|
dbri->dma->desc[rd].word1 = 0;
|
1034 |
|
|
dbri->dma->desc[rd].ba = bus_buffer;
|
1035 |
|
|
dbri->dma->desc[rd].nda = 0;
|
1036 |
|
|
dbri->dma->desc[rd].word4 = DBRI_RD_B | DBRI_RD_BCNT(mylen);
|
1037 |
|
|
|
1038 |
|
|
dbri->descs[rd].buffer = NULL;
|
1039 |
|
|
dbri->descs[rd].len = 0;
|
1040 |
|
|
dbri->descs[rd].input_callback = NULL;
|
1041 |
|
|
dbri->descs[rd].output_callback = NULL;
|
1042 |
|
|
dbri->descs[rd].next = -1;
|
1043 |
|
|
dbri->descs[rd].inuse = 1;
|
1044 |
|
|
|
1045 |
|
|
if (first_rd == -1) first_rd = rd;
|
1046 |
|
|
if (last_rd != -1) {
|
1047 |
|
|
dbri->dma->desc[last_rd].nda =
|
1048 |
|
|
dbri->dma_dvma + dbri_dma_off(desc, rd);
|
1049 |
|
|
dbri->descs[last_rd].next = rd;
|
1050 |
|
|
}
|
1051 |
|
|
last_rd = rd;
|
1052 |
|
|
|
1053 |
|
|
bus_buffer += mylen;
|
1054 |
|
|
len -= mylen;
|
1055 |
|
|
}
|
1056 |
|
|
|
1057 |
|
|
if (last_rd == -1 || first_rd == -1) {
|
1058 |
|
|
sbus_unmap_single(dbri->sdev, bus_buffer_base,
|
1059 |
|
|
bus_buffer - bus_buffer_base + len,
|
1060 |
|
|
SBUS_DMA_FROMDEVICE);
|
1061 |
|
|
return;
|
1062 |
|
|
}
|
1063 |
|
|
|
1064 |
|
|
for (rd=first_rd; rd != -1; rd = dbri->descs[rd].next) {
|
1065 |
|
|
dprintk(D_DESC, ("DBRI RD %d: %08x %08x %08x %08x\n",
|
1066 |
|
|
rd,
|
1067 |
|
|
dbri->dma->desc[rd].word1,
|
1068 |
|
|
dbri->dma->desc[rd].ba,
|
1069 |
|
|
dbri->dma->desc[rd].nda,
|
1070 |
|
|
dbri->dma->desc[rd].word4));
|
1071 |
|
|
}
|
1072 |
|
|
|
1073 |
|
|
dbri->descs[last_rd].buffer = buffer;
|
1074 |
|
|
dbri->descs[last_rd].buffer_dvma = bus_buffer_base;
|
1075 |
|
|
dbri->descs[last_rd].len = bus_buffer - bus_buffer_base + len;
|
1076 |
|
|
dbri->descs[last_rd].input_callback = callback;
|
1077 |
|
|
dbri->descs[last_rd].input_callback_arg = callback_arg;
|
1078 |
|
|
|
1079 |
|
|
dbri->pipes[pipe].desc = first_rd;
|
1080 |
|
|
|
1081 |
|
|
cmd = dbri_cmdlock(dbri);
|
1082 |
|
|
|
1083 |
|
|
*(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[pipe].sdp | D_SDP_P | D_SDP_C);
|
1084 |
|
|
*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_rd);
|
1085 |
|
|
|
1086 |
|
|
dbri_cmdsend(dbri, cmd);
|
1087 |
|
|
}
|
1088 |
|
|
|
1089 |
|
|
|
1090 |
|
|
/*
|
1091 |
|
|
****************************************************************************
|
1092 |
|
|
************************** DBRI - CHI interface ****************************
|
1093 |
|
|
****************************************************************************
|
1094 |
|
|
|
1095 |
|
|
The CHI is a four-wire (clock, frame sync, data in, data out) time-division
|
1096 |
|
|
multiplexed serial interface which the DBRI can operate in either master
|
1097 |
|
|
(give clock/frame sync) or slave (take clock/frame sync) mode.
|
1098 |
|
|
|
1099 |
|
|
*/
|
1100 |
|
|
|
1101 |
|
|
enum master_or_slave { CHImaster, CHIslave };
|
1102 |
|
|
|
1103 |
|
|
static void reset_chi(struct dbri *dbri, enum master_or_slave master_or_slave,
|
1104 |
|
|
int bits_per_frame)
|
1105 |
|
|
{
|
1106 |
|
|
volatile s32 *cmd;
|
1107 |
|
|
int val;
|
1108 |
|
|
static int chi_initialized = 0;
|
1109 |
|
|
|
1110 |
|
|
if (!chi_initialized) {
|
1111 |
|
|
|
1112 |
|
|
cmd = dbri_cmdlock(dbri);
|
1113 |
|
|
|
1114 |
|
|
/* Set CHI Anchor: Pipe 16 */
|
1115 |
|
|
|
1116 |
|
|
val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
|
1117 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
1118 |
|
|
*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
|
1119 |
|
|
*(cmd++) = 0;
|
1120 |
|
|
|
1121 |
|
|
val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
|
1122 |
|
|
*(cmd++) = DBRI_CMD(D_DTS, 0, val);
|
1123 |
|
|
*(cmd++) = 0;
|
1124 |
|
|
*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
|
1125 |
|
|
|
1126 |
|
|
dbri->pipes[16].sdp = 1;
|
1127 |
|
|
dbri->pipes[16].nextpipe = 16;
|
1128 |
|
|
dbri->chi_in_pipe = 16;
|
1129 |
|
|
dbri->chi_out_pipe = 16;
|
1130 |
|
|
|
1131 |
|
|
#if 0
|
1132 |
|
|
chi_initialized ++;
|
1133 |
|
|
#endif
|
1134 |
|
|
} else {
|
1135 |
|
|
int pipe;
|
1136 |
|
|
|
1137 |
|
|
for (pipe = dbri->chi_in_pipe;
|
1138 |
|
|
pipe != 16;
|
1139 |
|
|
pipe = dbri->pipes[pipe].nextpipe) {
|
1140 |
|
|
unlink_time_slot(dbri, pipe, PIPEinput,
|
1141 |
|
|
16, dbri->pipes[pipe].nextpipe);
|
1142 |
|
|
}
|
1143 |
|
|
for (pipe = dbri->chi_out_pipe;
|
1144 |
|
|
pipe != 16;
|
1145 |
|
|
pipe = dbri->pipes[pipe].nextpipe) {
|
1146 |
|
|
unlink_time_slot(dbri, pipe, PIPEoutput,
|
1147 |
|
|
16, dbri->pipes[pipe].nextpipe);
|
1148 |
|
|
}
|
1149 |
|
|
|
1150 |
|
|
dbri->chi_in_pipe = 16;
|
1151 |
|
|
dbri->chi_out_pipe = 16;
|
1152 |
|
|
|
1153 |
|
|
cmd = dbri_cmdlock(dbri);
|
1154 |
|
|
}
|
1155 |
|
|
|
1156 |
|
|
if (master_or_slave == CHIslave) {
|
1157 |
|
|
/* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
|
1158 |
|
|
*
|
1159 |
|
|
* CHICM = 0 (slave mode, 8 kHz frame rate)
|
1160 |
|
|
* IR = give immediate CHI status interrupt
|
1161 |
|
|
* EN = give CHI status interrupt upon change
|
1162 |
|
|
*/
|
1163 |
|
|
*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
|
1164 |
|
|
} else {
|
1165 |
|
|
/* Setup DBRI for CHI Master - generate clock, FS
|
1166 |
|
|
*
|
1167 |
|
|
* BPF = bits per 8 kHz frame
|
1168 |
|
|
* 12.288 MHz / CHICM_divisor = clock rate
|
1169 |
|
|
* FD = 1 - drive CHIFS on rising edge of CHICK
|
1170 |
|
|
*/
|
1171 |
|
|
int clockrate = bits_per_frame * 8;
|
1172 |
|
|
int divisor = 12288 / clockrate;
|
1173 |
|
|
|
1174 |
|
|
if (divisor > 255 || divisor * clockrate != 12288)
|
1175 |
|
|
printk("DBRI: illegal bits_per_frame in setup_chi\n");
|
1176 |
|
|
|
1177 |
|
|
*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
|
1178 |
|
|
| D_CHI_BPF(bits_per_frame));
|
1179 |
|
|
}
|
1180 |
|
|
|
1181 |
|
|
dbri->chi_bpf = bits_per_frame;
|
1182 |
|
|
|
1183 |
|
|
/* CHI Data Mode
|
1184 |
|
|
*
|
1185 |
|
|
* RCE = 0 - receive on falling edge of CHICK
|
1186 |
|
|
* XCE = 1 - transmit on rising edge of CHICK
|
1187 |
|
|
* XEN = 1 - enable transmitter
|
1188 |
|
|
* REN = 1 - enable receiver
|
1189 |
|
|
*/
|
1190 |
|
|
|
1191 |
|
|
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
|
1192 |
|
|
*(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE|D_CDM_XEN|D_CDM_REN);
|
1193 |
|
|
|
1194 |
|
|
dbri_cmdsend(dbri, cmd);
|
1195 |
|
|
}
|
1196 |
|
|
|
1197 |
|
|
/*
|
1198 |
|
|
****************************************************************************
|
1199 |
|
|
*********************** CS4215 audio codec management **********************
|
1200 |
|
|
****************************************************************************
|
1201 |
|
|
|
1202 |
|
|
In the standard SPARC audio configuration, the CS4215 codec is attached
|
1203 |
|
|
to the DBRI via the CHI interface and few of the DBRI's PIO pins.
|
1204 |
|
|
|
1205 |
|
|
*/
|
1206 |
|
|
static void mmcodec_default(struct cs4215 *mm)
|
1207 |
|
|
{
|
1208 |
|
|
/*
|
1209 |
|
|
* No action, memory resetting only.
|
1210 |
|
|
*
|
1211 |
|
|
* Data Time Slot 5-8
|
1212 |
|
|
* Speaker,Line and Headphone enable. Gain set to the half.
|
1213 |
|
|
* Input is mike.
|
1214 |
|
|
*/
|
1215 |
|
|
mm->data[0] = CS4215_LO(0x20) | CS4215_HE|CS4215_LE;
|
1216 |
|
|
mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
|
1217 |
|
|
mm->data[2] = CS4215_LG( 0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
|
1218 |
|
|
mm->data[3] = CS4215_RG( 0x8) | CS4215_MA(0xf);
|
1219 |
|
|
|
1220 |
|
|
/*
|
1221 |
|
|
* Control Time Slot 1-4
|
1222 |
|
|
* 0: Default I/O voltage scale
|
1223 |
|
|
* 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
|
1224 |
|
|
* 2: Serial enable, CHI master, 128 bits per frame, clock 1
|
1225 |
|
|
* 3: Tests disabled
|
1226 |
|
|
*/
|
1227 |
|
|
mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
|
1228 |
|
|
mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
|
1229 |
|
|
mm->ctrl[2] = CS4215_XCLK |
|
1230 |
|
|
CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
|
1231 |
|
|
mm->ctrl[3] = 0;
|
1232 |
|
|
}
|
1233 |
|
|
|
1234 |
|
|
static void mmcodec_setup_pipes(struct dbri *dbri)
|
1235 |
|
|
{
|
1236 |
|
|
/*
|
1237 |
|
|
* Data mode:
|
1238 |
|
|
* Pipe 4: Send timeslots 1-4 (audio data)
|
1239 |
|
|
* Pipe 20: Send timeslots 5-8 (part of ctrl data)
|
1240 |
|
|
* Pipe 6: Receive timeslots 1-4 (audio data)
|
1241 |
|
|
* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
|
1242 |
|
|
* interrupt, and the rest of the data (slot 5 and 8) is
|
1243 |
|
|
* not relevant for us (only for doublechecking).
|
1244 |
|
|
*
|
1245 |
|
|
* Control mode:
|
1246 |
|
|
* Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
|
1247 |
|
|
* Pipe 18: Receive timeslot 1 (clb).
|
1248 |
|
|
* Pipe 19: Receive timeslot 7 (version).
|
1249 |
|
|
*/
|
1250 |
|
|
|
1251 |
|
|
setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
|
1252 |
|
|
setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
|
1253 |
|
|
setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
|
1254 |
|
|
setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
|
1255 |
|
|
|
1256 |
|
|
setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
|
1257 |
|
|
setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
|
1258 |
|
|
setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
|
1259 |
|
|
|
1260 |
|
|
dbri->mm.status = 0;
|
1261 |
|
|
|
1262 |
|
|
recv_fixed(dbri, 18, & dbri->mm.status);
|
1263 |
|
|
recv_fixed(dbri, 19, & dbri->mm.version);
|
1264 |
|
|
}
|
1265 |
|
|
|
1266 |
|
|
static void mmcodec_setgain(struct dbri *dbri, int muted)
|
1267 |
|
|
{
|
1268 |
|
|
if (muted || dbri->perchip_info.output_muted) {
|
1269 |
|
|
dbri->mm.data[0] = 63;
|
1270 |
|
|
dbri->mm.data[1] = 63;
|
1271 |
|
|
} else {
|
1272 |
|
|
int left_gain = (dbri->perchip_info.play.gain / 4) % 64;
|
1273 |
|
|
int right_gain = (dbri->perchip_info.play.gain / 4) % 64;
|
1274 |
|
|
int outport = dbri->perchip_info.play.port;
|
1275 |
|
|
|
1276 |
|
|
if (dbri->perchip_info.play.balance < AUDIO_MID_BALANCE) {
|
1277 |
|
|
right_gain *= dbri->perchip_info.play.balance;
|
1278 |
|
|
right_gain /= AUDIO_MID_BALANCE;
|
1279 |
|
|
} else {
|
1280 |
|
|
left_gain *= AUDIO_RIGHT_BALANCE
|
1281 |
|
|
- dbri->perchip_info.play.balance;
|
1282 |
|
|
left_gain /= AUDIO_MID_BALANCE;
|
1283 |
|
|
}
|
1284 |
|
|
|
1285 |
|
|
dprintk(D_MM, ("DBRI: Setting codec gain left: %d right: %d\n",
|
1286 |
|
|
left_gain, right_gain));
|
1287 |
|
|
|
1288 |
|
|
dbri->mm.data[0] = (63 - left_gain);
|
1289 |
|
|
if (outport & AUDIO_HEADPHONE) dbri->mm.data[0] |= CS4215_HE;
|
1290 |
|
|
if (outport & AUDIO_LINE_OUT) dbri->mm.data[0] |= CS4215_LE;
|
1291 |
|
|
dbri->mm.data[1] = (63 - right_gain);
|
1292 |
|
|
if (outport & AUDIO_SPEAKER) dbri->mm.data[1] |= CS4215_SE;
|
1293 |
|
|
}
|
1294 |
|
|
|
1295 |
|
|
xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
|
1296 |
|
|
}
|
1297 |
|
|
|
1298 |
|
|
static void mmcodec_init_data(struct dbri *dbri)
|
1299 |
|
|
{
|
1300 |
|
|
int data_width;
|
1301 |
|
|
u32 tmp;
|
1302 |
|
|
|
1303 |
|
|
/*
|
1304 |
|
|
* Data mode:
|
1305 |
|
|
* Pipe 4: Send timeslots 1-4 (audio data)
|
1306 |
|
|
* Pipe 20: Send timeslots 5-8 (part of ctrl data)
|
1307 |
|
|
* Pipe 6: Receive timeslots 1-4 (audio data)
|
1308 |
|
|
* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
|
1309 |
|
|
* interrupt, and the rest of the data (slot 5 and 8) is
|
1310 |
|
|
* not relevant for us (only for doublechecking).
|
1311 |
|
|
*
|
1312 |
|
|
* Just like in control mode, the time slots are all offset by eight
|
1313 |
|
|
* bits. The CS4215, it seems, observes TSIN (the delayed signal)
|
1314 |
|
|
* even if it's the CHI master. Don't ask me...
|
1315 |
|
|
*/
|
1316 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
1317 |
|
|
tmp &= ~(D_C); /* Disable CHI */
|
1318 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
1319 |
|
|
|
1320 |
|
|
/* Switch CS4215 to data mode - set PIO3 to 1 */
|
1321 |
|
|
sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
|
1322 |
|
|
(dbri->mm.onboard ? D_PIO0 : D_PIO2),
|
1323 |
|
|
dbri->regs + REG2);
|
1324 |
|
|
|
1325 |
|
|
reset_chi(dbri, CHIslave, 128);
|
1326 |
|
|
|
1327 |
|
|
/* Note: this next doesn't work for 8-bit stereo, because the two
|
1328 |
|
|
* channels would be on timeslots 1 and 3, with 2 and 4 idle.
|
1329 |
|
|
* (See CS4215 datasheet Fig 15)
|
1330 |
|
|
*
|
1331 |
|
|
* DBRI non-contiguous mode would be required to make this work.
|
1332 |
|
|
*/
|
1333 |
|
|
|
1334 |
|
|
data_width = dbri->perchip_info.play.channels
|
1335 |
|
|
* dbri->perchip_info.play.precision;
|
1336 |
|
|
|
1337 |
|
|
link_time_slot(dbri, 20, PIPEoutput, 16,
|
1338 |
|
|
32, dbri->mm.offset + 32);
|
1339 |
|
|
link_time_slot(dbri, 4, PIPEoutput, 16,
|
1340 |
|
|
data_width, dbri->mm.offset);
|
1341 |
|
|
link_time_slot(dbri, 6, PIPEinput, 16,
|
1342 |
|
|
data_width, dbri->mm.offset);
|
1343 |
|
|
link_time_slot(dbri, 21, PIPEinput, 16,
|
1344 |
|
|
16, dbri->mm.offset + 40);
|
1345 |
|
|
|
1346 |
|
|
mmcodec_setgain(dbri, 0);
|
1347 |
|
|
|
1348 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
1349 |
|
|
tmp |= D_C; /* Enable CHI */
|
1350 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
1351 |
|
|
}
|
1352 |
|
|
|
1353 |
|
|
/*
|
1354 |
|
|
* Send the control information (i.e. audio format)
|
1355 |
|
|
*/
|
1356 |
|
|
static int mmcodec_setctrl(struct dbri *dbri)
|
1357 |
|
|
{
|
1358 |
|
|
int i, val;
|
1359 |
|
|
u32 tmp;
|
1360 |
|
|
|
1361 |
|
|
/* XXX - let the CPU do something useful during these delays */
|
1362 |
|
|
|
1363 |
|
|
/* Temporarily mute outputs, and wait 1/8000 sec (125 us)
|
1364 |
|
|
* to make sure this takes. This avoids clicking noises.
|
1365 |
|
|
*/
|
1366 |
|
|
|
1367 |
|
|
mmcodec_setgain(dbri, 1);
|
1368 |
|
|
udelay(125);
|
1369 |
|
|
|
1370 |
|
|
/*
|
1371 |
|
|
* Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
|
1372 |
|
|
* 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
|
1373 |
|
|
*/
|
1374 |
|
|
val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
|
1375 |
|
|
sbus_writel(val, dbri->regs + REG2);
|
1376 |
|
|
udelay(34);
|
1377 |
|
|
|
1378 |
|
|
/* In Control mode, the CS4215 is a slave device, so the DBRI must
|
1379 |
|
|
* operate as CHI master, supplying clocking and frame synchronization.
|
1380 |
|
|
*
|
1381 |
|
|
* In Data mode, however, the CS4215 must be CHI master to insure
|
1382 |
|
|
* that its data stream is synchronous with its codec.
|
1383 |
|
|
*
|
1384 |
|
|
* The upshot of all this? We start by putting the DBRI into master
|
1385 |
|
|
* mode, program the CS4215 in Control mode, then switch the CS4215
|
1386 |
|
|
* into Data mode and put the DBRI into slave mode. Various timing
|
1387 |
|
|
* requirements must be observed along the way.
|
1388 |
|
|
*
|
1389 |
|
|
* Oh, and one more thing, on a SPARCStation 20 (and maybe
|
1390 |
|
|
* others?), the addressing of the CS4215's time slots is
|
1391 |
|
|
* offset by eight bits, so we add eight to all the "cycle"
|
1392 |
|
|
* values in the Define Time Slot (DTS) commands. This is
|
1393 |
|
|
* done in hardware by a TI 248 that delays the DBRI->4215
|
1394 |
|
|
* frame sync signal by eight clock cycles. Anybody know why?
|
1395 |
|
|
*/
|
1396 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
1397 |
|
|
tmp &= ~D_C; /* Disable CHI */
|
1398 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
1399 |
|
|
|
1400 |
|
|
reset_chi(dbri, CHImaster, 128);
|
1401 |
|
|
|
1402 |
|
|
/*
|
1403 |
|
|
* Control mode:
|
1404 |
|
|
* Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
|
1405 |
|
|
* Pipe 18: Receive timeslot 1 (clb).
|
1406 |
|
|
* Pipe 19: Receive timeslot 7 (version).
|
1407 |
|
|
*/
|
1408 |
|
|
|
1409 |
|
|
link_time_slot(dbri, 17, PIPEoutput, 16,
|
1410 |
|
|
32, dbri->mm.offset);
|
1411 |
|
|
link_time_slot(dbri, 18, PIPEinput, 16,
|
1412 |
|
|
8, dbri->mm.offset);
|
1413 |
|
|
link_time_slot(dbri, 19, PIPEinput, 16,
|
1414 |
|
|
8, dbri->mm.offset + 48);
|
1415 |
|
|
|
1416 |
|
|
/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
|
1417 |
|
|
|
1418 |
|
|
dbri->mm.ctrl[0] &= ~CS4215_CLB;
|
1419 |
|
|
xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
|
1420 |
|
|
|
1421 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
1422 |
|
|
tmp |= D_C; /* Enable CHI */
|
1423 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
1424 |
|
|
|
1425 |
|
|
i = 64;
|
1426 |
|
|
while (((dbri->mm.status & 0xe4) != 0x20) && --i)
|
1427 |
|
|
udelay(125);
|
1428 |
|
|
if (i == 0) {
|
1429 |
|
|
dprintk(D_MM, ("DBRI: CS4215 didn't respond to CLB (0x%02x)\n",
|
1430 |
|
|
dbri->mm.status));
|
1431 |
|
|
return -1;
|
1432 |
|
|
}
|
1433 |
|
|
|
1434 |
|
|
/* Terminate CS4215 control mode - data sheet says
|
1435 |
|
|
* "Set CLB=1 and send two more frames of valid control info"
|
1436 |
|
|
*/
|
1437 |
|
|
dbri->mm.ctrl[0] |= CS4215_CLB;
|
1438 |
|
|
xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
|
1439 |
|
|
|
1440 |
|
|
/* Two frames of control info @ 8kHz frame rate = 250 us delay */
|
1441 |
|
|
udelay(250);
|
1442 |
|
|
|
1443 |
|
|
mmcodec_setgain(dbri, 0);
|
1444 |
|
|
|
1445 |
|
|
return 0;
|
1446 |
|
|
}
|
1447 |
|
|
|
1448 |
|
|
static int mmcodec_init(struct sparcaudio_driver *drv)
|
1449 |
|
|
{
|
1450 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1451 |
|
|
u32 reg2 = sbus_readl(dbri->regs + REG2);
|
1452 |
|
|
|
1453 |
|
|
/* Look for the cs4215 chips */
|
1454 |
|
|
if(reg2 & D_PIO2) {
|
1455 |
|
|
dprintk(D_MM, ("DBRI: Onboard CS4215 detected\n"));
|
1456 |
|
|
dbri->mm.onboard = 1;
|
1457 |
|
|
}
|
1458 |
|
|
if(reg2 & D_PIO0) {
|
1459 |
|
|
dprintk(D_MM, ("DBRI: Speakerbox detected\n"));
|
1460 |
|
|
dbri->mm.onboard = 0;
|
1461 |
|
|
}
|
1462 |
|
|
|
1463 |
|
|
|
1464 |
|
|
/* Using the Speakerbox, if both are attached. */
|
1465 |
|
|
if((reg2 & D_PIO2) && (reg2 & D_PIO0)) {
|
1466 |
|
|
printk("DBRI: Using speakerbox / ignoring onboard mmcodec.\n");
|
1467 |
|
|
sbus_writel(D_ENPIO2, dbri->regs + REG2);
|
1468 |
|
|
dbri->mm.onboard = 0;
|
1469 |
|
|
}
|
1470 |
|
|
|
1471 |
|
|
if(!(reg2 & (D_PIO0|D_PIO2))) {
|
1472 |
|
|
printk("DBRI: no mmcodec found.\n");
|
1473 |
|
|
return -EIO;
|
1474 |
|
|
}
|
1475 |
|
|
|
1476 |
|
|
|
1477 |
|
|
mmcodec_setup_pipes(dbri);
|
1478 |
|
|
|
1479 |
|
|
mmcodec_default(&dbri->mm);
|
1480 |
|
|
|
1481 |
|
|
dbri->mm.version = 0xff;
|
1482 |
|
|
dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
|
1483 |
|
|
if (mmcodec_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
|
1484 |
|
|
dprintk(D_MM, ("DBRI: CS4215 failed probe at offset %d\n",
|
1485 |
|
|
dbri->mm.offset));
|
1486 |
|
|
return -EIO;
|
1487 |
|
|
}
|
1488 |
|
|
|
1489 |
|
|
dprintk(D_MM, ("DBRI: Found CS4215 at offset %d\n", dbri->mm.offset));
|
1490 |
|
|
|
1491 |
|
|
dbri->perchip_info.play.channels = 1;
|
1492 |
|
|
dbri->perchip_info.play.precision = 8;
|
1493 |
|
|
dbri->perchip_info.play.gain = (AUDIO_MAX_GAIN * 7 / 10); /* 70% */
|
1494 |
|
|
dbri->perchip_info.play.balance = AUDIO_MID_BALANCE;
|
1495 |
|
|
dbri->perchip_info.play.port = dbri->perchip_info.play.avail_ports =
|
1496 |
|
|
AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
|
1497 |
|
|
dbri->perchip_info.record.port = AUDIO_MICROPHONE;
|
1498 |
|
|
dbri->perchip_info.record.avail_ports =
|
1499 |
|
|
AUDIO_MICROPHONE | AUDIO_LINE_IN;
|
1500 |
|
|
|
1501 |
|
|
mmcodec_init_data(dbri);
|
1502 |
|
|
|
1503 |
|
|
return 0;
|
1504 |
|
|
}
|
1505 |
|
|
|
1506 |
|
|
|
1507 |
|
|
/*
|
1508 |
|
|
****************************************************************************
|
1509 |
|
|
******************** Interface with sparcaudio midlevel ********************
|
1510 |
|
|
****************************************************************************
|
1511 |
|
|
|
1512 |
|
|
The sparcaudio midlevel is contained in the file audio.c. It interfaces
|
1513 |
|
|
to the user process and performs buffering, intercepts SunOS-style ioctl's,
|
1514 |
|
|
etc. It interfaces to a abstract audio device via a struct sparcaudio_driver.
|
1515 |
|
|
This code presents such an interface for the DBRI with an attached CS4215.
|
1516 |
|
|
All our routines are defined, and then comes our struct sparcaudio_driver.
|
1517 |
|
|
|
1518 |
|
|
*/
|
1519 |
|
|
|
1520 |
|
|
/******************* sparcaudio midlevel - audio output *******************/
|
1521 |
|
|
static void dbri_audio_output_callback(void * callback_arg, int status)
|
1522 |
|
|
{
|
1523 |
|
|
struct sparcaudio_driver *drv = callback_arg;
|
1524 |
|
|
|
1525 |
|
|
if (status != -1)
|
1526 |
|
|
sparcaudio_output_done(drv, 1);
|
1527 |
|
|
}
|
1528 |
|
|
|
1529 |
|
|
static void dbri_start_output(struct sparcaudio_driver *drv,
|
1530 |
|
|
__u8 * buffer, unsigned long count)
|
1531 |
|
|
{
|
1532 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1533 |
|
|
|
1534 |
|
|
dprintk(D_USR, ("DBRI: start audio output buf=%p/%ld\n",
|
1535 |
|
|
buffer, count));
|
1536 |
|
|
|
1537 |
|
|
/* Pipe 4 is audio transmit */
|
1538 |
|
|
xmit_on_pipe(dbri, 4, buffer, count,
|
1539 |
|
|
&dbri_audio_output_callback, drv);
|
1540 |
|
|
|
1541 |
|
|
#if 0
|
1542 |
|
|
/* Notify midlevel that we're a DMA-capable driver that
|
1543 |
|
|
* can accept another buffer immediately. We should probably
|
1544 |
|
|
* check that we've got enough resources (i.e, descriptors)
|
1545 |
|
|
* available before doing this, but the default midlevel
|
1546 |
|
|
* settings only buffer 64KB, which we can handle with 16
|
1547 |
|
|
* of our DBRI_NO_DESCS (64) descriptors.
|
1548 |
|
|
*
|
1549 |
|
|
* This code is #ifdef'ed out because it's caused me more
|
1550 |
|
|
* problems than it solved. It'd be nice to provide the
|
1551 |
|
|
* DBRI with a chain of buffers, but the midlevel code is
|
1552 |
|
|
* so tricky that I really don't want to deal with it.
|
1553 |
|
|
*/
|
1554 |
|
|
|
1555 |
|
|
sparcaudio_output_done(drv, 2);
|
1556 |
|
|
#endif
|
1557 |
|
|
}
|
1558 |
|
|
|
1559 |
|
|
static void dbri_stop_output(struct sparcaudio_driver *drv)
|
1560 |
|
|
{
|
1561 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1562 |
|
|
|
1563 |
|
|
reset_pipe(dbri, 4);
|
1564 |
|
|
}
|
1565 |
|
|
|
1566 |
|
|
/******************* sparcaudio midlevel - audio input ********************/
|
1567 |
|
|
|
1568 |
|
|
static void dbri_audio_input_callback(void * callback_arg, int status,
|
1569 |
|
|
unsigned int len)
|
1570 |
|
|
{
|
1571 |
|
|
struct sparcaudio_driver * drv =
|
1572 |
|
|
(struct sparcaudio_driver *) callback_arg;
|
1573 |
|
|
|
1574 |
|
|
if (status != -1)
|
1575 |
|
|
sparcaudio_input_done(drv, 3);
|
1576 |
|
|
}
|
1577 |
|
|
|
1578 |
|
|
static void dbri_start_input(struct sparcaudio_driver *drv,
|
1579 |
|
|
__u8 * buffer, unsigned long len)
|
1580 |
|
|
{
|
1581 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1582 |
|
|
|
1583 |
|
|
/* Pipe 6 is audio receive */
|
1584 |
|
|
recv_on_pipe(dbri, 6, buffer, len,
|
1585 |
|
|
&dbri_audio_input_callback, (void *)drv);
|
1586 |
|
|
dprintk(D_USR, ("DBRI: start audio input buf=%p/%ld\n",
|
1587 |
|
|
buffer, len));
|
1588 |
|
|
}
|
1589 |
|
|
|
1590 |
|
|
static void dbri_stop_input(struct sparcaudio_driver *drv)
|
1591 |
|
|
{
|
1592 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1593 |
|
|
|
1594 |
|
|
reset_pipe(dbri, 6);
|
1595 |
|
|
}
|
1596 |
|
|
|
1597 |
|
|
/******************* sparcaudio midlevel - volume & balance ***************/
|
1598 |
|
|
|
1599 |
|
|
static int dbri_set_output_volume(struct sparcaudio_driver *drv, int volume)
|
1600 |
|
|
{
|
1601 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1602 |
|
|
|
1603 |
|
|
dbri->perchip_info.play.gain = volume;
|
1604 |
|
|
mmcodec_setgain(dbri, 0);
|
1605 |
|
|
|
1606 |
|
|
return 0;
|
1607 |
|
|
}
|
1608 |
|
|
|
1609 |
|
|
static int dbri_get_output_volume(struct sparcaudio_driver *drv)
|
1610 |
|
|
{
|
1611 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1612 |
|
|
|
1613 |
|
|
return dbri->perchip_info.play.gain;
|
1614 |
|
|
}
|
1615 |
|
|
|
1616 |
|
|
static int dbri_set_input_volume(struct sparcaudio_driver *drv, int volume)
|
1617 |
|
|
{
|
1618 |
|
|
return 0;
|
1619 |
|
|
}
|
1620 |
|
|
|
1621 |
|
|
static int dbri_get_input_volume(struct sparcaudio_driver *drv)
|
1622 |
|
|
{
|
1623 |
|
|
return 0;
|
1624 |
|
|
}
|
1625 |
|
|
|
1626 |
|
|
static int dbri_set_monitor_volume(struct sparcaudio_driver *drv, int volume)
|
1627 |
|
|
{
|
1628 |
|
|
return 0;
|
1629 |
|
|
}
|
1630 |
|
|
|
1631 |
|
|
static int dbri_get_monitor_volume(struct sparcaudio_driver *drv)
|
1632 |
|
|
{
|
1633 |
|
|
return 0;
|
1634 |
|
|
}
|
1635 |
|
|
|
1636 |
|
|
static int dbri_set_output_balance(struct sparcaudio_driver *drv, int balance)
|
1637 |
|
|
{
|
1638 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1639 |
|
|
|
1640 |
|
|
dbri->perchip_info.play.balance = balance;
|
1641 |
|
|
mmcodec_setgain(dbri, 0);
|
1642 |
|
|
|
1643 |
|
|
return 0;
|
1644 |
|
|
}
|
1645 |
|
|
|
1646 |
|
|
static int dbri_get_output_balance(struct sparcaudio_driver *drv)
|
1647 |
|
|
{
|
1648 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1649 |
|
|
|
1650 |
|
|
return dbri->perchip_info.play.balance;
|
1651 |
|
|
}
|
1652 |
|
|
|
1653 |
|
|
static int dbri_set_input_balance(struct sparcaudio_driver *drv, int balance)
|
1654 |
|
|
{
|
1655 |
|
|
return 0;
|
1656 |
|
|
}
|
1657 |
|
|
|
1658 |
|
|
static int dbri_get_input_balance(struct sparcaudio_driver *drv)
|
1659 |
|
|
{
|
1660 |
|
|
return 0;
|
1661 |
|
|
}
|
1662 |
|
|
|
1663 |
|
|
static int dbri_set_output_muted(struct sparcaudio_driver *drv, int mute)
|
1664 |
|
|
{
|
1665 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1666 |
|
|
|
1667 |
|
|
dbri->perchip_info.output_muted = mute;
|
1668 |
|
|
|
1669 |
|
|
return 0;
|
1670 |
|
|
}
|
1671 |
|
|
|
1672 |
|
|
static int dbri_get_output_muted(struct sparcaudio_driver *drv)
|
1673 |
|
|
{
|
1674 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1675 |
|
|
|
1676 |
|
|
return dbri->perchip_info.output_muted;
|
1677 |
|
|
}
|
1678 |
|
|
|
1679 |
|
|
/******************* sparcaudio midlevel - encoding format ****************/
|
1680 |
|
|
|
1681 |
|
|
static int dbri_set_output_channels(struct sparcaudio_driver *drv, int chan)
|
1682 |
|
|
{
|
1683 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1684 |
|
|
|
1685 |
|
|
switch (chan) {
|
1686 |
|
|
case 0:
|
1687 |
|
|
return 0;
|
1688 |
|
|
case 1:
|
1689 |
|
|
dbri->mm.ctrl[1] &= ~CS4215_DFR_STEREO;
|
1690 |
|
|
break;
|
1691 |
|
|
case 2:
|
1692 |
|
|
dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
|
1693 |
|
|
break;
|
1694 |
|
|
default:
|
1695 |
|
|
return -1;
|
1696 |
|
|
}
|
1697 |
|
|
|
1698 |
|
|
dbri->perchip_info.play.channels = chan;
|
1699 |
|
|
mmcodec_setctrl(dbri);
|
1700 |
|
|
mmcodec_init_data(dbri);
|
1701 |
|
|
return 0;
|
1702 |
|
|
}
|
1703 |
|
|
|
1704 |
|
|
static int dbri_get_output_channels(struct sparcaudio_driver *drv)
|
1705 |
|
|
{
|
1706 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1707 |
|
|
|
1708 |
|
|
return dbri->perchip_info.play.channels;
|
1709 |
|
|
}
|
1710 |
|
|
|
1711 |
|
|
static int dbri_set_input_channels(struct sparcaudio_driver *drv, int chan)
|
1712 |
|
|
{
|
1713 |
|
|
return dbri_set_output_channels(drv, chan);
|
1714 |
|
|
}
|
1715 |
|
|
|
1716 |
|
|
static int dbri_get_input_channels(struct sparcaudio_driver *drv)
|
1717 |
|
|
{
|
1718 |
|
|
return dbri_get_output_channels(drv);
|
1719 |
|
|
}
|
1720 |
|
|
|
1721 |
|
|
static int dbri_set_output_precision(struct sparcaudio_driver *drv, int prec)
|
1722 |
|
|
{
|
1723 |
|
|
return 0;
|
1724 |
|
|
}
|
1725 |
|
|
|
1726 |
|
|
static int dbri_get_output_precision(struct sparcaudio_driver *drv)
|
1727 |
|
|
{
|
1728 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1729 |
|
|
|
1730 |
|
|
return dbri->perchip_info.play.precision;
|
1731 |
|
|
}
|
1732 |
|
|
|
1733 |
|
|
static int dbri_set_input_precision(struct sparcaudio_driver *drv, int prec)
|
1734 |
|
|
{
|
1735 |
|
|
return 0;
|
1736 |
|
|
}
|
1737 |
|
|
|
1738 |
|
|
static int dbri_get_input_precision(struct sparcaudio_driver *drv)
|
1739 |
|
|
{
|
1740 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1741 |
|
|
|
1742 |
|
|
return dbri->perchip_info.play.precision;
|
1743 |
|
|
}
|
1744 |
|
|
|
1745 |
|
|
static int dbri_set_output_encoding(struct sparcaudio_driver *drv, int enc)
|
1746 |
|
|
{
|
1747 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1748 |
|
|
|
1749 |
|
|
/* For ULAW and ALAW, audio.c enforces precision = 8,
|
1750 |
|
|
* for LINEAR, precision must be 16
|
1751 |
|
|
*/
|
1752 |
|
|
|
1753 |
|
|
switch (enc) {
|
1754 |
|
|
case AUDIO_ENCODING_NONE:
|
1755 |
|
|
return 0;
|
1756 |
|
|
case AUDIO_ENCODING_ULAW:
|
1757 |
|
|
dbri->mm.ctrl[1] &= ~3;
|
1758 |
|
|
dbri->mm.ctrl[1] |= CS4215_DFR_ULAW;
|
1759 |
|
|
dbri->perchip_info.play.encoding = enc;
|
1760 |
|
|
dbri->perchip_info.play.precision = 8;
|
1761 |
|
|
break;
|
1762 |
|
|
case AUDIO_ENCODING_ALAW:
|
1763 |
|
|
dbri->mm.ctrl[1] &= ~3;
|
1764 |
|
|
dbri->mm.ctrl[1] |= CS4215_DFR_ALAW;
|
1765 |
|
|
dbri->perchip_info.play.encoding = enc;
|
1766 |
|
|
dbri->perchip_info.play.precision = 8;
|
1767 |
|
|
break;
|
1768 |
|
|
case AUDIO_ENCODING_LINEAR:
|
1769 |
|
|
dbri->mm.ctrl[1] &= ~3;
|
1770 |
|
|
dbri->mm.ctrl[1] |= CS4215_DFR_LINEAR16;
|
1771 |
|
|
dbri->perchip_info.play.encoding = enc;
|
1772 |
|
|
dbri->perchip_info.play.precision = 16;
|
1773 |
|
|
break;
|
1774 |
|
|
default:
|
1775 |
|
|
return -1;
|
1776 |
|
|
};
|
1777 |
|
|
|
1778 |
|
|
mmcodec_setctrl(dbri);
|
1779 |
|
|
mmcodec_init_data(dbri);
|
1780 |
|
|
return 0;
|
1781 |
|
|
}
|
1782 |
|
|
|
1783 |
|
|
static int dbri_get_output_encoding(struct sparcaudio_driver *drv)
|
1784 |
|
|
{
|
1785 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1786 |
|
|
|
1787 |
|
|
return dbri->perchip_info.play.encoding;
|
1788 |
|
|
}
|
1789 |
|
|
|
1790 |
|
|
static int dbri_set_input_encoding(struct sparcaudio_driver *drv, int enc)
|
1791 |
|
|
{
|
1792 |
|
|
return dbri_set_output_encoding(drv, enc);
|
1793 |
|
|
}
|
1794 |
|
|
|
1795 |
|
|
static int dbri_get_input_encoding(struct sparcaudio_driver *drv)
|
1796 |
|
|
{
|
1797 |
|
|
return dbri_get_output_encoding(drv);
|
1798 |
|
|
}
|
1799 |
|
|
|
1800 |
|
|
static int dbri_set_output_rate(struct sparcaudio_driver *drv, int rate)
|
1801 |
|
|
{
|
1802 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1803 |
|
|
int i;
|
1804 |
|
|
|
1805 |
|
|
if (rate == 0)
|
1806 |
|
|
return 0;
|
1807 |
|
|
|
1808 |
|
|
for (i=0; CS4215_FREQ[i].freq; i++) {
|
1809 |
|
|
if (CS4215_FREQ[i].freq == rate)
|
1810 |
|
|
break;
|
1811 |
|
|
}
|
1812 |
|
|
|
1813 |
|
|
if (CS4215_FREQ[i].freq == 0)
|
1814 |
|
|
return -1;
|
1815 |
|
|
|
1816 |
|
|
dbri->mm.ctrl[1] &= ~ 0x38;
|
1817 |
|
|
dbri->mm.ctrl[1] |= CS4215_FREQ[i].csval;
|
1818 |
|
|
dbri->mm.ctrl[2] &= ~ 0x70;
|
1819 |
|
|
dbri->mm.ctrl[2] |= CS4215_FREQ[i].xtal;
|
1820 |
|
|
|
1821 |
|
|
dbri->perchip_info.play.sample_rate = rate;
|
1822 |
|
|
|
1823 |
|
|
mmcodec_setctrl(dbri);
|
1824 |
|
|
mmcodec_init_data(dbri);
|
1825 |
|
|
return 0;
|
1826 |
|
|
}
|
1827 |
|
|
|
1828 |
|
|
static int dbri_get_output_rate(struct sparcaudio_driver *drv)
|
1829 |
|
|
{
|
1830 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1831 |
|
|
|
1832 |
|
|
return dbri->perchip_info.play.sample_rate;
|
1833 |
|
|
}
|
1834 |
|
|
|
1835 |
|
|
static int dbri_set_input_rate(struct sparcaudio_driver *drv, int rate)
|
1836 |
|
|
{
|
1837 |
|
|
return dbri_set_output_rate(drv, rate);
|
1838 |
|
|
}
|
1839 |
|
|
|
1840 |
|
|
static int dbri_get_input_rate(struct sparcaudio_driver *drv)
|
1841 |
|
|
{
|
1842 |
|
|
return dbri_get_output_rate(drv);
|
1843 |
|
|
}
|
1844 |
|
|
|
1845 |
|
|
/******************* sparcaudio midlevel - ports ***********************/
|
1846 |
|
|
|
1847 |
|
|
static int dbri_set_output_port(struct sparcaudio_driver *drv, int port)
|
1848 |
|
|
{
|
1849 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1850 |
|
|
|
1851 |
|
|
port &= dbri->perchip_info.play.avail_ports;
|
1852 |
|
|
dbri->perchip_info.play.port = port;
|
1853 |
|
|
mmcodec_setgain(dbri, 0);
|
1854 |
|
|
|
1855 |
|
|
return 0;
|
1856 |
|
|
}
|
1857 |
|
|
|
1858 |
|
|
static int dbri_get_output_port(struct sparcaudio_driver *drv)
|
1859 |
|
|
{
|
1860 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1861 |
|
|
|
1862 |
|
|
return dbri->perchip_info.play.port;
|
1863 |
|
|
}
|
1864 |
|
|
|
1865 |
|
|
static int dbri_set_input_port(struct sparcaudio_driver *drv, int port)
|
1866 |
|
|
{
|
1867 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1868 |
|
|
|
1869 |
|
|
port &= dbri->perchip_info.record.avail_ports;
|
1870 |
|
|
dbri->perchip_info.record.port = port;
|
1871 |
|
|
mmcodec_setgain(dbri, 0);
|
1872 |
|
|
|
1873 |
|
|
return 0;
|
1874 |
|
|
}
|
1875 |
|
|
|
1876 |
|
|
static int dbri_get_input_port(struct sparcaudio_driver *drv)
|
1877 |
|
|
{
|
1878 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1879 |
|
|
|
1880 |
|
|
return dbri->perchip_info.record.port;
|
1881 |
|
|
}
|
1882 |
|
|
|
1883 |
|
|
static int dbri_get_output_ports(struct sparcaudio_driver *drv)
|
1884 |
|
|
{
|
1885 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1886 |
|
|
|
1887 |
|
|
return dbri->perchip_info.play.avail_ports;
|
1888 |
|
|
}
|
1889 |
|
|
|
1890 |
|
|
static int dbri_get_input_ports(struct sparcaudio_driver *drv)
|
1891 |
|
|
{
|
1892 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1893 |
|
|
|
1894 |
|
|
return dbri->perchip_info.record.avail_ports;
|
1895 |
|
|
}
|
1896 |
|
|
|
1897 |
|
|
/******************* sparcaudio midlevel - driver ID ********************/
|
1898 |
|
|
|
1899 |
|
|
static void dbri_audio_getdev(struct sparcaudio_driver *drv,
|
1900 |
|
|
audio_device_t *audinfo)
|
1901 |
|
|
{
|
1902 |
|
|
struct dbri *dbri = (struct dbri *) drv->private;
|
1903 |
|
|
|
1904 |
|
|
strncpy(audinfo->name, "SUNW,DBRI", sizeof(audinfo->name) - 1);
|
1905 |
|
|
|
1906 |
|
|
audinfo->version[0] = dbri->dbri_version;
|
1907 |
|
|
audinfo->version[1] = '\0';
|
1908 |
|
|
|
1909 |
|
|
strncpy(audinfo->config, "onboard1", sizeof(audinfo->config) - 1);
|
1910 |
|
|
}
|
1911 |
|
|
|
1912 |
|
|
static int dbri_sunaudio_getdev_sunos(struct sparcaudio_driver *drv)
|
1913 |
|
|
{
|
1914 |
|
|
return AUDIO_DEV_CODEC;
|
1915 |
|
|
}
|
1916 |
|
|
|
1917 |
|
|
/******************* sparcaudio midlevel - open & close ******************/
|
1918 |
|
|
|
1919 |
|
|
static int dbri_open(struct inode * inode, struct file * file,
|
1920 |
|
|
struct sparcaudio_driver *drv)
|
1921 |
|
|
{
|
1922 |
|
|
MOD_INC_USE_COUNT;
|
1923 |
|
|
|
1924 |
|
|
return 0;
|
1925 |
|
|
}
|
1926 |
|
|
|
1927 |
|
|
static void dbri_release(struct inode * inode, struct file * file,
|
1928 |
|
|
struct sparcaudio_driver *drv)
|
1929 |
|
|
{
|
1930 |
|
|
MOD_DEC_USE_COUNT;
|
1931 |
|
|
}
|
1932 |
|
|
|
1933 |
|
|
static int dbri_ioctl(struct inode * inode, struct file * file,
|
1934 |
|
|
unsigned int x, unsigned long y,
|
1935 |
|
|
struct sparcaudio_driver *drv)
|
1936 |
|
|
{
|
1937 |
|
|
return -EINVAL;
|
1938 |
|
|
}
|
1939 |
|
|
|
1940 |
|
|
/*********** sparcaudio midlevel - struct sparcaudio_driver ************/
|
1941 |
|
|
|
1942 |
|
|
static struct sparcaudio_operations dbri_ops = {
|
1943 |
|
|
dbri_open,
|
1944 |
|
|
dbri_release,
|
1945 |
|
|
dbri_ioctl,
|
1946 |
|
|
dbri_start_output,
|
1947 |
|
|
dbri_stop_output,
|
1948 |
|
|
dbri_start_input,
|
1949 |
|
|
dbri_stop_input,
|
1950 |
|
|
dbri_audio_getdev,
|
1951 |
|
|
dbri_set_output_volume,
|
1952 |
|
|
dbri_get_output_volume,
|
1953 |
|
|
dbri_set_input_volume,
|
1954 |
|
|
dbri_get_input_volume,
|
1955 |
|
|
dbri_set_monitor_volume,
|
1956 |
|
|
dbri_get_monitor_volume,
|
1957 |
|
|
dbri_set_output_balance,
|
1958 |
|
|
dbri_get_output_balance,
|
1959 |
|
|
dbri_set_input_balance,
|
1960 |
|
|
dbri_get_input_balance,
|
1961 |
|
|
dbri_set_output_channels,
|
1962 |
|
|
dbri_get_output_channels,
|
1963 |
|
|
dbri_set_input_channels,
|
1964 |
|
|
dbri_get_input_channels,
|
1965 |
|
|
dbri_set_output_precision,
|
1966 |
|
|
dbri_get_output_precision,
|
1967 |
|
|
dbri_set_input_precision,
|
1968 |
|
|
dbri_get_input_precision,
|
1969 |
|
|
dbri_set_output_port,
|
1970 |
|
|
dbri_get_output_port,
|
1971 |
|
|
dbri_set_input_port,
|
1972 |
|
|
dbri_get_input_port,
|
1973 |
|
|
dbri_set_output_encoding,
|
1974 |
|
|
dbri_get_output_encoding,
|
1975 |
|
|
dbri_set_input_encoding,
|
1976 |
|
|
dbri_get_input_encoding,
|
1977 |
|
|
dbri_set_output_rate,
|
1978 |
|
|
dbri_get_output_rate,
|
1979 |
|
|
dbri_set_input_rate,
|
1980 |
|
|
dbri_get_input_rate,
|
1981 |
|
|
dbri_sunaudio_getdev_sunos,
|
1982 |
|
|
dbri_get_output_ports,
|
1983 |
|
|
dbri_get_input_ports,
|
1984 |
|
|
dbri_set_output_muted,
|
1985 |
|
|
dbri_get_output_muted,
|
1986 |
|
|
};
|
1987 |
|
|
|
1988 |
|
|
|
1989 |
|
|
/*
|
1990 |
|
|
****************************************************************************
|
1991 |
|
|
************************** ISDN (Hisax) Interface **************************
|
1992 |
|
|
****************************************************************************
|
1993 |
|
|
*/
|
1994 |
|
|
void dbri_isdn_init(struct dbri *dbri)
|
1995 |
|
|
{
|
1996 |
|
|
/* Pipe 0: Receive D channel
|
1997 |
|
|
* Pipe 8: Receive B1 channel
|
1998 |
|
|
* Pipe 9: Receive B2 channel
|
1999 |
|
|
* Pipe 1: Transmit D channel
|
2000 |
|
|
* Pipe 10: Transmit B1 channel
|
2001 |
|
|
* Pipe 11: Transmit B2 channel
|
2002 |
|
|
*/
|
2003 |
|
|
|
2004 |
|
|
setup_pipe(dbri, 0, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
|
2005 |
|
|
setup_pipe(dbri, 8, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
|
2006 |
|
|
setup_pipe(dbri, 9, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
|
2007 |
|
|
|
2008 |
|
|
setup_pipe(dbri, 1, D_SDP_HDLC_D | D_SDP_TO_SER | D_SDP_LSB);
|
2009 |
|
|
setup_pipe(dbri,10, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
|
2010 |
|
|
setup_pipe(dbri,11, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
|
2011 |
|
|
|
2012 |
|
|
link_time_slot(dbri, 0, PIPEinput, 0, 2, 17);
|
2013 |
|
|
link_time_slot(dbri, 8, PIPEinput, 0, 8, 0);
|
2014 |
|
|
link_time_slot(dbri, 9, PIPEinput, 8, 8, 8);
|
2015 |
|
|
|
2016 |
|
|
link_time_slot(dbri, 1, PIPEoutput, 1, 2, 17);
|
2017 |
|
|
link_time_slot(dbri, 10, PIPEoutput, 1, 8, 0);
|
2018 |
|
|
link_time_slot(dbri, 11, PIPEoutput, 10, 8, 8);
|
2019 |
|
|
}
|
2020 |
|
|
|
2021 |
|
|
int dbri_get_irqnum(int dev)
|
2022 |
|
|
{
|
2023 |
|
|
struct dbri *dbri;
|
2024 |
|
|
|
2025 |
|
|
if (dev >= num_drivers)
|
2026 |
|
|
return(0);
|
2027 |
|
|
|
2028 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2029 |
|
|
|
2030 |
|
|
tprintk(("dbri_get_irqnum()\n"));
|
2031 |
|
|
|
2032 |
|
|
/* On the sparc, the cpu's irq number is only part of the "irq" */
|
2033 |
|
|
return (dbri->irq & NR_IRQS);
|
2034 |
|
|
}
|
2035 |
|
|
|
2036 |
|
|
int dbri_get_liu_state(int dev)
|
2037 |
|
|
{
|
2038 |
|
|
struct dbri *dbri;
|
2039 |
|
|
|
2040 |
|
|
if (dev >= num_drivers)
|
2041 |
|
|
return(0);
|
2042 |
|
|
|
2043 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2044 |
|
|
|
2045 |
|
|
tprintk(("dbri_get_liu_state() returns %d\n", dbri->liu_state));
|
2046 |
|
|
|
2047 |
|
|
return dbri->liu_state;
|
2048 |
|
|
}
|
2049 |
|
|
|
2050 |
|
|
void dbri_liu_activate(int dev, int priority);
|
2051 |
|
|
|
2052 |
|
|
void dbri_liu_init(int dev, void (*callback)(void *), void *callback_arg)
|
2053 |
|
|
{
|
2054 |
|
|
struct dbri *dbri;
|
2055 |
|
|
|
2056 |
|
|
if (dev >= num_drivers)
|
2057 |
|
|
return;
|
2058 |
|
|
|
2059 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2060 |
|
|
|
2061 |
|
|
tprintk(("dbri_liu_init()\n"));
|
2062 |
|
|
|
2063 |
|
|
/* Set callback for LIU state change */
|
2064 |
|
|
dbri->liu_callback = callback;
|
2065 |
|
|
dbri->liu_callback_arg = callback_arg;
|
2066 |
|
|
|
2067 |
|
|
dbri_isdn_init(dbri);
|
2068 |
|
|
dbri_liu_activate(dev, 0);
|
2069 |
|
|
}
|
2070 |
|
|
|
2071 |
|
|
void dbri_liu_activate(int dev, int priority)
|
2072 |
|
|
{
|
2073 |
|
|
struct dbri *dbri;
|
2074 |
|
|
int val;
|
2075 |
|
|
volatile s32 *cmd;
|
2076 |
|
|
|
2077 |
|
|
if (dev >= num_drivers)
|
2078 |
|
|
return;
|
2079 |
|
|
|
2080 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2081 |
|
|
|
2082 |
|
|
tprintk(("dbri_liu_activate()\n"));
|
2083 |
|
|
|
2084 |
|
|
if (dbri->liu_state <= 3) {
|
2085 |
|
|
u32 tmp;
|
2086 |
|
|
|
2087 |
|
|
cmd = dbri_cmdlock(dbri);
|
2088 |
|
|
|
2089 |
|
|
/* Turn on the ISDN TE interface and request activation */
|
2090 |
|
|
val = D_NT_IRM_IMM | D_NT_IRM_EN | D_NT_ACT;
|
2091 |
|
|
#ifdef LOOPBACK_D
|
2092 |
|
|
val |= D_NT_LLB(4);
|
2093 |
|
|
#endif
|
2094 |
|
|
*(cmd++) = DBRI_CMD(D_TE, 0, val);
|
2095 |
|
|
|
2096 |
|
|
dbri_cmdsend(dbri, cmd);
|
2097 |
|
|
|
2098 |
|
|
/* Activate the interface */
|
2099 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
2100 |
|
|
tmp |= D_T;
|
2101 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
2102 |
|
|
}
|
2103 |
|
|
}
|
2104 |
|
|
|
2105 |
|
|
void dbri_liu_deactivate(int dev)
|
2106 |
|
|
{
|
2107 |
|
|
struct dbri *dbri;
|
2108 |
|
|
#if 0
|
2109 |
|
|
u32 tmp;
|
2110 |
|
|
#endif
|
2111 |
|
|
|
2112 |
|
|
if (dev >= num_drivers)
|
2113 |
|
|
return;
|
2114 |
|
|
|
2115 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2116 |
|
|
|
2117 |
|
|
tprintk(("dbri_liu_deactivate()\n"));
|
2118 |
|
|
|
2119 |
|
|
#if 0
|
2120 |
|
|
/* Turn off the ISDN TE interface */
|
2121 |
|
|
tmp = sbus_readl(dbri->regs + REG0);
|
2122 |
|
|
tmp &= ~D_T;
|
2123 |
|
|
sbus_writel(tmp, dbri->regs + REG0);
|
2124 |
|
|
|
2125 |
|
|
dbri->liu_state = 0;
|
2126 |
|
|
#endif
|
2127 |
|
|
}
|
2128 |
|
|
|
2129 |
|
|
void dbri_dxmit(int dev, __u8 *buffer, unsigned int count,
|
2130 |
|
|
void (*callback)(void *, int), void *callback_arg)
|
2131 |
|
|
{
|
2132 |
|
|
struct dbri *dbri;
|
2133 |
|
|
|
2134 |
|
|
if (dev >= num_drivers)
|
2135 |
|
|
return;
|
2136 |
|
|
|
2137 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2138 |
|
|
|
2139 |
|
|
/* Pipe 1 is D channel transmit */
|
2140 |
|
|
xmit_on_pipe(dbri, 1, buffer, count, callback, callback_arg);
|
2141 |
|
|
}
|
2142 |
|
|
|
2143 |
|
|
void dbri_drecv(int dev, __u8 *buffer, unsigned int size,
|
2144 |
|
|
void (*callback)(void *, int, unsigned int),
|
2145 |
|
|
void *callback_arg)
|
2146 |
|
|
{
|
2147 |
|
|
struct dbri *dbri;
|
2148 |
|
|
|
2149 |
|
|
if (dev >= num_drivers)
|
2150 |
|
|
return;
|
2151 |
|
|
|
2152 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2153 |
|
|
|
2154 |
|
|
/* Pipe 0 is D channel receive */
|
2155 |
|
|
recv_on_pipe(dbri, 0, buffer, size, callback, callback_arg);
|
2156 |
|
|
}
|
2157 |
|
|
|
2158 |
|
|
int dbri_bopen(int dev, unsigned int chan,
|
2159 |
|
|
int hdlcmode, u_char xmit_idle_char)
|
2160 |
|
|
{
|
2161 |
|
|
struct dbri *dbri;
|
2162 |
|
|
|
2163 |
|
|
if (dev >= num_drivers || chan > 1)
|
2164 |
|
|
return -1;
|
2165 |
|
|
|
2166 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2167 |
|
|
|
2168 |
|
|
if (hdlcmode) {
|
2169 |
|
|
/* return -1; */
|
2170 |
|
|
|
2171 |
|
|
/* Pipe 8/9: receive B1/B2 channel */
|
2172 |
|
|
setup_pipe(dbri, 8+chan, D_SDP_HDLC | D_SDP_FROM_SER|D_SDP_LSB);
|
2173 |
|
|
|
2174 |
|
|
/* Pipe 10/11: transmit B1/B2 channel */
|
2175 |
|
|
setup_pipe(dbri,10+chan, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
|
2176 |
|
|
} else { /* !hdlcmode means transparent */
|
2177 |
|
|
/* Pipe 8/9: receive B1/B2 channel */
|
2178 |
|
|
setup_pipe(dbri, 8+chan, D_SDP_MEM | D_SDP_FROM_SER|D_SDP_LSB);
|
2179 |
|
|
|
2180 |
|
|
/* Pipe 10/11: transmit B1/B2 channel */
|
2181 |
|
|
setup_pipe(dbri,10+chan, D_SDP_MEM | D_SDP_TO_SER | D_SDP_LSB);
|
2182 |
|
|
}
|
2183 |
|
|
return 0;
|
2184 |
|
|
}
|
2185 |
|
|
|
2186 |
|
|
void dbri_bclose(int dev, unsigned int chan)
|
2187 |
|
|
{
|
2188 |
|
|
struct dbri *dbri;
|
2189 |
|
|
|
2190 |
|
|
if (dev >= num_drivers || chan > 1)
|
2191 |
|
|
return;
|
2192 |
|
|
|
2193 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2194 |
|
|
|
2195 |
|
|
reset_pipe(dbri, 8+chan);
|
2196 |
|
|
reset_pipe(dbri, 10+chan);
|
2197 |
|
|
}
|
2198 |
|
|
|
2199 |
|
|
void dbri_bxmit(int dev, unsigned int chan,
|
2200 |
|
|
__u8 *buffer, unsigned long count,
|
2201 |
|
|
void (*callback)(void *, int),
|
2202 |
|
|
void *callback_arg)
|
2203 |
|
|
{
|
2204 |
|
|
struct dbri *dbri;
|
2205 |
|
|
|
2206 |
|
|
if (dev >= num_drivers || chan > 1)
|
2207 |
|
|
return;
|
2208 |
|
|
|
2209 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2210 |
|
|
|
2211 |
|
|
/* Pipe 10/11 is B1/B2 channel transmit */
|
2212 |
|
|
xmit_on_pipe(dbri, 10+chan, buffer, count, callback, callback_arg);
|
2213 |
|
|
}
|
2214 |
|
|
|
2215 |
|
|
void dbri_brecv(int dev, unsigned int chan,
|
2216 |
|
|
__u8 *buffer, unsigned long size,
|
2217 |
|
|
void (*callback)(void *, int, unsigned int),
|
2218 |
|
|
void *callback_arg)
|
2219 |
|
|
{
|
2220 |
|
|
struct dbri *dbri;
|
2221 |
|
|
|
2222 |
|
|
if (dev >= num_drivers || chan > 1)
|
2223 |
|
|
return;
|
2224 |
|
|
|
2225 |
|
|
dbri = (struct dbri *) drivers[dev].private;
|
2226 |
|
|
|
2227 |
|
|
/* Pipe 8/9 is B1/B2 channel receive */
|
2228 |
|
|
recv_on_pipe(dbri, 8+chan, buffer, size, callback, callback_arg);
|
2229 |
|
|
}
|
2230 |
|
|
|
2231 |
|
|
#if defined(DBRI_ISDN)
|
2232 |
|
|
struct foreign_interface dbri_foreign_interface = {
|
2233 |
|
|
dbri_get_irqnum,
|
2234 |
|
|
dbri_get_liu_state,
|
2235 |
|
|
dbri_liu_init,
|
2236 |
|
|
dbri_liu_activate,
|
2237 |
|
|
dbri_liu_deactivate,
|
2238 |
|
|
dbri_dxmit,
|
2239 |
|
|
dbri_drecv,
|
2240 |
|
|
dbri_bopen,
|
2241 |
|
|
dbri_bclose,
|
2242 |
|
|
dbri_bxmit,
|
2243 |
|
|
dbri_brecv
|
2244 |
|
|
};
|
2245 |
|
|
EXPORT_SYMBOL(dbri_foreign_interface);
|
2246 |
|
|
#endif
|
2247 |
|
|
|
2248 |
|
|
/*
|
2249 |
|
|
****************************************************************************
|
2250 |
|
|
**************************** Initialization ********************************
|
2251 |
|
|
****************************************************************************
|
2252 |
|
|
*/
|
2253 |
|
|
|
2254 |
|
|
static int dbri_attach(struct sparcaudio_driver *drv,
|
2255 |
|
|
struct sbus_dev *sdev)
|
2256 |
|
|
{
|
2257 |
|
|
struct dbri *dbri;
|
2258 |
|
|
struct linux_prom_irqs irq;
|
2259 |
|
|
int err;
|
2260 |
|
|
|
2261 |
|
|
if (sdev->prom_name[9] < 'e') {
|
2262 |
|
|
printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
|
2263 |
|
|
sdev->prom_name[9]);
|
2264 |
|
|
return -EIO;
|
2265 |
|
|
}
|
2266 |
|
|
|
2267 |
|
|
drv->ops = &dbri_ops;
|
2268 |
|
|
drv->private = kmalloc(sizeof(struct dbri), GFP_KERNEL);
|
2269 |
|
|
if (drv->private == NULL)
|
2270 |
|
|
return -ENOMEM;
|
2271 |
|
|
|
2272 |
|
|
dbri = (struct dbri *) drv->private;
|
2273 |
|
|
memset(dbri, 0, sizeof(*dbri));
|
2274 |
|
|
|
2275 |
|
|
dbri->dma = sbus_alloc_consistent(sdev,
|
2276 |
|
|
sizeof(struct dbri_dma),
|
2277 |
|
|
&dbri->dma_dvma);
|
2278 |
|
|
|
2279 |
|
|
memset((void *) dbri->dma, 0, sizeof(struct dbri_dma));
|
2280 |
|
|
|
2281 |
|
|
dprintk(D_GEN, ("DBRI: DMA Cmd Block 0x%p (0x%08x)\n",
|
2282 |
|
|
dbri->dma, dbri->dma_dvma));
|
2283 |
|
|
|
2284 |
|
|
dbri->dbri_version = sdev->prom_name[9];
|
2285 |
|
|
dbri->sdev = sdev;
|
2286 |
|
|
|
2287 |
|
|
/* Map the registers into memory. */
|
2288 |
|
|
dbri->regs_size = sdev->reg_addrs[0].reg_size;
|
2289 |
|
|
dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
|
2290 |
|
|
sdev->reg_addrs[0].reg_size,
|
2291 |
|
|
"DBRI Registers");
|
2292 |
|
|
if (!dbri->regs) {
|
2293 |
|
|
printk(KERN_ERR "DBRI: could not allocate registers\n");
|
2294 |
|
|
sbus_free_consistent(sdev, sizeof(struct dbri_dma),
|
2295 |
|
|
(void *)dbri->dma, dbri->dma_dvma);
|
2296 |
|
|
kfree(drv->private);
|
2297 |
|
|
return -EIO;
|
2298 |
|
|
}
|
2299 |
|
|
|
2300 |
|
|
prom_getproperty(sdev->prom_node, "intr", (char *)&irq, sizeof(irq));
|
2301 |
|
|
dbri->irq = irq.pri;
|
2302 |
|
|
|
2303 |
|
|
err = request_irq(dbri->irq, dbri_intr, SA_SHIRQ,
|
2304 |
|
|
"DBRI audio/ISDN", dbri);
|
2305 |
|
|
if (err) {
|
2306 |
|
|
printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
|
2307 |
|
|
sbus_iounmap(dbri->regs, dbri->regs_size);
|
2308 |
|
|
sbus_free_consistent(sdev, sizeof(struct dbri_dma),
|
2309 |
|
|
(void *)dbri->dma, dbri->dma_dvma);
|
2310 |
|
|
kfree(drv->private);
|
2311 |
|
|
return err;
|
2312 |
|
|
}
|
2313 |
|
|
|
2314 |
|
|
dbri_initialize(dbri);
|
2315 |
|
|
err = mmcodec_init(drv);
|
2316 |
|
|
if(err) {
|
2317 |
|
|
dbri_detach(dbri);
|
2318 |
|
|
return err;
|
2319 |
|
|
}
|
2320 |
|
|
|
2321 |
|
|
/* Register ourselves with the midlevel audio driver. */
|
2322 |
|
|
err = register_sparcaudio_driver(drv,1);
|
2323 |
|
|
if (err) {
|
2324 |
|
|
printk(KERN_ERR "DBRI: unable to register audio\n");
|
2325 |
|
|
dbri_detach(dbri);
|
2326 |
|
|
return err;
|
2327 |
|
|
}
|
2328 |
|
|
|
2329 |
|
|
dbri->perchip_info.play.active = dbri->perchip_info.play.pause = 0;
|
2330 |
|
|
dbri->perchip_info.record.active = dbri->perchip_info.record.pause = 0;
|
2331 |
|
|
|
2332 |
|
|
printk(KERN_INFO "audio%d at 0x%lx (irq %d) is DBRI(%c)+CS4215(%d)\n",
|
2333 |
|
|
num_drivers, dbri->regs,
|
2334 |
|
|
dbri->irq, dbri->dbri_version, dbri->mm.version);
|
2335 |
|
|
|
2336 |
|
|
return 0;
|
2337 |
|
|
}
|
2338 |
|
|
|
2339 |
|
|
/* Probe for the dbri chip and then attach the driver. */
|
2340 |
|
|
static int __init dbri_init(void)
|
2341 |
|
|
{
|
2342 |
|
|
struct sbus_bus *sbus;
|
2343 |
|
|
struct sbus_dev *sdev;
|
2344 |
|
|
|
2345 |
|
|
num_drivers = 0;
|
2346 |
|
|
|
2347 |
|
|
/* Probe each SBUS for the DBRI chip(s). */
|
2348 |
|
|
for_all_sbusdev(sdev, sbus) {
|
2349 |
|
|
/*
|
2350 |
|
|
* The version is coded in the last character
|
2351 |
|
|
*/
|
2352 |
|
|
if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
|
2353 |
|
|
dprintk(D_GEN, ("DBRI: Found %s in SBUS slot %d\n",
|
2354 |
|
|
sdev->prom_name, sdev->slot));
|
2355 |
|
|
if (num_drivers >= MAX_DRIVERS) {
|
2356 |
|
|
printk("DBRI: Ignoring slot %d\n", sdev->slot);
|
2357 |
|
|
continue;
|
2358 |
|
|
}
|
2359 |
|
|
|
2360 |
|
|
if (dbri_attach(&drivers[num_drivers], sdev) == 0)
|
2361 |
|
|
num_drivers++;
|
2362 |
|
|
}
|
2363 |
|
|
}
|
2364 |
|
|
|
2365 |
|
|
return (num_drivers > 0) ? 0 : -EIO;
|
2366 |
|
|
}
|
2367 |
|
|
|
2368 |
|
|
static void __exit dbri_exit(void)
|
2369 |
|
|
{
|
2370 |
|
|
register int i;
|
2371 |
|
|
|
2372 |
|
|
for (i = 0; i < num_drivers; i++) {
|
2373 |
|
|
dbri_detach((struct dbri *) drivers[i].private);
|
2374 |
|
|
unregister_sparcaudio_driver(& drivers[i], 1);
|
2375 |
|
|
num_drivers--;
|
2376 |
|
|
}
|
2377 |
|
|
}
|
2378 |
|
|
|
2379 |
|
|
module_init(dbri_init);
|
2380 |
|
|
module_exit(dbri_exit);
|
2381 |
|
|
MODULE_LICENSE("GPL");
|
2382 |
|
|
|
2383 |
|
|
/*
|
2384 |
|
|
* Overrides for Emacs so that we follow Linus's tabbing style.
|
2385 |
|
|
* Emacs will notice this stuff at the end of the file and automatically
|
2386 |
|
|
* adjust the settings for this buffer only. This must remain at the end
|
2387 |
|
|
* of the file.
|
2388 |
|
|
* ---------------------------------------------------------------------------
|
2389 |
|
|
* Local Variables:
|
2390 |
|
|
* c-indent-level: 8
|
2391 |
|
|
* c-brace-imaginary-offset: 0
|
2392 |
|
|
* c-brace-offset: -8
|
2393 |
|
|
* c-argdecl-indent: 8
|
2394 |
|
|
* c-label-offset: -8
|
2395 |
|
|
* c-continued-statement-offset: 8
|
2396 |
|
|
* c-continued-brace-offset: 0
|
2397 |
|
|
* indent-tabs-mode: nil
|
2398 |
|
|
* tab-width: 8
|
2399 |
|
|
* End:
|
2400 |
|
|
*/
|