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1275 |
phoenix |
/********************************************************
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* Header file for eata_dma.c and eata_pio.c *
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* Linux EATA SCSI drivers *
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* (c) 1993-96 Michael Neuffer *
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* mike@i-Connect.Net *
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* neuffer@mail.uni-mainz.de *
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*********************************************************
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* last change: 96/08/14 *
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********************************************************/
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#ifndef _EATA_GENERIC_H
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#define _EATA_GENERIC_H
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/*********************************************
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* Misc. definitions *
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*********************************************/
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#define R_LIMIT 0x20000
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#define MAXISA 4
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#define MAXEISA 16
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#define MAXPCI 16
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#define MAXIRQ 16
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#define MAXTARGET 16
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#define MAXCHANNEL 3
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#define IS_ISA 'I'
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#define IS_EISA 'E'
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#define IS_PCI 'P'
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#define BROKEN_INQUIRY 1
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#define BUSMASTER 0xff
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#define PIO 0xfe
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#define EATA_SIGNATURE 0x45415441 /* BIG ENDIAN coded "EATA" sig. */
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#define DPT_ID1 0x12
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#define DPT_ID2 0x14
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#define ATT_ID1 0x06
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#define ATT_ID2 0x94
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#define ATT_ID3 0x0
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#define NEC_ID1 0x38
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#define NEC_ID2 0xa3
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#define NEC_ID3 0x82
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#define EATA_CP_SIZE 44
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#define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */
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#define MAX_METHOD_2 16 /* Max Devices For Method 2 */
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#define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */
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#define SG_SIZE 64
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#define SG_SIZE_BIG 252 /* max. 8096 elements, 64k */
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#define UPPER_DEVICE_QUEUE_LIMIT 64 /* The limit we have to set for the
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* device queue to keep the broken
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* midlevel SCSI code from producing
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* bogus timeouts
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*/
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#define TYPE_DISK_QUEUE 16
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#define TYPE_TAPE_QUEUE 4
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#define TYPE_ROM_QUEUE 4
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#define TYPE_OTHER_QUEUE 2
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#define FREE 0
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#define OK 0
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#define NO_TIMEOUT 0
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#define USED 1
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#define TIMEOUT 2
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#define RESET 4
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#define LOCKED 8
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#define ABORTED 16
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#define READ 0
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#define WRITE 1
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#define OTHER 2
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#define HD(cmd) ((hostdata *)&(cmd->host->hostdata))
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#define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble))
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#define SD(host) ((hostdata *)&(host->hostdata))
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#define DELAY(x) { ulong flags, i; \
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save_flags(flags); sti(); \
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i = jiffies + (x * HZ); \
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while (time_before(jiffies, i)) cpu_relax(); \
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restore_flags(flags); }
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/***********************************************
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* EATA Command & Register definitions *
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***********************************************/
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#define PCI_REG_DPTconfig 0x40
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#define PCI_REG_PumpModeAddress 0x44
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#define PCI_REG_PumpModeData 0x48
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#define PCI_REG_ConfigParam1 0x50
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#define PCI_REG_ConfigParam2 0x54
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#define EATA_CMD_PIO_SETUPTEST 0xc6
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#define EATA_CMD_PIO_READ_CONFIG 0xf0
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#define EATA_CMD_PIO_SET_CONFIG 0xf1
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#define EATA_CMD_PIO_SEND_CP 0xf2
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#define EATA_CMD_PIO_RECEIVE_SP 0xf3
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#define EATA_CMD_PIO_TRUNC 0xf4
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#define EATA_CMD_RESET 0xf9
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#define EATA_CMD_IMMEDIATE 0xfa
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#define EATA_CMD_DMA_READ_CONFIG 0xfd
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#define EATA_CMD_DMA_SET_CONFIG 0xfe
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#define EATA_CMD_DMA_SEND_CP 0xff
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#define ECS_EMULATE_SENSE 0xd4
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#define EATA_GENERIC_ABORT 0x00
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#define EATA_SPECIFIC_RESET 0x01
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#define EATA_BUS_RESET 0x02
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#define EATA_SPECIFIC_ABORT 0x03
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#define EATA_QUIET_INTR 0x04
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#define EATA_COLD_BOOT_HBA 0x06 /* Only as a last resort */
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#define EATA_FORCE_IO 0x07
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#define HA_CTRLREG 0x206 /* control register for HBA */
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#define HA_CTRL_DISINT 0x02 /* CTRLREG: disable interrupts */
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#define HA_CTRL_RESCPU 0x04 /* CTRLREG: reset processor */
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#define HA_CTRL_8HEADS 0x08 /* CTRLREG: set for drives with*
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* >=8 heads (WD1003 rudimentary :-) */
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#define HA_WCOMMAND 0x07 /* command register offset */
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#define HA_WIFC 0x06 /* immediate command offset */
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#define HA_WCODE 0x05
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#define HA_WCODE2 0x04
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#define HA_WDMAADDR 0x02 /* DMA address LSB offset */
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#define HA_RAUXSTAT 0x08 /* aux status register offset*/
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#define HA_RSTATUS 0x07 /* status register offset */
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#define HA_RDATA 0x00 /* data register (16bit) */
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#define HA_WDATA 0x00 /* data register (16bit) */
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#define HA_ABUSY 0x01 /* aux busy bit */
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#define HA_AIRQ 0x02 /* aux IRQ pending bit */
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#define HA_SERROR 0x01 /* pr. command ended in error*/
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#define HA_SMORE 0x02 /* more data soon to come */
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#define HA_SCORR 0x04 /* data corrected */
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#define HA_SDRQ 0x08 /* data request active */
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#define HA_SSC 0x10 /* seek complete */
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#define HA_SFAULT 0x20 /* write fault */
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#define HA_SREADY 0x40 /* drive ready */
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#define HA_SBUSY 0x80 /* drive busy */
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#define HA_SDRDY HA_SSC+HA_SREADY+HA_SDRQ
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/**********************************************
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* Message definitions *
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**********************************************/
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#define HA_NO_ERROR 0x00 /* No Error */
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#define HA_ERR_SEL_TO 0x01 /* Selection Timeout */
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#define HA_ERR_CMD_TO 0x02 /* Command Timeout */
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#define HA_BUS_RESET 0x03 /* SCSI Bus Reset Received */
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#define HA_INIT_POWERUP 0x04 /* Initial Controller Power-up */
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#define HA_UNX_BUSPHASE 0x05 /* Unexpected Bus Phase */
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#define HA_UNX_BUS_FREE 0x06 /* Unexpected Bus Free */
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#define HA_BUS_PARITY 0x07 /* Bus Parity Error */
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#define HA_SCSI_HUNG 0x08 /* SCSI Hung */
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#define HA_UNX_MSGRJCT 0x09 /* Unexpected Message Rejected */
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#define HA_RESET_STUCK 0x0a /* SCSI Bus Reset Stuck */
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#define HA_RSENSE_FAIL 0x0b /* Auto Request-Sense Failed */
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#define HA_PARITY_ERR 0x0c /* Controller Ram Parity Error */
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#define HA_CP_ABORT_NA 0x0d /* Abort Message sent to non-active cmd */
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#define HA_CP_ABORTED 0x0e /* Abort Message sent to active cmd */
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#define HA_CP_RESET_NA 0x0f /* Reset Message sent to non-active cmd */
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#define HA_CP_RESET 0x10 /* Reset Message sent to active cmd */
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#define HA_ECC_ERR 0x11 /* Controller Ram ECC Error */
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#define HA_PCI_PARITY 0x12 /* PCI Parity Error */
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#define HA_PCI_MABORT 0x13 /* PCI Master Abort */
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#define HA_PCI_TABORT 0x14 /* PCI Target Abort */
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#define HA_PCI_STABORT 0x15 /* PCI Signaled Target Abort */
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/**********************************************
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* Other definitions *
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**********************************************/
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struct reg_bit { /* reading this one will clear the interrupt */
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__u8 error:1; /* previous command ended in an error */
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__u8 more:1; /* more DATA coming soon, poll BSY & DRQ (PIO) */
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__u8 corr:1; /* data read was successfully corrected with ECC*/
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__u8 drq:1; /* data request active */
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__u8 sc:1; /* seek complete */
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__u8 fault:1; /* write fault */
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__u8 ready:1; /* drive ready */
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__u8 busy:1; /* controller busy */
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};
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struct reg_abit { /* reading this won't clear the interrupt */
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__u8 abusy:1; /* auxiliary busy */
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__u8 irq:1; /* set when drive interrupt is asserted */
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__u8 dummy:6;
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};
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struct eata_register { /* EATA register set */
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__u8 data_reg[2]; /* R, couldn't figure this one out */
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__u8 cp_addr[4]; /* W, CP address register */
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union {
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__u8 command; /* W, command code: [read|set] conf, send CP*/
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struct reg_bit status; /* R, see register_bit1 */
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__u8 statusbyte;
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} ovr;
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struct reg_abit aux_stat; /* R, see register_bit2 */
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};
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struct get_conf { /* Read Configuration Array */
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__u32 len; /* Should return 0x22, 0x24, etc */
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__u32 signature; /* Signature MUST be "EATA" */
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__u8 version2:4,
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version:4; /* EATA Version level */
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__u8 OCS_enabled:1, /* Overlap Command Support enabled */
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TAR_support:1, /* SCSI Target Mode supported */
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TRNXFR:1, /* Truncate Transfer Cmd not necessary *
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* Only used in PIO Mode */
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MORE_support:1, /* MORE supported (only PIO Mode) */
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DMA_support:1, /* DMA supported Driver uses only *
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* this mode */
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DMA_valid:1, /* DRQ value in Byte 30 is valid */
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ATA:1, /* ATA device connected (not supported) */
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HAA_valid:1; /* Hostadapter Address is valid */
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__u16 cppadlen; /* Number of pad bytes send after CD data *
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* set to zero for DMA commands */
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__u8 scsi_id[4]; /* SCSI ID of controller 2-0 Byte 0 res. *
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* if not, zero is returned */
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__u32 cplen; /* CP length: number of valid cp bytes */
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__u32 splen; /* Number of bytes returned after *
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* Receive SP command */
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__u16 queuesiz; /* max number of queueable CPs */
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__u16 dummy;
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__u16 SGsiz; /* max number of SG table entries */
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__u8 IRQ:4, /* IRQ used this HA */
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IRQ_TR:1, /* IRQ Trigger: 0=edge, 1=level */
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SECOND:1, /* This is a secondary controller */
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DMA_channel:2; /* DRQ index, DRQ is 2comp of DRQX */
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__u8 sync; /* device at ID 7 tru 0 is running in *
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* synchronous mode, this will disappear */
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__u8 DSBLE:1, /* ISA i/o addressing is disabled */
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FORCADR:1, /* i/o address has been forced */
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SG_64K:1,
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SG_UAE:1,
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:4;
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__u8 MAX_ID:5, /* Max number of SCSI target IDs */
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MAX_CHAN:3; /* Number of SCSI busses on HBA */
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__u8 MAX_LUN; /* Max number of LUNs */
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__u8 :3,
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AUTOTRM:1,
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M1_inst:1,
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ID_qest:1, /* Raidnum ID is questionable */
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is_PCI:1, /* HBA is PCI */
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is_EISA:1; /* HBA is EISA */
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__u8 RAIDNUM; /* unique HBA identifier */
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__u8 unused[474];
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};
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struct eata_sg_list
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{
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__u32 data;
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__u32 len;
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};
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struct eata_ccb { /* Send Command Packet structure */
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__u8 SCSI_Reset:1, /* Cause a SCSI Bus reset on the cmd */
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HBA_Init:1, /* Cause Controller to reinitialize */
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Auto_Req_Sen:1, /* Do Auto Request Sense on errors */
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scatter:1, /* Data Ptr points to a SG Packet */
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Resrvd:1, /* RFU */
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Interpret:1, /* Interpret the SCSI cdb of own use */
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DataOut:1, /* Data Out phase with command */
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DataIn:1; /* Data In phase with command */
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__u8 reqlen; /* Request Sense Length *
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* Valid if Auto_Req_Sen=1 */
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__u8 unused[3];
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__u8 FWNEST:1, /* send cmd to phys RAID component */
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unused2:7;
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__u8 Phsunit:1, /* physical unit on mirrored pair */
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I_AT:1, /* inhibit address translation */
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I_HBA_C:1, /* HBA inhibit caching */
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unused3:5;
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__u8 cp_id:5, /* SCSI Device ID of target */
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cp_channel:3; /* SCSI Channel # of HBA */
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__u8 cp_lun:3,
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:2,
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cp_luntar:1, /* CP is for target ROUTINE */
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cp_dispri:1, /* Grant disconnect privilege */
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cp_identify:1; /* Always TRUE */
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__u8 cp_msg1; /* Message bytes 0-3 */
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__u8 cp_msg2;
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__u8 cp_msg3;
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__u8 cp_cdb[12]; /* Command Descriptor Block */
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__u32 cp_datalen; /* Data Transfer Length *
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* If scatter=1 len of sg package */
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void *cp_viraddr; /* address of this ccb */
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__u32 cp_dataDMA; /* Data Address, if scatter=1 *
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* address of scatter packet */
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__u32 cp_statDMA; /* address for Status Packet */
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__u32 cp_reqDMA; /* Request Sense Address, used if *
|
| 318 |
|
|
* CP command ends with error */
|
| 319 |
|
|
/* Additional CP info begins here */
|
| 320 |
|
|
__u32 timestamp; /* Needed to measure command latency */
|
| 321 |
|
|
__u32 timeout;
|
| 322 |
|
|
__u8 sizeindex;
|
| 323 |
|
|
__u8 rw_latency;
|
| 324 |
|
|
__u8 retries;
|
| 325 |
|
|
__u8 status; /* status of this queueslot */
|
| 326 |
|
|
Scsi_Cmnd *cmd; /* address of cmd */
|
| 327 |
|
|
struct eata_sg_list *sg_list;
|
| 328 |
|
|
};
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
struct eata_sp {
|
| 332 |
|
|
__u8 hba_stat:7, /* HBA status */
|
| 333 |
|
|
EOC:1; /* True if command finished */
|
| 334 |
|
|
__u8 scsi_stat; /* Target SCSI status */
|
| 335 |
|
|
__u8 reserved[2];
|
| 336 |
|
|
__u32 residue_len; /* Number of bytes not transferred */
|
| 337 |
|
|
struct eata_ccb *ccb; /* Address set in COMMAND PACKET */
|
| 338 |
|
|
__u8 msg[12];
|
| 339 |
|
|
};
|
| 340 |
|
|
|
| 341 |
|
|
typedef struct hstd {
|
| 342 |
|
|
__u8 vendor[9];
|
| 343 |
|
|
__u8 name[18];
|
| 344 |
|
|
__u8 revision[6];
|
| 345 |
|
|
__u8 EATA_revision;
|
| 346 |
|
|
__u32 firmware_revision;
|
| 347 |
|
|
__u8 HBA_number;
|
| 348 |
|
|
__u8 bustype; /* bustype of HBA */
|
| 349 |
|
|
__u8 channel; /* # of avail. scsi channels */
|
| 350 |
|
|
__u8 state; /* state of HBA */
|
| 351 |
|
|
__u8 primary; /* true if primary */
|
| 352 |
|
|
__u8 more_support:1, /* HBA supports MORE flag */
|
| 353 |
|
|
immediate_support:1, /* HBA supports IMMEDIATE CMDs*/
|
| 354 |
|
|
broken_INQUIRY:1; /* This is an EISA HBA with *
|
| 355 |
|
|
* broken INQUIRY */
|
| 356 |
|
|
__u8 do_latency; /* Latency measurement flag */
|
| 357 |
|
|
__u32 reads[13];
|
| 358 |
|
|
__u32 writes[13];
|
| 359 |
|
|
__u32 reads_lat[12][4];
|
| 360 |
|
|
__u32 writes_lat[12][4];
|
| 361 |
|
|
__u32 all_lat[4];
|
| 362 |
|
|
__u8 resetlevel[MAXCHANNEL];
|
| 363 |
|
|
__u32 last_ccb; /* Last used ccb */
|
| 364 |
|
|
__u32 cplen; /* size of CP in words */
|
| 365 |
|
|
__u16 cppadlen; /* pad length of cp in words */
|
| 366 |
|
|
__u16 queuesize;
|
| 367 |
|
|
__u16 sgsize; /* # of entries in the SG list*/
|
| 368 |
|
|
__u16 devflags; /* bits set for detected devices */
|
| 369 |
|
|
__u8 hostid; /* SCSI ID of HBA */
|
| 370 |
|
|
__u8 moresupport; /* HBA supports MORE flag */
|
| 371 |
|
|
struct Scsi_Host *next;
|
| 372 |
|
|
struct Scsi_Host *prev;
|
| 373 |
|
|
struct eata_sp sp; /* status packet */
|
| 374 |
|
|
struct eata_ccb ccb[0]; /* ccb array begins here */
|
| 375 |
|
|
}hostdata;
|
| 376 |
|
|
|
| 377 |
|
|
/* structure for max. 2 emulated drives */
|
| 378 |
|
|
struct drive_geom_emul {
|
| 379 |
|
|
__u8 trans; /* translation flag 1=transl */
|
| 380 |
|
|
__u8 channel; /* SCSI channel number */
|
| 381 |
|
|
__u8 HBA; /* HBA number (prim/sec) */
|
| 382 |
|
|
__u8 id; /* drive id */
|
| 383 |
|
|
__u8 lun; /* drive lun */
|
| 384 |
|
|
__u32 heads; /* number of heads */
|
| 385 |
|
|
__u32 sectors; /* number of sectors */
|
| 386 |
|
|
__u32 cylinder; /* number of cylinders */
|
| 387 |
|
|
};
|
| 388 |
|
|
|
| 389 |
|
|
struct geom_emul {
|
| 390 |
|
|
__u8 bios_drives; /* number of emulated drives */
|
| 391 |
|
|
struct drive_geom_emul drv[2]; /* drive structures */
|
| 392 |
|
|
};
|
| 393 |
|
|
|
| 394 |
|
|
#endif /* _EATA_GENERIC_H */
|
| 395 |
|
|
|
| 396 |
|
|
/*
|
| 397 |
|
|
* Overrides for Emacs so that we almost follow Linus's tabbing style.
|
| 398 |
|
|
* Emacs will notice this stuff at the end of the file and automatically
|
| 399 |
|
|
* adjust the settings for this buffer only. This must remain at the end
|
| 400 |
|
|
* of the file.
|
| 401 |
|
|
* ---------------------------------------------------------------------------
|
| 402 |
|
|
* Local variables:
|
| 403 |
|
|
* c-indent-level: 4
|
| 404 |
|
|
* c-brace-imaginary-offset: 0
|
| 405 |
|
|
* c-brace-offset: -4
|
| 406 |
|
|
* c-argdecl-indent: 4
|
| 407 |
|
|
* c-label-offset: -4
|
| 408 |
|
|
* c-continued-statement-offset: 4
|
| 409 |
|
|
* c-continued-brace-offset: 0
|
| 410 |
|
|
* tab-width: 8
|
| 411 |
|
|
* End:
|
| 412 |
|
|
*/
|
