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1275 |
phoenix |
/**************************************************************************
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* Initio A100 device driver for Linux.
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*
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* Copyright (c) 1994-1998 Initio Corporation
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* --------------------------------------------------------------------------
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Where this Software is combined with software released under the terms of
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* the GNU General Public License ("GPL") and the terms of the GPL would require the
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* combined work to also be released under the terms of the GPL, the terms
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* and conditions of this License will apply in addition to those of the
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* GPL with the exception of any terms or conditions of this License that
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* conflict with, or are expressly prohibited by, the GPL.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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**************************************************************************
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*
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* Module: inia100.h
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* Description: INI-A100U2W LINUX device driver header
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* Revision History:
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* 06/18/98 HL, Initial Version 1.02
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* 12/19/98 bv, v1.02a Use spinlocks for 2.1.95 and up.
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**************************************************************************/
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#include <linux/config.h>
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#include <linux/types.h>
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#define ULONG unsigned long
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#define PVOID void *
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#define USHORT unsigned short
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#define UCHAR unsigned char
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#define BYTE unsigned char
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#define WORD unsigned short
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#define DWORD unsigned long
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#define UBYTE unsigned char
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#define UWORD unsigned short
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#define UDWORD unsigned long
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#define U32 u32
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#ifndef NULL
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#define NULL 0 /* zero */
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#endif
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#ifndef TRUE
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#define TRUE (1) /* boolean true */
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#endif
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#ifndef FALSE
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#define FALSE (0) /* boolean false */
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#endif
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#ifndef FAILURE
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#define FAILURE (-1)
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#endif
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#if 1
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#define ORC_MAXQUEUE 245
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#else
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#define ORC_MAXQUEUE 25
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#endif
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#define TOTAL_SG_ENTRY 32
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#define MAX_TARGETS 16
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#define IMAX_CDB 15
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#define SENSE_SIZE 14
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#define MAX_SUPPORTED_ADAPTERS 4
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#define SUCCESSFUL 0x00
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#define I920_DEVICE_ID 0x0002 /* Initio's inic-950 product ID */
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/************************************************************************/
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/* Scatter-Gather Element Structure */
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/************************************************************************/
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typedef struct ORC_SG_Struc {
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U32 SG_Ptr; /* Data Pointer */
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U32 SG_Len; /* Data Length */
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} ORC_SG;
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typedef struct inia100_Adpt_Struc {
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UWORD ADPT_BIOS; /* 0 */
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UWORD ADPT_BASE; /* 1 */
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UBYTE ADPT_Bus; /* 2 */
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UBYTE ADPT_Device; /* 3 */
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UBYTE ADPT_INTR; /* 4 */
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} INIA100_ADPT_STRUCT;
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/* SCSI related definition */
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#define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
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#define DISC_ALLOW 0xC0 /* Disconnect is allowed */
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#define ORC_OFFSET_SCB 16
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#define ORC_MAX_SCBS 250
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#define MAX_CHANNELS 2
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#define MAX_ESCB_ELE 64
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#define TCF_DRV_255_63 0x0400
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/********************************************************/
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/* Orchid Configuration Register Set */
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/********************************************************/
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#define ORC_PVID 0x00 /* Vendor ID */
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#define ORC_VENDOR_ID 0x1101 /* Orchid vendor ID */
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#define ORC_PDID 0x02 /* Device ID */
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#define ORC_DEVICE_ID 0x1060 /* Orchid device ID */
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#define ORC_COMMAND 0x04 /* Command */
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#define BUSMS 0x04 /* BUS MASTER Enable */
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#define IOSPA 0x01 /* IO Space Enable */
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#define ORC_STATUS 0x06 /* Status register */
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#define ORC_REVISION 0x08 /* Revision number */
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#define ORC_BASE 0x10 /* Base address */
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#define ORC_BIOS 0x50 /* Expansion ROM base address */
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#define ORC_INT_NUM 0x3C /* Interrupt line */
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#define ORC_INT_PIN 0x3D /* Interrupt pin */
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/********************************************************/
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/* Orchid Host Command Set */
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/********************************************************/
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#define ORC_CMD_NOP 0x00 /* Host command - NOP */
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#define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
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#define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
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#define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
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#define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
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#define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
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#define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
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#define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
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/********************************************************/
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/* Orchid Register Set */
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/********************************************************/
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#define ORC_GINTS 0xA0 /* Global Interrupt Status */
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#define QINT 0x04 /* Reply Queue Interrupt */
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#define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
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#define MQINT 0x04 /* Mask Reply Queue Interrupt */
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#define ORC_GCFG 0xA2 /* Global Configure */
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#define EEPRG 0x01 /* Enable EEPROM programming */
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#define ORC_GSTAT 0xA3 /* Global status */
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#define WIDEBUS 0x10 /* Wide SCSI Devices connected */
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#define ORC_HDATA 0xA4 /* Host Data */
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#define ORC_HCTRL 0xA5 /* Host Control */
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#define SCSIRST 0x80 /* SCSI bus reset */
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#define HDO 0x40 /* Host data out */
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#define HOSTSTOP 0x02 /* Host stop RISC engine */
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#define DEVRST 0x01 /* Device reset */
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#define ORC_HSTUS 0xA6 /* Host Status */
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#define HDI 0x02 /* Host data in */
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#define RREADY 0x01 /* RISC engine is ready to receive */
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#define ORC_NVRAM 0xA7 /* Nvram port address */
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#define SE2CS 0x008
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#define SE2CLK 0x004
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#define SE2DO 0x002
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#define SE2DI 0x001
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#define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
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#define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
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#define ORC_RQUEUE 0xAA /* Reply queue FIFO */
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#define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
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#define ORC_FWBASEADR 0xAC /* Firmware base address */
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#define ORC_EBIOSADR0 0xB0 /* External Bios address */
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#define ORC_EBIOSADR1 0xB1 /* External Bios address */
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#define ORC_EBIOSADR2 0xB2 /* External Bios address */
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#define ORC_EBIOSDATA 0xB3 /* External Bios address */
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#define ORC_SCBSIZE 0xB7 /* SCB size register */
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#define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
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#define ORC_SCBBASE1 0xBC /* SCB base address 1 */
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#define ORC_RISCCTL 0xE0 /* RISC Control */
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#define PRGMRST 0x002
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#define DOWNLOAD 0x001
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#define ORC_PRGMCTR0 0xE2 /* RISC program counter */
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#define ORC_PRGMCTR1 0xE3 /* RISC program counter */
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#define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
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typedef struct orc_extended_scb { /* Extended SCB */
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ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */
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unsigned char *SCB_Srb; /*50 SRB Pointer */
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// Scsi_Cmnd *SCB_Srb; /*50 SRB Pointer */
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} ESCB;
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/***********************************************************************
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SCSI Control Block
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************************************************************************/
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typedef struct orc_scb { /* Scsi_Ctrl_Blk */
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UBYTE SCB_Opcode; /*00 SCB command code&residual */
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UBYTE SCB_Flags; /*01 SCB Flags */
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UBYTE SCB_Target; /*02 Target Id */
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UBYTE SCB_Lun; /*03 Lun */
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U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */
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U32 SCB_XferLen; /*08 Data Transfer Length */
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U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */
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U32 SCB_SGLen; /*10 SG list # * 8 */
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U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */
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U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */
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UBYTE SCB_HaStat; /*1C Host Status */
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UBYTE SCB_TaStat; /*1D Target Status */
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UBYTE SCB_Status; /*1E SCB status */
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UBYTE SCB_Link; /*1F Link pointer, default 0xFF */
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UBYTE SCB_SenseLen; /*20 Sense Allocation Length */
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UBYTE SCB_CDBLen; /*21 CDB Length */
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UBYTE SCB_Ident; /*22 Identify */
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UBYTE SCB_TagMsg; /*23 Tag Message */
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UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */
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UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */
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U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */
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ESCB *SCB_EScb; /*38 Extended SCB Pointer */
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#ifndef ALPHA
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UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */
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#endif
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} ORC_SCB;
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/* Opcodes of ORCSCB_Opcode */
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#define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
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#define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
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/* Status of ORCSCB_Status */
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#define SCB_COMPLETE 0x00 /* SCB request completed */
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#define SCB_POST 0x01 /* SCB is posted by the HOST */
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/* Bit Definition for ORCSCB_Flags */
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#define SCF_DISINT 0x01 /* Disable HOST interrupt */
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#define SCF_DIR 0x18 /* Direction bits */
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#define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
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#define SCF_DIN 0x08 /* From Target to Initiator */
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#define SCF_DOUT 0x10 /* From Initiator to Target */
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#define SCF_NO_XF 0x18 /* No data transfer */
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#define SCF_POLL 0x40
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/* Error Codes for ORCSCB_HaStat */
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#define HOST_SEL_TOUT 0x11
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#define HOST_DO_DU 0x12
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#define HOST_BUS_FREE 0x13
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#define HOST_BAD_PHAS 0x14
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#define HOST_INV_CMD 0x16
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#define HOST_SCSI_RST 0x1B
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#define HOST_DEV_RST 0x1C
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/* Error Codes for ORCSCB_TaStat */
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#define TARGET_CHK_COND 0x02
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#define TARGET_BUSY 0x08
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#define TARGET_TAG_FULL 0x28
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| 281 |
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/* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
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#define MSG_STAG 0x20
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#define MSG_HTAG 0x21
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#define MSG_OTAG 0x22
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#define MSG_IGNOREWIDE 0x23
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#define MSG_IDENT 0x80
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#define MSG_DISC 0x40 /* Disconnect allowed */
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/* SCSI MESSAGE */
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#define MSG_EXTEND 0x01
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#define MSG_SDP 0x02
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#define MSG_ABORT 0x06
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#define MSG_REJ 0x07
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#define MSG_NOP 0x08
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#define MSG_PARITY 0x09
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#define MSG_DEVRST 0x0C
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#define MSG_STAG 0x20
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/***********************************************************************
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Target Device Control Structure
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**********************************************************************/
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| 306 |
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typedef struct ORC_Tar_Ctrl_Struc {
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UBYTE TCS_DrvDASD; /* 6 */
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UBYTE TCS_DrvSCSI; /* 7 */
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UBYTE TCS_DrvHead; /* 8 */
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UWORD TCS_DrvFlags; /* 4 */
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UBYTE TCS_DrvSector; /* 7 */
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} ORC_TCS, *PORC_TCS;
|
| 313 |
|
|
|
| 314 |
|
|
/* Bit Definition for TCF_DrvFlags */
|
| 315 |
|
|
#define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
|
| 316 |
|
|
#define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
/***********************************************************************
|
| 320 |
|
|
Host Adapter Control Structure
|
| 321 |
|
|
************************************************************************/
|
| 322 |
|
|
typedef struct ORC_Ha_Ctrl_Struc {
|
| 323 |
|
|
USHORT HCS_Base; /* 00 */
|
| 324 |
|
|
UBYTE HCS_Index; /* 02 */
|
| 325 |
|
|
UBYTE HCS_Intr; /* 04 */
|
| 326 |
|
|
UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */
|
| 327 |
|
|
UBYTE HCS_BIOS; /* 07 BIOS configuration */
|
| 328 |
|
|
|
| 329 |
|
|
UBYTE HCS_Flags; /* 0B */
|
| 330 |
|
|
UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */
|
| 331 |
|
|
UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */
|
| 332 |
|
|
|
| 333 |
|
|
USHORT HCS_Units; /* Number of units this adapter */
|
| 334 |
|
|
USHORT HCS_AFlags; /* Adapter info. defined flags */
|
| 335 |
|
|
ULONG HCS_Timeout; /* Adapter timeout value */
|
| 336 |
|
|
PVOID HCS_virScbArray; /* 28 Virtual Pointer to SCB array */
|
| 337 |
|
|
U32 HCS_physScbArray; /* Scb Physical address */
|
| 338 |
|
|
PVOID HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */
|
| 339 |
|
|
U32 HCS_physEscbArray; /* scatter list Physical address */
|
| 340 |
|
|
UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */
|
| 341 |
|
|
UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */
|
| 342 |
|
|
UBYTE ActiveTags[16][16]; /* 50 */
|
| 343 |
|
|
ORC_TCS HCS_Tcs[16]; /* 28 */
|
| 344 |
|
|
U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
|
| 345 |
|
|
spinlock_t BitAllocFlagLock;
|
| 346 |
|
|
ULONG pSRB_head;
|
| 347 |
|
|
ULONG pSRB_tail;
|
| 348 |
|
|
spinlock_t pSRB_lock;
|
| 349 |
|
|
} ORC_HCS;
|
| 350 |
|
|
|
| 351 |
|
|
/* Bit Definition for HCS_Flags */
|
| 352 |
|
|
|
| 353 |
|
|
#define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
|
| 354 |
|
|
#define HCF_PARITY 0x02 /* parity card */
|
| 355 |
|
|
#define HCF_LVDS 0x10 /* parity card */
|
| 356 |
|
|
|
| 357 |
|
|
/* Bit Definition for TargetFlag */
|
| 358 |
|
|
|
| 359 |
|
|
#define TCF_EN_255 0x08
|
| 360 |
|
|
#define TCF_EN_TAG 0x10
|
| 361 |
|
|
#define TCF_BUSY 0x20
|
| 362 |
|
|
#define TCF_DISCONNECT 0x40
|
| 363 |
|
|
#define TCF_SPIN_UP 0x80
|
| 364 |
|
|
|
| 365 |
|
|
/* Bit Definition for HCS_AFlags */
|
| 366 |
|
|
#define HCS_AF_IGNORE 0x01 /* Adapter ignore */
|
| 367 |
|
|
#define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
|
| 368 |
|
|
#define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
/*---------------------------------------*/
|
| 372 |
|
|
/* TimeOut for RESET to complete (30s) */
|
| 373 |
|
|
/* */
|
| 374 |
|
|
/* After a RESET the drive is checked */
|
| 375 |
|
|
/* every 200ms. */
|
| 376 |
|
|
/*---------------------------------------*/
|
| 377 |
|
|
#define DELAYED_RESET_MAX (30*1000L)
|
| 378 |
|
|
#define DELAYED_RESET_INTERVAL 200L
|
| 379 |
|
|
|
| 380 |
|
|
/*----------------------------------------------*/
|
| 381 |
|
|
/* TimeOut for IRQ from last interrupt (5s) */
|
| 382 |
|
|
/*----------------------------------------------*/
|
| 383 |
|
|
#define IRQ_TIMEOUT_INTERVAL (5*1000L)
|
| 384 |
|
|
|
| 385 |
|
|
/*----------------------------------------------*/
|
| 386 |
|
|
/* Retry Delay interval (200ms) */
|
| 387 |
|
|
/*----------------------------------------------*/
|
| 388 |
|
|
#define DELAYED_RETRY_INTERVAL 200L
|
| 389 |
|
|
|
| 390 |
|
|
#define INQUIRY_SIZE 36
|
| 391 |
|
|
#define CAPACITY_SIZE 8
|
| 392 |
|
|
#define DEFAULT_SENSE_LEN 14
|
| 393 |
|
|
|
| 394 |
|
|
#define DEVICE_NOT_FOUND 0x86
|
| 395 |
|
|
|
| 396 |
|
|
/*----------------------------------------------*/
|
| 397 |
|
|
/* Definition for PCI device */
|
| 398 |
|
|
/*----------------------------------------------*/
|
| 399 |
|
|
#define MAX_PCI_DEVICES 21
|
| 400 |
|
|
#define MAX_PCI_BUSES 8
|
| 401 |
|
|
|
| 402 |
|
|
typedef struct Adpt_Struc {
|
| 403 |
|
|
USHORT ADPT_BIOS; /* 0 */
|
| 404 |
|
|
UBYTE ADPT_BASE; /* 1 */
|
| 405 |
|
|
UBYTE ADPT_Bus; /* 2 */
|
| 406 |
|
|
UBYTE ADPT_Device; /* 3 */
|
| 407 |
|
|
UBYTE ADPT_Reserved[3];
|
| 408 |
|
|
} JACS, *PJACS;
|
| 409 |
|
|
|
| 410 |
|
|
typedef struct _NVRAM {
|
| 411 |
|
|
/*----------header ---------------*/
|
| 412 |
|
|
UCHAR SubVendorID0; /* 00 - Sub Vendor ID */
|
| 413 |
|
|
UCHAR SubVendorID1; /* 00 - Sub Vendor ID */
|
| 414 |
|
|
UCHAR SubSysID0; /* 02 - Sub System ID */
|
| 415 |
|
|
UCHAR SubSysID1; /* 02 - Sub System ID */
|
| 416 |
|
|
UCHAR SubClass; /* 04 - Sub Class */
|
| 417 |
|
|
UCHAR VendorID0; /* 05 - Vendor ID */
|
| 418 |
|
|
UCHAR VendorID1; /* 05 - Vendor ID */
|
| 419 |
|
|
UCHAR DeviceID0; /* 07 - Device ID */
|
| 420 |
|
|
UCHAR DeviceID1; /* 07 - Device ID */
|
| 421 |
|
|
UCHAR Reserved0[2]; /* 09 - Reserved */
|
| 422 |
|
|
UCHAR Revision; /* 0B - Revision of data structure */
|
| 423 |
|
|
/* ----Host Adapter Structure ---- */
|
| 424 |
|
|
UCHAR NumOfCh; /* 0C - Number of SCSI channel */
|
| 425 |
|
|
UCHAR BIOSConfig1; /* 0D - BIOS configuration 1 */
|
| 426 |
|
|
UCHAR BIOSConfig2; /* 0E - BIOS boot channel&target ID */
|
| 427 |
|
|
UCHAR BIOSConfig3; /* 0F - BIOS configuration 3 */
|
| 428 |
|
|
/* ----SCSI channel Structure ---- */
|
| 429 |
|
|
/* from "CTRL-I SCSI Host Adapter SetUp menu " */
|
| 430 |
|
|
UCHAR SCSI0Id; /* 10 - Channel 0 SCSI ID */
|
| 431 |
|
|
UCHAR SCSI0Config; /* 11 - Channel 0 SCSI configuration */
|
| 432 |
|
|
UCHAR SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */
|
| 433 |
|
|
UCHAR SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */
|
| 434 |
|
|
UCHAR ReservedforChannel0[2]; /* 14 - Reserved */
|
| 435 |
|
|
|
| 436 |
|
|
/* ----SCSI target Structure ---- */
|
| 437 |
|
|
/* from "CTRL-I SCSI device SetUp menu " */
|
| 438 |
|
|
UCHAR Target00Config; /* 16 - Channel 0 Target 0 config */
|
| 439 |
|
|
UCHAR Target01Config; /* 17 - Channel 0 Target 1 config */
|
| 440 |
|
|
UCHAR Target02Config; /* 18 - Channel 0 Target 2 config */
|
| 441 |
|
|
UCHAR Target03Config; /* 19 - Channel 0 Target 3 config */
|
| 442 |
|
|
UCHAR Target04Config; /* 1A - Channel 0 Target 4 config */
|
| 443 |
|
|
UCHAR Target05Config; /* 1B - Channel 0 Target 5 config */
|
| 444 |
|
|
UCHAR Target06Config; /* 1C - Channel 0 Target 6 config */
|
| 445 |
|
|
UCHAR Target07Config; /* 1D - Channel 0 Target 7 config */
|
| 446 |
|
|
UCHAR Target08Config; /* 1E - Channel 0 Target 8 config */
|
| 447 |
|
|
UCHAR Target09Config; /* 1F - Channel 0 Target 9 config */
|
| 448 |
|
|
UCHAR Target0AConfig; /* 20 - Channel 0 Target A config */
|
| 449 |
|
|
UCHAR Target0BConfig; /* 21 - Channel 0 Target B config */
|
| 450 |
|
|
UCHAR Target0CConfig; /* 22 - Channel 0 Target C config */
|
| 451 |
|
|
UCHAR Target0DConfig; /* 23 - Channel 0 Target D config */
|
| 452 |
|
|
UCHAR Target0EConfig; /* 24 - Channel 0 Target E config */
|
| 453 |
|
|
UCHAR Target0FConfig; /* 25 - Channel 0 Target F config */
|
| 454 |
|
|
|
| 455 |
|
|
UCHAR SCSI1Id; /* 26 - Channel 1 SCSI ID */
|
| 456 |
|
|
UCHAR SCSI1Config; /* 27 - Channel 1 SCSI configuration */
|
| 457 |
|
|
UCHAR SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */
|
| 458 |
|
|
UCHAR SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */
|
| 459 |
|
|
UCHAR ReservedforChannel1[2]; /* 2A - Reserved */
|
| 460 |
|
|
|
| 461 |
|
|
/* ----SCSI target Structure ---- */
|
| 462 |
|
|
/* from "CTRL-I SCSI device SetUp menu " */
|
| 463 |
|
|
UCHAR Target10Config; /* 2C - Channel 1 Target 0 config */
|
| 464 |
|
|
UCHAR Target11Config; /* 2D - Channel 1 Target 1 config */
|
| 465 |
|
|
UCHAR Target12Config; /* 2E - Channel 1 Target 2 config */
|
| 466 |
|
|
UCHAR Target13Config; /* 2F - Channel 1 Target 3 config */
|
| 467 |
|
|
UCHAR Target14Config; /* 30 - Channel 1 Target 4 config */
|
| 468 |
|
|
UCHAR Target15Config; /* 31 - Channel 1 Target 5 config */
|
| 469 |
|
|
UCHAR Target16Config; /* 32 - Channel 1 Target 6 config */
|
| 470 |
|
|
UCHAR Target17Config; /* 33 - Channel 1 Target 7 config */
|
| 471 |
|
|
UCHAR Target18Config; /* 34 - Channel 1 Target 8 config */
|
| 472 |
|
|
UCHAR Target19Config; /* 35 - Channel 1 Target 9 config */
|
| 473 |
|
|
UCHAR Target1AConfig; /* 36 - Channel 1 Target A config */
|
| 474 |
|
|
UCHAR Target1BConfig; /* 37 - Channel 1 Target B config */
|
| 475 |
|
|
UCHAR Target1CConfig; /* 38 - Channel 1 Target C config */
|
| 476 |
|
|
UCHAR Target1DConfig; /* 39 - Channel 1 Target D config */
|
| 477 |
|
|
UCHAR Target1EConfig; /* 3A - Channel 1 Target E config */
|
| 478 |
|
|
UCHAR Target1FConfig; /* 3B - Channel 1 Target F config */
|
| 479 |
|
|
UCHAR reserved[3]; /* 3C - Reserved */
|
| 480 |
|
|
/* ---------- CheckSum ---------- */
|
| 481 |
|
|
UCHAR CheckSum; /* 3F - Checksum of NVRam */
|
| 482 |
|
|
} NVRAM, *PNVRAM;
|
| 483 |
|
|
|
| 484 |
|
|
/* Bios Configuration for nvram->BIOSConfig1 */
|
| 485 |
|
|
#define NBC_BIOSENABLE 0x01 /* BIOS enable */
|
| 486 |
|
|
#define NBC_CDROM 0x02 /* Support bootable CDROM */
|
| 487 |
|
|
#define NBC_REMOVABLE 0x04 /* Support removable drive */
|
| 488 |
|
|
|
| 489 |
|
|
/* Bios Configuration for nvram->BIOSConfig2 */
|
| 490 |
|
|
#define NBB_TARGET_MASK 0x0F /* Boot SCSI target ID number */
|
| 491 |
|
|
#define NBB_CHANL_MASK 0xF0 /* Boot SCSI channel number */
|
| 492 |
|
|
|
| 493 |
|
|
/* Bit definition for nvram->SCSIConfig */
|
| 494 |
|
|
#define NCC_BUSRESET 0x01 /* Reset SCSI bus at power up */
|
| 495 |
|
|
#define NCC_PARITYCHK 0x02 /* SCSI parity enable */
|
| 496 |
|
|
#define NCC_LVDS 0x10 /* Enable LVDS */
|
| 497 |
|
|
#define NCC_ACTTERM1 0x20 /* Enable active terminator 1 */
|
| 498 |
|
|
#define NCC_ACTTERM2 0x40 /* Enable active terminator 2 */
|
| 499 |
|
|
#define NCC_AUTOTERM 0x80 /* Enable auto termination */
|
| 500 |
|
|
|
| 501 |
|
|
/* Bit definition for nvram->TargetxConfig */
|
| 502 |
|
|
#define NTC_PERIOD 0x07 /* Maximum Sync. Speed */
|
| 503 |
|
|
#define NTC_1GIGA 0x08 /* 255 head / 63 sectors (64/32) */
|
| 504 |
|
|
#define NTC_NO_SYNC 0x10 /* NO SYNC. NEGO */
|
| 505 |
|
|
#define NTC_NO_WIDESYNC 0x20 /* NO WIDE SYNC. NEGO */
|
| 506 |
|
|
#define NTC_DISC_ENABLE 0x40 /* Enable SCSI disconnect */
|
| 507 |
|
|
#define NTC_SPINUP 0x80 /* Start disk drive */
|
| 508 |
|
|
|
| 509 |
|
|
/* Default NVRam values */
|
| 510 |
|
|
#define NBC_DEFAULT (NBC_ENABLE)
|
| 511 |
|
|
#define NCC_DEFAULT (NCC_BUSRESET | NCC_AUTOTERM | NCC_PARITYCHK)
|
| 512 |
|
|
#define NCC_MAX_TAGS 0x20 /* Maximum tags per target */
|
| 513 |
|
|
#define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */
|
| 514 |
|
|
#define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE)
|
| 515 |
|
|
|
| 516 |
|
|
typedef union { /* Union define for mechanism 1 */
|
| 517 |
|
|
struct {
|
| 518 |
|
|
unsigned char RegNum;
|
| 519 |
|
|
unsigned char FcnNum:3;
|
| 520 |
|
|
unsigned char DeviceNum:5;
|
| 521 |
|
|
unsigned char BusNum;
|
| 522 |
|
|
unsigned char Reserved:7;
|
| 523 |
|
|
unsigned char Enable:1;
|
| 524 |
|
|
} sConfigAdr;
|
| 525 |
|
|
unsigned long lConfigAdr;
|
| 526 |
|
|
} CONFIG_ADR;
|
| 527 |
|
|
|
| 528 |
|
|
typedef union { /* Union define for mechanism 2 */
|
| 529 |
|
|
struct {
|
| 530 |
|
|
unsigned char RegNum;
|
| 531 |
|
|
unsigned char DeviceNum;
|
| 532 |
|
|
unsigned short Reserved;
|
| 533 |
|
|
} sHostAdr;
|
| 534 |
|
|
unsigned long lHostAdr;
|
| 535 |
|
|
} HOST_ADR;
|
| 536 |
|
|
|
| 537 |
|
|
#define ORC_RD(x,y) (UCHAR)(inb( (int)((ULONG)((ULONG)x+(UCHAR)y)) ))
|
| 538 |
|
|
#define ORC_RDLONG(x,y) (long)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
|
| 539 |
|
|
|
| 540 |
|
|
#define ORC_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
|
| 541 |
|
|
#define ORC_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
|
| 542 |
|
|
#define ORC_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
|
| 543 |
|
|
|
| 544 |
|
|
|
| 545 |
|
|
#define SCSI_ABORT_SNOOZE 0
|
| 546 |
|
|
#define SCSI_ABORT_SUCCESS 1
|
| 547 |
|
|
#define SCSI_ABORT_PENDING 2
|
| 548 |
|
|
#define SCSI_ABORT_BUSY 3
|
| 549 |
|
|
#define SCSI_ABORT_NOT_RUNNING 4
|
| 550 |
|
|
#define SCSI_ABORT_ERROR 5
|
| 551 |
|
|
|
| 552 |
|
|
#define SCSI_RESET_SNOOZE 0
|
| 553 |
|
|
#define SCSI_RESET_PUNT 1
|
| 554 |
|
|
#define SCSI_RESET_SUCCESS 2
|
| 555 |
|
|
#define SCSI_RESET_PENDING 3
|
| 556 |
|
|
#define SCSI_RESET_WAKEUP 4
|
| 557 |
|
|
#define SCSI_RESET_NOT_RUNNING 5
|
| 558 |
|
|
#define SCSI_RESET_ERROR 6
|
| 559 |
|
|
|
| 560 |
|
|
#define SCSI_RESET_SYNCHRONOUS 0x01
|
| 561 |
|
|
#define SCSI_RESET_ASYNCHRONOUS 0x02
|
| 562 |
|
|
#define SCSI_RESET_SUGGEST_BUS_RESET 0x04
|
| 563 |
|
|
#define SCSI_RESET_SUGGEST_HOST_RESET 0x08
|
| 564 |
|
|
|
| 565 |
|
|
#define SCSI_RESET_BUS_RESET 0x100
|
| 566 |
|
|
#define SCSI_RESET_HOST_RESET 0x200
|
| 567 |
|
|
#define SCSI_RESET_ACTION 0xff
|
