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1275 |
phoenix |
/**************************************************************************
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* Initio 9100 device driver for Linux.
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*
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* Copyright (c) 1994-1998 Initio Corporation
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* --------------------------------------------------------------------------
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Where this Software is combined with software released under the terms of
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* the GNU General Public License ("GPL") and the terms of the GPL would require the
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* combined work to also be released under the terms of the GPL, the terms
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* and conditions of this License will apply in addition to those of the
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* GPL with the exception of any terms or conditions of this License that
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* conflict with, or are expressly prohibited by, the GPL.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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**************************************************************************/
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#include <linux/config.h>
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#include <linux/types.h>
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#define ULONG unsigned long
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#define USHORT unsigned short
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#define UCHAR unsigned char
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#define BYTE unsigned char
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#define WORD unsigned short
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#define DWORD unsigned long
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#define UBYTE unsigned char
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#define UWORD unsigned short
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#define UDWORD unsigned long
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#define U32 u32
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#ifndef NULL
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#define NULL 0 /* zero */
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#endif
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#ifndef TRUE
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#define TRUE (1) /* boolean true */
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#endif
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#ifndef FALSE
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#define FALSE (0) /* boolean false */
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#endif
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#ifndef FAILURE
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#define FAILURE (-1)
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#endif
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#define TOTAL_SG_ENTRY 32
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#define MAX_SUPPORTED_ADAPTERS 8
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#define MAX_OFFSET 15
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#define MAX_TARGETS 16
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#define INI_VENDOR_ID 0x1101 /* Initio's PCI vendor ID */
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#define I950_DEVICE_ID 0x9500 /* Initio's inic-950 product ID */
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#define I940_DEVICE_ID 0x9400 /* Initio's inic-940 product ID */
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#define I935_DEVICE_ID 0x9401 /* Initio's inic-935 product ID */
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#define _I91USCSI_H
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typedef struct {
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unsigned short base;
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unsigned short vec;
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} i91u_config;
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/***************************************/
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/* Tulip Configuration Register Set */
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/***************************************/
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#define TUL_PVID 0x00 /* Vendor ID */
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#define TUL_PDID 0x02 /* Device ID */
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#define TUL_PCMD 0x04 /* Command */
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#define TUL_PSTUS 0x06 /* Status */
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#define TUL_PRID 0x08 /* Revision number */
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#define TUL_PPI 0x09 /* Programming interface */
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#define TUL_PSC 0x0A /* Sub Class */
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#define TUL_PBC 0x0B /* Base Class */
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#define TUL_PCLS 0x0C /* Cache line size */
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#define TUL_PLTR 0x0D /* Latency timer */
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#define TUL_PHDT 0x0E /* Header type */
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#define TUL_PBIST 0x0F /* BIST */
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#define TUL_PBAD 0x10 /* Base address */
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#define TUL_PBAD1 0x14 /* Base address */
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#define TUL_PBAD2 0x18 /* Base address */
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#define TUL_PBAD3 0x1C /* Base address */
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#define TUL_PBAD4 0x20 /* Base address */
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#define TUL_PBAD5 0x24 /* Base address */
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#define TUL_PRSVD 0x28 /* Reserved */
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#define TUL_PRSVD1 0x2C /* Reserved */
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#define TUL_PRAD 0x30 /* Expansion ROM base address */
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#define TUL_PRSVD2 0x34 /* Reserved */
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#define TUL_PRSVD3 0x38 /* Reserved */
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#define TUL_PINTL 0x3C /* Interrupt line */
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#define TUL_PINTP 0x3D /* Interrupt pin */
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#define TUL_PIGNT 0x3E /* MIN_GNT */
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#define TUL_PMGNT 0x3F /* MAX_GNT */
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/************************/
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/* Jasmin Register Set */
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/************************/
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#define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */
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#define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */
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#define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */
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#define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */
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#define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */
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#define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */
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#define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */
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#define TUL_GINTS 0x50 /* Global Interrupt Status Register */
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#define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */
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#define TUL_GCTRL 0x54 /* Global Control Register */
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#define TUL_GCTRL_EEPROM_BIT 0x04
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#define TUL_GCTRL1 0x55 /* Global Control Register */
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#define TUL_DMACFG 0x5B /* DMA configuration */
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#define TUL_NVRAM 0x5D /* Non-volatile RAM port */
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#define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */
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#define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */
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#define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */
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#define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */
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#define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */
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#define TUL_SInt 0x84 /* 04 R Interrupt Register */
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#define TUL_SCtrl0 0x85 /* 05 W Control 0 */
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#define TUL_SStatus0 0x85 /* 05 R Status 0 */
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#define TUL_SCtrl1 0x86 /* 06 W Control 1 */
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#define TUL_SStatus1 0x86 /* 06 R Status 1 */
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#define TUL_SConfig 0x87 /* 07 W Configuration */
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#define TUL_SStatus2 0x87 /* 07 R Status 2 */
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#define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */
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#define TUL_SOffset 0x88 /* 08 R Offset */
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#define TUL_SScsiId 0x89 /* 09 W SCSI ID */
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#define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */
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#define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */
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#define TUL_SIdent 0x8A /* 0A R Identify Message Register */
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#define TUL_SAvail 0x8A /* 0A R Availiable Counter Register */
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#define TUL_SData 0x8B /* 0B R/W SCSI data in/out */
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#define TUL_SFifo 0x8C /* 0C R/W FIFO */
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#define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */
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#define TUL_SCmd 0x91 /* 11 R/W Command */
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#define TUL_STest0 0x92 /* 12 R/W Test0 */
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#define TUL_STest1 0x93 /* 13 R/W Test1 */
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#define TUL_SCFG1 0x94 /* 14 R/W Configuration */
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#define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */
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#define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */
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#define TUL_XCntH 0xD0 /*DMA Transfer Counter */
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#define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */
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#define TUL_XCmd 0xD8 /*DMA Command Register */
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#define TUL_Int 0xDC /*Interrupt Register */
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#define TUL_XStatus 0xDD /*DMA status Register */
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#define TUL_Mask 0xE0 /*Interrupt Mask Register */
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#define TUL_XCtrl 0xE4 /*DMA Control Register */
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#define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */
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#define TUL_XFifo 0xE8 /*DMA FIFO */
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#define TUL_WCtrl 0xF7 /*Bus master wait state control */
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#define TUL_DCtrl 0xFB /*DMA delay control */
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/*----------------------------------------------------------------------*/
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/* bit definition for Command register of Configuration Space Header */
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/*----------------------------------------------------------------------*/
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#define BUSMS 0x04 /* BUS MASTER Enable */
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#define IOSPA 0x01 /* IO Space Enable */
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/*----------------------------------------------------------------------*/
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/* Command Codes of Tulip SCSI Command register */
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/*----------------------------------------------------------------------*/
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#define TSC_EN_RESEL 0x80 /* Enable Reselection */
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#define TSC_CMD_COMP 0x84 /* Command Complete Sequence */
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#define TSC_SEL 0x01 /* Select Without ATN Sequence */
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#define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */
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#define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */
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#define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */
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#define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */
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#define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */
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#define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */
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#define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */
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#define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */
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#define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */
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#define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Infomation out */
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#define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Infomation in */
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#define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */
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#define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */
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#define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */
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#define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */
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#define TSC_MSG_ACCEPT 0x0F /* Message Accept */
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/*----------------------------------------------------------------------*/
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/* bit definition for Tulip SCSI Control 0 Register */
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/*----------------------------------------------------------------------*/
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#define TSC_RST_SEQ 0x20 /* Reset sequence counter */
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#define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */
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#define TSC_ABT_CMD 0x04 /* Abort command (sequence) */
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#define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */
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#define TSC_RST_BUS 0x01 /* Reset SCSI Bus */
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/*----------------------------------------------------------------------*/
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/* bit definition for Tulip SCSI Control 1 Register */
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/*----------------------------------------------------------------------*/
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#define TSC_EN_SCAM 0x80 /* Enable SCAM */
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#define TSC_TIMER 0x40 /* Select timeout unit */
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#define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */
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#define TSC_PWDN 0x10 /* Power down mode */
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#define TSC_WIDE_CPU 0x08 /* Wide CPU */
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#define TSC_HW_RESELECT 0x04 /* Enable HW reselect */
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#define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */
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#define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */
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/*----------------------------------------------------------------------*/
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/* bit definition for Tulip SCSI Configuration Register */
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/*----------------------------------------------------------------------*/
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#define TSC_EN_LATCH 0x80 /* Enable phase latch */
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#define TSC_INITIATOR 0x40 /* Initiator mode */
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#define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */
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#define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */
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#define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */
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#define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */
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#define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */
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#define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */
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#define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST)
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#define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */
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/*----------------------------------------------------------------------*/
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/* bit definition for Tulip SCSI signal Register */
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/*----------------------------------------------------------------------*/
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#define TSC_RST_ACK 0x00 /* Release ACK signal */
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#define TSC_RST_ATN 0x00 /* Release ATN signal */
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#define TSC_RST_BSY 0x00 /* Release BSY signal */
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#define TSC_SET_ACK 0x40 /* ACK signal */
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#define TSC_SET_ATN 0x08 /* ATN signal */
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#define TSC_REQI 0x80 /* REQ signal */
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#define TSC_ACKI 0x40 /* ACK signal */
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#define TSC_BSYI 0x20 /* BSY signal */
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#define TSC_SELI 0x10 /* SEL signal */
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#define TSC_ATNI 0x08 /* ATN signal */
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#define TSC_MSGI 0x04 /* MSG signal */
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#define TSC_CDI 0x02 /* C/D signal */
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#define TSC_IOI 0x01 /* I/O signal */
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/*----------------------------------------------------------------------*/
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/* bit definition for Tulip SCSI Status 0 Register */
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| 284 |
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/*----------------------------------------------------------------------*/
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| 285 |
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#define TSS_INT_PENDING 0x80 /* Interrupt pending */
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| 286 |
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#define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */
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#define TSS_XFER_CNT 0x20 /* Transfer counter zero */
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| 288 |
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#define TSS_FIFO_EMPTY 0x10 /* FIFO empty */
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#define TSS_PAR_ERROR 0x08 /* SCSI parity error */
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| 290 |
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#define TSS_PH_MASK 0x07 /* SCSI phase mask */
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| 291 |
|
|
|
| 292 |
|
|
/*----------------------------------------------------------------------*/
|
| 293 |
|
|
/* bit definition for Tulip SCSI Status 1 Register */
|
| 294 |
|
|
/*----------------------------------------------------------------------*/
|
| 295 |
|
|
#define TSS_STATUS_RCV 0x08 /* Status received */
|
| 296 |
|
|
#define TSS_MSG_SEND 0x40 /* Message sent */
|
| 297 |
|
|
#define TSS_CMD_PH_CMP 0x20 /* command phase done */
|
| 298 |
|
|
#define TSS_DATA_PH_CMP 0x10 /* Data phase done */
|
| 299 |
|
|
#define TSS_STATUS_SEND 0x08 /* Status sent */
|
| 300 |
|
|
#define TSS_XFER_CMP 0x04 /* Transfer completed */
|
| 301 |
|
|
#define TSS_SEL_CMP 0x02 /* Selection completed */
|
| 302 |
|
|
#define TSS_ARB_CMP 0x01 /* Arbitration completed */
|
| 303 |
|
|
|
| 304 |
|
|
/*----------------------------------------------------------------------*/
|
| 305 |
|
|
/* bit definition for Tulip SCSI Status 2 Register */
|
| 306 |
|
|
/*----------------------------------------------------------------------*/
|
| 307 |
|
|
#define TSS_CMD_ABTED 0x80 /* Command aborted */
|
| 308 |
|
|
#define TSS_OFFSET_0 0x40 /* Offset counter zero */
|
| 309 |
|
|
#define TSS_FIFO_FULL 0x20 /* FIFO full */
|
| 310 |
|
|
#define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */
|
| 311 |
|
|
#define TSS_BUSY_RLS 0x08 /* Busy release */
|
| 312 |
|
|
#define TSS_PH_MISMATCH 0x04 /* Phase mismatch */
|
| 313 |
|
|
#define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */
|
| 314 |
|
|
#define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */
|
| 315 |
|
|
|
| 316 |
|
|
/*----------------------------------------------------------------------*/
|
| 317 |
|
|
/* bit definition for Tulip SCSI Interrupt Register */
|
| 318 |
|
|
/*----------------------------------------------------------------------*/
|
| 319 |
|
|
#define TSS_RESEL_INT 0x80 /* Reselected interrupt */
|
| 320 |
|
|
#define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */
|
| 321 |
|
|
#define TSS_BUS_SERV 0x20
|
| 322 |
|
|
#define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */
|
| 323 |
|
|
#define TSS_DISC_INT 0x08 /* Disconnected interrupt */
|
| 324 |
|
|
#define TSS_SEL_INT 0x04 /* Select interrupt */
|
| 325 |
|
|
#define TSS_SCAM_SEL 0x02 /* SCAM selected */
|
| 326 |
|
|
#define TSS_FUNC_COMP 0x01
|
| 327 |
|
|
|
| 328 |
|
|
/*----------------------------------------------------------------------*/
|
| 329 |
|
|
/* SCSI Phase Codes. */
|
| 330 |
|
|
/*----------------------------------------------------------------------*/
|
| 331 |
|
|
#define DATA_OUT 0
|
| 332 |
|
|
#define DATA_IN 1 /* 4 */
|
| 333 |
|
|
#define CMD_OUT 2
|
| 334 |
|
|
#define STATUS_IN 3 /* 6 */
|
| 335 |
|
|
#define MSG_OUT 6 /* 3 */
|
| 336 |
|
|
#define MSG_IN 7
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
/*----------------------------------------------------------------------*/
|
| 341 |
|
|
/* Command Codes of Tulip xfer Command register */
|
| 342 |
|
|
/*----------------------------------------------------------------------*/
|
| 343 |
|
|
#define TAX_X_FORC 0x02
|
| 344 |
|
|
#define TAX_X_ABT 0x04
|
| 345 |
|
|
#define TAX_X_CLR_FIFO 0x08
|
| 346 |
|
|
|
| 347 |
|
|
#define TAX_X_IN 0x21
|
| 348 |
|
|
#define TAX_X_OUT 0x01
|
| 349 |
|
|
#define TAX_SG_IN 0xA1
|
| 350 |
|
|
#define TAX_SG_OUT 0x81
|
| 351 |
|
|
|
| 352 |
|
|
/*----------------------------------------------------------------------*/
|
| 353 |
|
|
/* Tulip Interrupt Register */
|
| 354 |
|
|
/*----------------------------------------------------------------------*/
|
| 355 |
|
|
#define XCMP 0x01
|
| 356 |
|
|
#define FCMP 0x02
|
| 357 |
|
|
#define XABT 0x04
|
| 358 |
|
|
#define XERR 0x08
|
| 359 |
|
|
#define SCMP 0x10
|
| 360 |
|
|
#define IPEND 0x80
|
| 361 |
|
|
|
| 362 |
|
|
/*----------------------------------------------------------------------*/
|
| 363 |
|
|
/* Tulip DMA Status Register */
|
| 364 |
|
|
/*----------------------------------------------------------------------*/
|
| 365 |
|
|
#define XPEND 0x01 /* Transfer pending */
|
| 366 |
|
|
#define FEMPTY 0x02 /* FIFO empty */
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
/*----------------------------------------------------------------------*/
|
| 371 |
|
|
/* bit definition for TUL_GCTRL */
|
| 372 |
|
|
/*----------------------------------------------------------------------*/
|
| 373 |
|
|
#define EXTSG 0x80
|
| 374 |
|
|
#define EXTAD 0x60
|
| 375 |
|
|
#define SEG4K 0x08
|
| 376 |
|
|
#define EEPRG 0x04
|
| 377 |
|
|
#define MRMUL 0x02
|
| 378 |
|
|
|
| 379 |
|
|
/*----------------------------------------------------------------------*/
|
| 380 |
|
|
/* bit definition for TUL_NVRAM */
|
| 381 |
|
|
/*----------------------------------------------------------------------*/
|
| 382 |
|
|
#define SE2CS 0x08
|
| 383 |
|
|
#define SE2CLK 0x04
|
| 384 |
|
|
#define SE2DO 0x02
|
| 385 |
|
|
#define SE2DI 0x01
|
| 386 |
|
|
|
| 387 |
|
|
|
| 388 |
|
|
/************************************************************************/
|
| 389 |
|
|
/* Scatter-Gather Element Structure */
|
| 390 |
|
|
/************************************************************************/
|
| 391 |
|
|
typedef struct SG_Struc {
|
| 392 |
|
|
U32 SG_Ptr; /* Data Pointer */
|
| 393 |
|
|
U32 SG_Len; /* Data Length */
|
| 394 |
|
|
} SG;
|
| 395 |
|
|
|
| 396 |
|
|
/***********************************************************************
|
| 397 |
|
|
SCSI Control Block
|
| 398 |
|
|
************************************************************************/
|
| 399 |
|
|
typedef struct Scsi_Ctrl_Blk {
|
| 400 |
|
|
struct Scsi_Ctrl_Blk *SCB_NxtScb;
|
| 401 |
|
|
UBYTE SCB_Status; /*4 */
|
| 402 |
|
|
UBYTE SCB_NxtStat; /*5 */
|
| 403 |
|
|
UBYTE SCB_Mode; /*6 */
|
| 404 |
|
|
UBYTE SCB_Msgin; /*7 SCB_Res0 */
|
| 405 |
|
|
UWORD SCB_SGIdx; /*8 */
|
| 406 |
|
|
UWORD SCB_SGMax; /*A */
|
| 407 |
|
|
#ifdef ALPHA
|
| 408 |
|
|
U32 SCB_Reserved[2]; /*C */
|
| 409 |
|
|
#else
|
| 410 |
|
|
U32 SCB_Reserved[3]; /*C */
|
| 411 |
|
|
#endif
|
| 412 |
|
|
|
| 413 |
|
|
U32 SCB_XferLen; /*18 Current xfer len */
|
| 414 |
|
|
U32 SCB_TotXLen; /*1C Total xfer len */
|
| 415 |
|
|
U32 SCB_PAddr; /*20 SCB phy. Addr. */
|
| 416 |
|
|
|
| 417 |
|
|
UBYTE SCB_Opcode; /*24 SCB command code */
|
| 418 |
|
|
UBYTE SCB_Flags; /*25 SCB Flags */
|
| 419 |
|
|
UBYTE SCB_Target; /*26 Target Id */
|
| 420 |
|
|
UBYTE SCB_Lun; /*27 Lun */
|
| 421 |
|
|
U32 SCB_BufPtr; /*28 Data Buffer Pointer */
|
| 422 |
|
|
U32 SCB_BufLen; /*2C Data Allocation Length */
|
| 423 |
|
|
UBYTE SCB_SGLen; /*30 SG list # */
|
| 424 |
|
|
UBYTE SCB_SenseLen; /*31 Sense Allocation Length */
|
| 425 |
|
|
UBYTE SCB_HaStat; /*32 */
|
| 426 |
|
|
UBYTE SCB_TaStat; /*33 */
|
| 427 |
|
|
UBYTE SCB_CDBLen; /*34 CDB Length */
|
| 428 |
|
|
UBYTE SCB_Ident; /*35 Identify */
|
| 429 |
|
|
UBYTE SCB_TagMsg; /*36 Tag Message */
|
| 430 |
|
|
UBYTE SCB_TagId; /*37 Queue Tag */
|
| 431 |
|
|
UBYTE SCB_CDB[12]; /*38 */
|
| 432 |
|
|
U32 SCB_SGPAddr; /*44 SG List/Sense Buf phy. Addr. */
|
| 433 |
|
|
U32 SCB_SensePtr; /*48 Sense data pointer */
|
| 434 |
|
|
void (*SCB_Post) (BYTE *, BYTE *); /*4C POST routine */
|
| 435 |
|
|
unsigned char *SCB_Srb; /*50 SRB Pointer */
|
| 436 |
|
|
SG SCB_SGList[TOTAL_SG_ENTRY]; /*54 Start of SG list */
|
| 437 |
|
|
} SCB;
|
| 438 |
|
|
|
| 439 |
|
|
/* Bit Definition for SCB_Status */
|
| 440 |
|
|
#define SCB_RENT 0x01
|
| 441 |
|
|
#define SCB_PEND 0x02
|
| 442 |
|
|
#define SCB_CONTIG 0x04 /* Contigent Allegiance */
|
| 443 |
|
|
#define SCB_SELECT 0x08
|
| 444 |
|
|
#define SCB_BUSY 0x10
|
| 445 |
|
|
#define SCB_DONE 0x20
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
/* Opcodes of SCB_Opcode */
|
| 449 |
|
|
#define ExecSCSI 0x1
|
| 450 |
|
|
#define BusDevRst 0x2
|
| 451 |
|
|
#define AbortCmd 0x3
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
/* Bit Definition for SCB_Mode */
|
| 455 |
|
|
#define SCM_RSENS 0x01 /* request sense mode */
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
/* Bit Definition for SCB_Flags */
|
| 459 |
|
|
#define SCF_DONE 0x01
|
| 460 |
|
|
#define SCF_POST 0x02
|
| 461 |
|
|
#define SCF_SENSE 0x04
|
| 462 |
|
|
#define SCF_DIR 0x18
|
| 463 |
|
|
#define SCF_NO_DCHK 0x00
|
| 464 |
|
|
#define SCF_DIN 0x08
|
| 465 |
|
|
#define SCF_DOUT 0x10
|
| 466 |
|
|
#define SCF_NO_XF 0x18
|
| 467 |
|
|
#define SCF_WR_VF 0x20 /* Write verify turn on */
|
| 468 |
|
|
#define SCF_POLL 0x40
|
| 469 |
|
|
#define SCF_SG 0x80
|
| 470 |
|
|
|
| 471 |
|
|
/* Error Codes for SCB_HaStat */
|
| 472 |
|
|
#define HOST_SEL_TOUT 0x11
|
| 473 |
|
|
#define HOST_DO_DU 0x12
|
| 474 |
|
|
#define HOST_BUS_FREE 0x13
|
| 475 |
|
|
#define HOST_BAD_PHAS 0x14
|
| 476 |
|
|
#define HOST_INV_CMD 0x16
|
| 477 |
|
|
#define HOST_ABORTED 0x1A /* 07/21/98 */
|
| 478 |
|
|
#define HOST_SCSI_RST 0x1B
|
| 479 |
|
|
#define HOST_DEV_RST 0x1C
|
| 480 |
|
|
|
| 481 |
|
|
/* Error Codes for SCB_TaStat */
|
| 482 |
|
|
#define TARGET_CHKCOND 0x02
|
| 483 |
|
|
#define TARGET_BUSY 0x08
|
| 484 |
|
|
#define QUEUE_FULL 0x28
|
| 485 |
|
|
|
| 486 |
|
|
/* SCSI MESSAGE */
|
| 487 |
|
|
#define MSG_COMP 0x00
|
| 488 |
|
|
#define MSG_EXTEND 0x01
|
| 489 |
|
|
#define MSG_SDP 0x02
|
| 490 |
|
|
#define MSG_RESTORE 0x03
|
| 491 |
|
|
#define MSG_DISC 0x04
|
| 492 |
|
|
#define MSG_IDE 0x05
|
| 493 |
|
|
#define MSG_ABORT 0x06
|
| 494 |
|
|
#define MSG_REJ 0x07
|
| 495 |
|
|
#define MSG_NOP 0x08
|
| 496 |
|
|
#define MSG_PARITY 0x09
|
| 497 |
|
|
#define MSG_LINK_COMP 0x0A
|
| 498 |
|
|
#define MSG_LINK_FLAG 0x0B
|
| 499 |
|
|
#define MSG_DEVRST 0x0C
|
| 500 |
|
|
#define MSG_ABORT_TAG 0x0D
|
| 501 |
|
|
|
| 502 |
|
|
/* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
|
| 503 |
|
|
#define MSG_STAG 0x20
|
| 504 |
|
|
#define MSG_HTAG 0x21
|
| 505 |
|
|
#define MSG_OTAG 0x22
|
| 506 |
|
|
|
| 507 |
|
|
#define MSG_IGNOREWIDE 0x23
|
| 508 |
|
|
|
| 509 |
|
|
#define MSG_IDENT 0x80
|
| 510 |
|
|
|
| 511 |
|
|
/***********************************************************************
|
| 512 |
|
|
Target Device Control Structure
|
| 513 |
|
|
**********************************************************************/
|
| 514 |
|
|
|
| 515 |
|
|
typedef struct Tar_Ctrl_Struc {
|
| 516 |
|
|
UWORD TCS_Flags; /* 0 */
|
| 517 |
|
|
UBYTE TCS_JS_Period; /* 2 */
|
| 518 |
|
|
UBYTE TCS_SConfig0; /* 3 */
|
| 519 |
|
|
|
| 520 |
|
|
UWORD TCS_DrvFlags; /* 4 */
|
| 521 |
|
|
UBYTE TCS_DrvHead; /* 6 */
|
| 522 |
|
|
UBYTE TCS_DrvSector; /* 7 */
|
| 523 |
|
|
} TCS;
|
| 524 |
|
|
|
| 525 |
|
|
/***********************************************************************
|
| 526 |
|
|
Target Device Control Structure
|
| 527 |
|
|
**********************************************************************/
|
| 528 |
|
|
|
| 529 |
|
|
/* Bit Definition for TCF_Flags */
|
| 530 |
|
|
#define TCF_SCSI_RATE 0x0007
|
| 531 |
|
|
#define TCF_EN_DISC 0x0008
|
| 532 |
|
|
#define TCF_NO_SYNC_NEGO 0x0010
|
| 533 |
|
|
#define TCF_NO_WDTR 0x0020
|
| 534 |
|
|
#define TCF_EN_255 0x0040
|
| 535 |
|
|
#define TCF_EN_START 0x0080
|
| 536 |
|
|
#define TCF_WDTR_DONE 0x0100
|
| 537 |
|
|
#define TCF_SYNC_DONE 0x0200
|
| 538 |
|
|
#define TCF_BUSY 0x0400
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
/* Bit Definition for TCF_DrvFlags */
|
| 542 |
|
|
#define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */
|
| 543 |
|
|
#define TCF_DRV_EN_TAG 0x0800
|
| 544 |
|
|
#define TCF_DRV_255_63 0x0400
|
| 545 |
|
|
|
| 546 |
|
|
typedef struct I91u_Adpt_Struc {
|
| 547 |
|
|
UWORD ADPT_BIOS; /* 0 */
|
| 548 |
|
|
UWORD ADPT_BASE; /* 1 */
|
| 549 |
|
|
UBYTE ADPT_Bus; /* 2 */
|
| 550 |
|
|
UBYTE ADPT_Device; /* 3 */
|
| 551 |
|
|
UBYTE ADPT_INTR; /* 4 */
|
| 552 |
|
|
} INI_ADPT_STRUCT;
|
| 553 |
|
|
|
| 554 |
|
|
|
| 555 |
|
|
/***********************************************************************
|
| 556 |
|
|
Host Adapter Control Structure
|
| 557 |
|
|
************************************************************************/
|
| 558 |
|
|
typedef struct Ha_Ctrl_Struc {
|
| 559 |
|
|
UWORD HCS_Base; /* 00 */
|
| 560 |
|
|
UWORD HCS_BIOS; /* 02 */
|
| 561 |
|
|
UBYTE HCS_Intr; /* 04 */
|
| 562 |
|
|
UBYTE HCS_SCSI_ID; /* 05 */
|
| 563 |
|
|
UBYTE HCS_MaxTar; /* 06 */
|
| 564 |
|
|
UBYTE HCS_NumScbs; /* 07 */
|
| 565 |
|
|
|
| 566 |
|
|
UBYTE HCS_Flags; /* 08 */
|
| 567 |
|
|
UBYTE HCS_Index; /* 09 */
|
| 568 |
|
|
UBYTE HCS_HaId; /* 0A */
|
| 569 |
|
|
UBYTE HCS_Config; /* 0B */
|
| 570 |
|
|
UWORD HCS_IdMask; /* 0C */
|
| 571 |
|
|
UBYTE HCS_Semaph; /* 0E */
|
| 572 |
|
|
UBYTE HCS_Phase; /* 0F */
|
| 573 |
|
|
UBYTE HCS_JSStatus0; /* 10 */
|
| 574 |
|
|
UBYTE HCS_JSInt; /* 11 */
|
| 575 |
|
|
UBYTE HCS_JSStatus1; /* 12 */
|
| 576 |
|
|
UBYTE HCS_SConf1; /* 13 */
|
| 577 |
|
|
|
| 578 |
|
|
UBYTE HCS_Msg[8]; /* 14 */
|
| 579 |
|
|
SCB *HCS_NxtAvail; /* 1C */
|
| 580 |
|
|
SCB *HCS_Scb; /* 20 */
|
| 581 |
|
|
SCB *HCS_ScbEnd; /* 24 */
|
| 582 |
|
|
SCB *HCS_NxtPend; /* 28 */
|
| 583 |
|
|
SCB *HCS_NxtContig; /* 2C */
|
| 584 |
|
|
SCB *HCS_ActScb; /* 30 */
|
| 585 |
|
|
TCS *HCS_ActTcs; /* 34 */
|
| 586 |
|
|
|
| 587 |
|
|
SCB *HCS_FirstAvail; /* 38 */
|
| 588 |
|
|
SCB *HCS_LastAvail; /* 3C */
|
| 589 |
|
|
SCB *HCS_FirstPend; /* 40 */
|
| 590 |
|
|
SCB *HCS_LastPend; /* 44 */
|
| 591 |
|
|
SCB *HCS_FirstBusy; /* 48 */
|
| 592 |
|
|
SCB *HCS_LastBusy; /* 4C */
|
| 593 |
|
|
SCB *HCS_FirstDone; /* 50 */
|
| 594 |
|
|
SCB *HCS_LastDone; /* 54 */
|
| 595 |
|
|
UBYTE HCS_MaxTags[16]; /* 58 */
|
| 596 |
|
|
UBYTE HCS_ActTags[16]; /* 68 */
|
| 597 |
|
|
TCS HCS_Tcs[MAX_TARGETS]; /* 78 */
|
| 598 |
|
|
ULONG pSRB_head; /* SRB save queue header */
|
| 599 |
|
|
ULONG pSRB_tail; /* SRB save queue tail */
|
| 600 |
|
|
#if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
|
| 601 |
|
|
spinlock_t HCS_AvailLock;
|
| 602 |
|
|
spinlock_t HCS_SemaphLock;
|
| 603 |
|
|
spinlock_t pSRB_lock; /* SRB queue lock */
|
| 604 |
|
|
#endif
|
| 605 |
|
|
} HCS;
|
| 606 |
|
|
|
| 607 |
|
|
/* Bit Definition for HCB_Config */
|
| 608 |
|
|
#define HCC_SCSI_RESET 0x01
|
| 609 |
|
|
#define HCC_EN_PAR 0x02
|
| 610 |
|
|
#define HCC_ACT_TERM1 0x04
|
| 611 |
|
|
#define HCC_ACT_TERM2 0x08
|
| 612 |
|
|
#define HCC_AUTO_TERM 0x10
|
| 613 |
|
|
#define HCC_EN_PWR 0x80
|
| 614 |
|
|
|
| 615 |
|
|
/* Bit Definition for HCB_Flags */
|
| 616 |
|
|
#define HCF_EXPECT_DISC 0x01
|
| 617 |
|
|
#define HCF_EXPECT_SELECT 0x02
|
| 618 |
|
|
#define HCF_EXPECT_RESET 0x10
|
| 619 |
|
|
#define HCF_EXPECT_DONE_DISC 0x20
|
| 620 |
|
|
|
| 621 |
|
|
/******************************************************************
|
| 622 |
|
|
Serial EEProm
|
| 623 |
|
|
*******************************************************************/
|
| 624 |
|
|
|
| 625 |
|
|
typedef struct _NVRAM_SCSI { /* SCSI channel configuration */
|
| 626 |
|
|
UCHAR NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */
|
| 627 |
|
|
UCHAR NVM_ChConfig1; /* 0Dh -> Channel config 1 */
|
| 628 |
|
|
UCHAR NVM_ChConfig2; /* 0Eh -> Channel config 2 */
|
| 629 |
|
|
UCHAR NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */
|
| 630 |
|
|
/* SCSI target configuration */
|
| 631 |
|
|
UCHAR NVM_Targ0Config; /* 10h -> Target 0 configuration */
|
| 632 |
|
|
UCHAR NVM_Targ1Config; /* 11h -> Target 1 configuration */
|
| 633 |
|
|
UCHAR NVM_Targ2Config; /* 12h -> Target 2 configuration */
|
| 634 |
|
|
UCHAR NVM_Targ3Config; /* 13h -> Target 3 configuration */
|
| 635 |
|
|
UCHAR NVM_Targ4Config; /* 14h -> Target 4 configuration */
|
| 636 |
|
|
UCHAR NVM_Targ5Config; /* 15h -> Target 5 configuration */
|
| 637 |
|
|
UCHAR NVM_Targ6Config; /* 16h -> Target 6 configuration */
|
| 638 |
|
|
UCHAR NVM_Targ7Config; /* 17h -> Target 7 configuration */
|
| 639 |
|
|
UCHAR NVM_Targ8Config; /* 18h -> Target 8 configuration */
|
| 640 |
|
|
UCHAR NVM_Targ9Config; /* 19h -> Target 9 configuration */
|
| 641 |
|
|
UCHAR NVM_TargAConfig; /* 1Ah -> Target A configuration */
|
| 642 |
|
|
UCHAR NVM_TargBConfig; /* 1Bh -> Target B configuration */
|
| 643 |
|
|
UCHAR NVM_TargCConfig; /* 1Ch -> Target C configuration */
|
| 644 |
|
|
UCHAR NVM_TargDConfig; /* 1Dh -> Target D configuration */
|
| 645 |
|
|
UCHAR NVM_TargEConfig; /* 1Eh -> Target E configuration */
|
| 646 |
|
|
UCHAR NVM_TargFConfig; /* 1Fh -> Target F configuration */
|
| 647 |
|
|
} NVRAM_SCSI;
|
| 648 |
|
|
|
| 649 |
|
|
typedef struct _NVRAM {
|
| 650 |
|
|
/*----------header ---------------*/
|
| 651 |
|
|
USHORT NVM_Signature; /* 0,1: Signature */
|
| 652 |
|
|
UCHAR NVM_Size; /* 2: Size of data structure */
|
| 653 |
|
|
UCHAR NVM_Revision; /* 3: Revision of data structure */
|
| 654 |
|
|
/* ----Host Adapter Structure ---- */
|
| 655 |
|
|
UCHAR NVM_ModelByte0; /* 4: Model number (byte 0) */
|
| 656 |
|
|
UCHAR NVM_ModelByte1; /* 5: Model number (byte 1) */
|
| 657 |
|
|
UCHAR NVM_ModelInfo; /* 6: Model information */
|
| 658 |
|
|
UCHAR NVM_NumOfCh; /* 7: Number of SCSI channel */
|
| 659 |
|
|
UCHAR NVM_BIOSConfig1; /* 8: BIOS configuration 1 */
|
| 660 |
|
|
UCHAR NVM_BIOSConfig2; /* 9: BIOS configuration 2 */
|
| 661 |
|
|
UCHAR NVM_HAConfig1; /* A: Hoat adapter configuration 1 */
|
| 662 |
|
|
UCHAR NVM_HAConfig2; /* B: Hoat adapter configuration 2 */
|
| 663 |
|
|
NVRAM_SCSI NVM_SCSIInfo[2];
|
| 664 |
|
|
UCHAR NVM_reserved[10];
|
| 665 |
|
|
/* ---------- CheckSum ---------- */
|
| 666 |
|
|
USHORT NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */
|
| 667 |
|
|
} NVRAM, *PNVRAM;
|
| 668 |
|
|
|
| 669 |
|
|
/* Bios Configuration for nvram->BIOSConfig1 */
|
| 670 |
|
|
#define NBC1_ENABLE 0x01 /* BIOS enable */
|
| 671 |
|
|
#define NBC1_8DRIVE 0x02 /* Support more than 2 drives */
|
| 672 |
|
|
#define NBC1_REMOVABLE 0x04 /* Support removable drive */
|
| 673 |
|
|
#define NBC1_INT19 0x08 /* Intercept int 19h */
|
| 674 |
|
|
#define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */
|
| 675 |
|
|
#define NBC1_LUNSUPPORT 0x40 /* Support LUN */
|
| 676 |
|
|
|
| 677 |
|
|
/* HA Configuration Byte 1 */
|
| 678 |
|
|
#define NHC1_BOOTIDMASK 0x0F /* Boot ID number */
|
| 679 |
|
|
#define NHC1_LUNMASK 0x70 /* Boot LUN number */
|
| 680 |
|
|
#define NHC1_CHANMASK 0x80 /* Boot Channel number */
|
| 681 |
|
|
|
| 682 |
|
|
/* Bit definition for nvram->SCSIconfig1 */
|
| 683 |
|
|
#define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */
|
| 684 |
|
|
#define NCC1_PARITYCHK 0x02 /* SCSI parity enable */
|
| 685 |
|
|
#define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */
|
| 686 |
|
|
#define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */
|
| 687 |
|
|
#define NCC1_AUTOTERM 0x10 /* Enable auto terminator */
|
| 688 |
|
|
#define NCC1_PWRMGR 0x80 /* Enable power management */
|
| 689 |
|
|
|
| 690 |
|
|
/* Bit definition for SCSI Target configuration byte */
|
| 691 |
|
|
#define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */
|
| 692 |
|
|
#define NTC_SYNC 0x10 /* SYNC_NEGO */
|
| 693 |
|
|
#define NTC_NO_WDTR 0x20 /* SYNC_NEGO */
|
| 694 |
|
|
#define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */
|
| 695 |
|
|
#define NTC_SPINUP 0x80 /* Start disk drive */
|
| 696 |
|
|
|
| 697 |
|
|
/* Default NVRam values */
|
| 698 |
|
|
#define INI_SIGNATURE 0xC925
|
| 699 |
|
|
#define NBC1_DEFAULT (NBC1_ENABLE)
|
| 700 |
|
|
#define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK)
|
| 701 |
|
|
#define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT)
|
| 702 |
|
|
|
| 703 |
|
|
/* SCSI related definition */
|
| 704 |
|
|
#define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
|
| 705 |
|
|
#define DISC_ALLOW 0xC0 /* Disconnect is allowed */
|
| 706 |
|
|
#define SCSICMD_RequestSense 0x03
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
/*----------------------------------------------------------------------*/
|
| 710 |
|
|
/* PCI */
|
| 711 |
|
|
/*----------------------------------------------------------------------*/
|
| 712 |
|
|
#define PCI_FUNCTION_ID 0xB1
|
| 713 |
|
|
#define PCI_BIOS_PRESENT 0x01
|
| 714 |
|
|
#define FIND_PCI_DEVICE 0x02
|
| 715 |
|
|
#define FIND_PCI_CLASS_CODE 0x03
|
| 716 |
|
|
#define GENERATE_SPECIAL_CYCLE 0x06
|
| 717 |
|
|
#define READ_CONFIG_BYTE 0x08
|
| 718 |
|
|
#define READ_CONFIG_WORD 0x09
|
| 719 |
|
|
#define READ_CONFIG_DWORD 0x0A
|
| 720 |
|
|
#define WRITE_CONFIG_BYTE 0x0B
|
| 721 |
|
|
#define WRITE_CONFIG_WORD 0x0C
|
| 722 |
|
|
#define WRITE_CONFIG_DWORD 0x0D
|
| 723 |
|
|
|
| 724 |
|
|
#define SUCCESSFUL 0x00
|
| 725 |
|
|
#define FUNC_NOT_SUPPORTED 0x81
|
| 726 |
|
|
#define BAD_VENDOR_ID 0x83 /* Bad vendor ID */
|
| 727 |
|
|
#define DEVICE_NOT_FOUND 0x86 /* PCI device not found */
|
| 728 |
|
|
#define BAD_REGISTER_NUMBER 0x87
|
| 729 |
|
|
|
| 730 |
|
|
#define MAX_PCI_DEVICES 21 /* Maximum devices supportted */
|
| 731 |
|
|
|
| 732 |
|
|
#define MAX_PCI_CHANL 4
|
| 733 |
|
|
|
| 734 |
|
|
typedef struct _BIOS32_ENTRY_STRUCTURE {
|
| 735 |
|
|
DWORD Signatures; /* Should be "_32_" */
|
| 736 |
|
|
DWORD BIOS32Entry; /* 32-bit physical address */
|
| 737 |
|
|
BYTE Revision; /* Revision level, should be 0 */
|
| 738 |
|
|
BYTE Length; /* Multiply of 16, should be 1 */
|
| 739 |
|
|
BYTE CheckSum; /* Checksum of whole structure */
|
| 740 |
|
|
BYTE Reserved[5]; /* Reserved */
|
| 741 |
|
|
} BIOS32_ENTRY_STRUCTURE, *PBIOS32_ENTRY_STRUCTURE;
|
| 742 |
|
|
|
| 743 |
|
|
typedef struct {
|
| 744 |
|
|
union {
|
| 745 |
|
|
unsigned int eax;
|
| 746 |
|
|
struct {
|
| 747 |
|
|
unsigned short ax;
|
| 748 |
|
|
} word;
|
| 749 |
|
|
struct {
|
| 750 |
|
|
unsigned char al;
|
| 751 |
|
|
unsigned char ah;
|
| 752 |
|
|
} byte;
|
| 753 |
|
|
} eax;
|
| 754 |
|
|
union {
|
| 755 |
|
|
unsigned int ebx;
|
| 756 |
|
|
struct {
|
| 757 |
|
|
unsigned short bx;
|
| 758 |
|
|
} word;
|
| 759 |
|
|
struct {
|
| 760 |
|
|
unsigned char bl;
|
| 761 |
|
|
unsigned char bh;
|
| 762 |
|
|
} byte;
|
| 763 |
|
|
} ebx;
|
| 764 |
|
|
union {
|
| 765 |
|
|
unsigned int ecx;
|
| 766 |
|
|
struct {
|
| 767 |
|
|
unsigned short cx;
|
| 768 |
|
|
} word;
|
| 769 |
|
|
struct {
|
| 770 |
|
|
unsigned char cl;
|
| 771 |
|
|
unsigned char ch;
|
| 772 |
|
|
} byte;
|
| 773 |
|
|
} ecx;
|
| 774 |
|
|
union {
|
| 775 |
|
|
unsigned int edx;
|
| 776 |
|
|
struct {
|
| 777 |
|
|
unsigned short dx;
|
| 778 |
|
|
} word;
|
| 779 |
|
|
struct {
|
| 780 |
|
|
unsigned char dl;
|
| 781 |
|
|
unsigned char dh;
|
| 782 |
|
|
} byte;
|
| 783 |
|
|
} edx;
|
| 784 |
|
|
union {
|
| 785 |
|
|
unsigned int edi;
|
| 786 |
|
|
struct {
|
| 787 |
|
|
unsigned short di;
|
| 788 |
|
|
} word;
|
| 789 |
|
|
} edi;
|
| 790 |
|
|
union {
|
| 791 |
|
|
unsigned int esi;
|
| 792 |
|
|
struct {
|
| 793 |
|
|
unsigned short si;
|
| 794 |
|
|
} word;
|
| 795 |
|
|
} esi;
|
| 796 |
|
|
} REGS;
|
| 797 |
|
|
|
| 798 |
|
|
typedef union { /* Union define for mechanism 1 */
|
| 799 |
|
|
struct {
|
| 800 |
|
|
unsigned char RegNum;
|
| 801 |
|
|
unsigned char FcnNum:3;
|
| 802 |
|
|
unsigned char DeviceNum:5;
|
| 803 |
|
|
unsigned char BusNum;
|
| 804 |
|
|
unsigned char Reserved:7;
|
| 805 |
|
|
unsigned char Enable:1;
|
| 806 |
|
|
} sConfigAdr;
|
| 807 |
|
|
unsigned long lConfigAdr;
|
| 808 |
|
|
} CONFIG_ADR;
|
| 809 |
|
|
|
| 810 |
|
|
typedef union { /* Union define for mechanism 2 */
|
| 811 |
|
|
struct {
|
| 812 |
|
|
unsigned char RegNum;
|
| 813 |
|
|
unsigned char DeviceNum;
|
| 814 |
|
|
unsigned short Reserved;
|
| 815 |
|
|
} sHostAdr;
|
| 816 |
|
|
unsigned long lHostAdr;
|
| 817 |
|
|
} HOST_ADR;
|
| 818 |
|
|
|
| 819 |
|
|
typedef struct _HCSinfo {
|
| 820 |
|
|
ULONG base;
|
| 821 |
|
|
UCHAR vec;
|
| 822 |
|
|
UCHAR bios; /* High byte of BIOS address */
|
| 823 |
|
|
USHORT BaseAndBios; /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */
|
| 824 |
|
|
} HCSINFO;
|
| 825 |
|
|
|
| 826 |
|
|
#define TUL_RD(x,y) (UCHAR)(inb( (int)((ULONG)(x+y)) ))
|
| 827 |
|
|
#define TUL_RDLONG(x,y) (ULONG)(inl((int)((ULONG)(x+y)) ))
|
| 828 |
|
|
#define TUL_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
|
| 829 |
|
|
#define TUL_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
|
| 830 |
|
|
#define TUL_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
|
| 831 |
|
|
|
| 832 |
|
|
#define SCSI_ABORT_SNOOZE 0
|
| 833 |
|
|
#define SCSI_ABORT_SUCCESS 1
|
| 834 |
|
|
#define SCSI_ABORT_PENDING 2
|
| 835 |
|
|
#define SCSI_ABORT_BUSY 3
|
| 836 |
|
|
#define SCSI_ABORT_NOT_RUNNING 4
|
| 837 |
|
|
#define SCSI_ABORT_ERROR 5
|
| 838 |
|
|
|
| 839 |
|
|
#define SCSI_RESET_SNOOZE 0
|
| 840 |
|
|
#define SCSI_RESET_PUNT 1
|
| 841 |
|
|
#define SCSI_RESET_SUCCESS 2
|
| 842 |
|
|
#define SCSI_RESET_PENDING 3
|
| 843 |
|
|
#define SCSI_RESET_WAKEUP 4
|
| 844 |
|
|
#define SCSI_RESET_NOT_RUNNING 5
|
| 845 |
|
|
#define SCSI_RESET_ERROR 6
|
| 846 |
|
|
|
| 847 |
|
|
#define SCSI_RESET_SYNCHRONOUS 0x01
|
| 848 |
|
|
#define SCSI_RESET_ASYNCHRONOUS 0x02
|
| 849 |
|
|
#define SCSI_RESET_SUGGEST_BUS_RESET 0x04
|
| 850 |
|
|
#define SCSI_RESET_SUGGEST_HOST_RESET 0x08
|
| 851 |
|
|
|
| 852 |
|
|
#define SCSI_RESET_BUS_RESET 0x100
|
| 853 |
|
|
#define SCSI_RESET_HOST_RESET 0x200
|
| 854 |
|
|
#define SCSI_RESET_ACTION 0xff
|
