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1275 |
phoenix |
/*****************************************************************************/
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/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
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/* */
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/* Written By: Keith Mitchell, IBM Corporation */
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/* Jack Hammer, Adaptec, Inc. */
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/* David Jeffery, Adaptec, Inc. */
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/* */
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/* Copyright (C) 2000 IBM Corporation */
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/* Copyright (C) 2002,2003 Adaptec, Inc. */
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/* */
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/* This program is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU General Public License as published by */
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/* the Free Software Foundation; either version 2 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This program is distributed in the hope that it will be useful, */
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/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
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/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
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/* GNU General Public License for more details. */
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/* */
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/* NO WARRANTY */
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/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
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/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
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/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
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/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
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/* solely responsible for determining the appropriateness of using and */
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/* distributing the Program and assumes all risks associated with its */
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/* exercise of rights under this Agreement, including but not limited to */
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/* the risks and costs of program errors, damage to or loss of data, */
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/* programs or equipment, and unavailability or interruption of operations. */
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/* */
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/* DISCLAIMER OF LIABILITY */
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/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
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/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
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/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
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/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
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/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
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/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
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/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
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/* */
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/* You should have received a copy of the GNU General Public License */
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/* along with this program; if not, write to the Free Software */
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/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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/* */
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/* Bugs/Comments/Suggestions about this driver should be mailed to: */
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/* ipslinux@adaptec.com */
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/* */
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/* For system support issues, contact your local IBM Customer support. */
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/* Directions to find IBM Customer Support for each country can be found at: */
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/* http://www.ibm.com/planetwide/ */
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/* */
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/*****************************************************************************/
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/*****************************************************************************/
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/* Change Log */
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/* */
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/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
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/* 0.99.03 - Make interrupt routine handle all completed request on the */
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/* adapter not just the first one */
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/* - Make sure passthru commands get woken up if we run out of */
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/* SCBs */
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/* - Send all of the commands on the queue at once rather than */
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/* one at a time since the card will support it. */
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/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
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/* the interface to the utilities to change */
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/* - Fix error recovery code */
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/* 0.99.05 - Fix an oops when we get certain passthru commands */
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/* 1.00.00 - Initial Public Release */
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/* Functionally equivalent to 0.99.05 */
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/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
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/* - Change version to 3.60 to coincide with release numbering. */
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/* 3.60.01 - Remove bogus error check in passthru routine */
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/* 3.60.02 - Make DCDB direction based on lookup table */
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/* - Only allow one DCDB command to a SCSI ID at a time */
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/* 4.00.00 - Add support for ServeRAID 4 */
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/* 4.00.01 - Add support for First Failure Data Capture */
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/* 4.00.02 - Fix problem with PT DCDB with no buffer */
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/* 4.00.03 - Add alternative passthru interface */
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/* - Add ability to flash BIOS */
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/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
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/* 4.00.05 - Remove wish_block from init routine */
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/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
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/* 2.3.18 and later */
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/* - Sync with other changes from the 2.3 kernels */
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/* 4.00.06 - Fix timeout with initial FFDC command */
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/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
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/* 4.10.00 - Add support for ServeRAID 4M/4L */
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/* 4.10.13 - Fix for dynamic unload and proc file system */
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/* 4.20.03 - Rename version to coincide with new release schedules */
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/* Performance fixes */
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/* Fix truncation of /proc files with cat */
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/* Merge in changes through kernel 2.4.0test1ac21 */
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/* 4.20.13 - Fix some failure cases / reset code */
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/* - Hook into the reboot_notifier to flush the controller cache */
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/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
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/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
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/* - Add IPSSEND Flash Support */
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/* - Set Sense Data for Unknown SCSI Command */
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/* - Use Slot Number from NVRAM Page 5 */
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/* - Restore caller's DCDB Structure */
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/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
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/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
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/* - Don't release HA Lock in ips_next() until SC taken off queue */
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/* - Unregister SCSI device in ips_release() */
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/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
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/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
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/* Code Clean-Up for 2.4.x kernel */
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/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
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/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
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/* - Don't Issue Internal FFDC Command if there are Active Commands */
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/* - Close Window for getting too many IOCTL's active */
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/* 4.80.00 - Make ia64 Safe */
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/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
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/* - Adjustments to Device Queue Depth */
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/* 4.80.14 - Take all semaphores off stack */
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/* - Clean Up New_IOCTL path */
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/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
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/* - 5 second delay needed after resetting an i960 adapter */
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/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
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/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
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/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
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/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
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/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
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/* 4.90.11 - Don't actually RESET unless it's physically required */
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/* - Remove unused compile options */
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/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
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/* - Get rid on IOCTL_NEW_COMMAND code */
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/* - Add Extended DCDB Commands for Tape Support in 5I */
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/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
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/* 5.10.15 - remove unused code (sem, macros, etc.) */
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/* 5.30.00 - use __devexit_p() */
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/* 6.00.00 - Add 6x Adapters and Battery Flash */
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/* 6.10.00 - Remove 1G Addressing Limitations */
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/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
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/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
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/*****************************************************************************/
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/*
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* Conditional Compilation directives for this driver:
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*
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* IPS_DEBUG - Turn on debugging info
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*
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* Parameters:
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*
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* debug:<number> - Set debug level to <number>
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* NOTE: only works when IPS_DEBUG compile directive is used.
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* 1 - Normal debug messages
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* 2 - Verbose debug messages
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* 11 - Method trace (non interrupt)
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* 12 - Method trace (includes interrupt)
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*
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* noi2o - Don't use I2O Queues (ServeRAID 4 only)
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* nommap - Don't use memory mapped I/O
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* ioctlsize - Initial size of the IOCTL buffer
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*/
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <linux/stddef.h>
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#include <linux/version.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <linux/blk.h>
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#include <linux/types.h>
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#include <scsi/sg.h>
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#include "sd.h"
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#include "scsi.h"
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#include "hosts.h"
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#include "ips.h"
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#include <linux/module.h>
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#include <linux/stat.h>
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#include <linux/config.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#ifdef MODULE
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static char *ips = NULL;
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MODULE_PARM(ips, "s");
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#endif
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/*
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* DRIVER_VER
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*/
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#define IPS_VERSION_HIGH "6.11"
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#define IPS_VERSION_LOW ".07 "
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#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
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#warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
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#endif
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#if LINUX_VERSION_CODE <= LinuxVersionCode(2,5,0)
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#define IPS_SG_ADDRESS(sg) ((sg)->address)
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#define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
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#define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
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#else
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#define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
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page_address((sg)->page)+(sg)->offset : 0)
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#define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
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#define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
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#endif
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#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
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SCSI_DATA_NONE == scb->scsi_cmd->sc_data_direction) ? \
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PCI_DMA_BIDIRECTIONAL : \
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scsi_to_pci_dma_dir(scb->scsi_cmd->sc_data_direction))
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#ifdef IPS_DEBUG
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#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
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#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
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#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
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#else
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#define METHOD_TRACE(s, i)
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#define DEBUG(i, s)
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#define DEBUG_VAR(i, s, v...)
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#endif
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/*
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* global variables
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*/
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static const char ips_name[] = "ips";
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static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
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static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
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static unsigned int ips_next_controller;
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static unsigned int ips_num_controllers;
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static unsigned int ips_released_controllers;
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static int ips_cmd_timeout = 60;
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| 244 |
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static int ips_reset_timeout = 60 * 5;
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| 245 |
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static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
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| 246 |
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static int ips_force_i2o = 1; /* Always use I2O command delivery */
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static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
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| 248 |
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static int ips_cd_boot; /* Booting from Manager CD */
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| 249 |
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static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
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| 250 |
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static dma_addr_t ips_flashbusaddr;
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| 251 |
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static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
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| 252 |
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static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
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| 253 |
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static Scsi_Host_Template ips_driver_template = IPS;
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| 254 |
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| 255 |
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IPS_DEFINE_COMPAT_TABLE(Compatable); /* Version Compatability Table */
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| 256 |
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| 257 |
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/* This table describes all ServeRAID Adapters */
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| 258 |
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static struct pci_device_id ips_pci_table[] __devinitdata = {
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| 259 |
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{0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0},
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{0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0},
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{0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0},
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| 262 |
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{0,}
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| 263 |
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};
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| 264 |
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| 265 |
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MODULE_DEVICE_TABLE(pci, ips_pci_table);
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| 266 |
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| 267 |
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static char ips_hot_plug_name[] = "ips";
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| 268 |
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| 269 |
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static int __devinit ips_insert_device(struct pci_dev *pci_dev,
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| 270 |
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const struct pci_device_id *ent);
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| 271 |
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static void ips_remove_device(struct pci_dev *pci_dev);
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| 272 |
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| 273 |
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struct pci_driver ips_pci_driver = {
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| 274 |
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.name = ips_hot_plug_name,
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| 275 |
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.id_table = ips_pci_table,
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| 276 |
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.probe = ips_insert_device,
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.remove = ips_remove_device,
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| 278 |
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};
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| 279 |
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| 280 |
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/*
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| 281 |
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* Necessary forward function protoypes
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| 282 |
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*/
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| 283 |
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static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
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| 284 |
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| 285 |
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#define MAX_ADAPTER_NAME 15
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| 286 |
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| 287 |
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static char ips_adapter_name[][30] = {
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| 288 |
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"ServeRAID",
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| 289 |
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"ServeRAID II",
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| 290 |
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"ServeRAID on motherboard",
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| 291 |
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"ServeRAID on motherboard",
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| 292 |
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"ServeRAID 3H",
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| 293 |
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"ServeRAID 3L",
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| 294 |
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"ServeRAID 4H",
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"ServeRAID 4M",
|
| 296 |
|
|
"ServeRAID 4L",
|
| 297 |
|
|
"ServeRAID 4Mx",
|
| 298 |
|
|
"ServeRAID 4Lx",
|
| 299 |
|
|
"ServeRAID 5i",
|
| 300 |
|
|
"ServeRAID 5i",
|
| 301 |
|
|
"ServeRAID 6M",
|
| 302 |
|
|
"ServeRAID 6i"
|
| 303 |
|
|
};
|
| 304 |
|
|
|
| 305 |
|
|
static struct notifier_block ips_notifier = {
|
| 306 |
|
|
ips_halt, NULL, 0
|
| 307 |
|
|
};
|
| 308 |
|
|
|
| 309 |
|
|
/*
|
| 310 |
|
|
* Direction table
|
| 311 |
|
|
*/
|
| 312 |
|
|
static char ips_command_direction[] = {
|
| 313 |
|
|
IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
|
| 314 |
|
|
IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
|
| 315 |
|
|
IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 316 |
|
|
IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
|
| 317 |
|
|
IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
|
| 318 |
|
|
IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
|
| 319 |
|
|
IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
|
| 320 |
|
|
IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 321 |
|
|
IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
|
| 322 |
|
|
IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
|
| 323 |
|
|
IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
|
| 324 |
|
|
IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
|
| 325 |
|
|
IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
|
| 326 |
|
|
IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
|
| 327 |
|
|
IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
|
| 328 |
|
|
IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 329 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 330 |
|
|
IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 331 |
|
|
IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 332 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 333 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 334 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 335 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 336 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 337 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 338 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 339 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 340 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 341 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 342 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 343 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 344 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 345 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 346 |
|
|
IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
|
| 347 |
|
|
IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
|
| 348 |
|
|
IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
|
| 349 |
|
|
IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
|
| 350 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 351 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 352 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 353 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 354 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 355 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 356 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 357 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 358 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 359 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
|
| 360 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 361 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 362 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
|
| 363 |
|
|
IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
|
| 364 |
|
|
};
|
| 365 |
|
|
|
| 366 |
|
|
/*
|
| 367 |
|
|
* Function prototypes
|
| 368 |
|
|
*/
|
| 369 |
|
|
int ips_detect(Scsi_Host_Template *);
|
| 370 |
|
|
int ips_release(struct Scsi_Host *);
|
| 371 |
|
|
int ips_eh_abort(Scsi_Cmnd *);
|
| 372 |
|
|
int ips_eh_reset(Scsi_Cmnd *);
|
| 373 |
|
|
int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
|
| 374 |
|
|
int ips_biosparam(Disk *, kdev_t, int *);
|
| 375 |
|
|
const char *ips_info(struct Scsi_Host *);
|
| 376 |
|
|
void do_ipsintr(int, void *, struct pt_regs *);
|
| 377 |
|
|
static int ips_hainit(ips_ha_t *);
|
| 378 |
|
|
static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
|
| 379 |
|
|
static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
|
| 380 |
|
|
static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
|
| 381 |
|
|
static int ips_online(ips_ha_t *, ips_scb_t *);
|
| 382 |
|
|
static int ips_inquiry(ips_ha_t *, ips_scb_t *);
|
| 383 |
|
|
static int ips_rdcap(ips_ha_t *, ips_scb_t *);
|
| 384 |
|
|
static int ips_msense(ips_ha_t *, ips_scb_t *);
|
| 385 |
|
|
static int ips_reqsen(ips_ha_t *, ips_scb_t *);
|
| 386 |
|
|
static int ips_deallocatescbs(ips_ha_t *, int);
|
| 387 |
|
|
static int ips_allocatescbs(ips_ha_t *);
|
| 388 |
|
|
static int ips_reset_copperhead(ips_ha_t *);
|
| 389 |
|
|
static int ips_reset_copperhead_memio(ips_ha_t *);
|
| 390 |
|
|
static int ips_reset_morpheus(ips_ha_t *);
|
| 391 |
|
|
static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
|
| 392 |
|
|
static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
|
| 393 |
|
|
static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
|
| 394 |
|
|
static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
|
| 395 |
|
|
static int ips_isintr_copperhead(ips_ha_t *);
|
| 396 |
|
|
static int ips_isintr_copperhead_memio(ips_ha_t *);
|
| 397 |
|
|
static int ips_isintr_morpheus(ips_ha_t *);
|
| 398 |
|
|
static int ips_wait(ips_ha_t *, int, int);
|
| 399 |
|
|
static int ips_write_driver_status(ips_ha_t *, int);
|
| 400 |
|
|
static int ips_read_adapter_status(ips_ha_t *, int);
|
| 401 |
|
|
static int ips_read_subsystem_parameters(ips_ha_t *, int);
|
| 402 |
|
|
static int ips_read_config(ips_ha_t *, int);
|
| 403 |
|
|
static int ips_clear_adapter(ips_ha_t *, int);
|
| 404 |
|
|
static int ips_readwrite_page5(ips_ha_t *, int, int);
|
| 405 |
|
|
static int ips_init_copperhead(ips_ha_t *);
|
| 406 |
|
|
static int ips_init_copperhead_memio(ips_ha_t *);
|
| 407 |
|
|
static int ips_init_morpheus(ips_ha_t *);
|
| 408 |
|
|
static int ips_isinit_copperhead(ips_ha_t *);
|
| 409 |
|
|
static int ips_isinit_copperhead_memio(ips_ha_t *);
|
| 410 |
|
|
static int ips_isinit_morpheus(ips_ha_t *);
|
| 411 |
|
|
static int ips_erase_bios(ips_ha_t *);
|
| 412 |
|
|
static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
|
| 413 |
|
|
static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
|
| 414 |
|
|
static int ips_erase_bios_memio(ips_ha_t *);
|
| 415 |
|
|
static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
|
| 416 |
|
|
static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
|
| 417 |
|
|
static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
|
| 418 |
|
|
static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
|
| 419 |
|
|
static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
|
| 420 |
|
|
static void ips_free_flash_copperhead(ips_ha_t * ha);
|
| 421 |
|
|
static void ips_get_bios_version(ips_ha_t *, int);
|
| 422 |
|
|
static void ips_identify_controller(ips_ha_t *);
|
| 423 |
|
|
static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
|
| 424 |
|
|
static void ips_enable_int_copperhead(ips_ha_t *);
|
| 425 |
|
|
static void ips_enable_int_copperhead_memio(ips_ha_t *);
|
| 426 |
|
|
static void ips_enable_int_morpheus(ips_ha_t *);
|
| 427 |
|
|
static void ips_intr_copperhead(ips_ha_t *);
|
| 428 |
|
|
static void ips_intr_morpheus(ips_ha_t *);
|
| 429 |
|
|
static void ips_next(ips_ha_t *, int);
|
| 430 |
|
|
static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
|
| 431 |
|
|
static void ipsintr_done(ips_ha_t *, struct ips_scb *);
|
| 432 |
|
|
static void ips_done(ips_ha_t *, ips_scb_t *);
|
| 433 |
|
|
static void ips_free(ips_ha_t *);
|
| 434 |
|
|
static void ips_init_scb(ips_ha_t *, ips_scb_t *);
|
| 435 |
|
|
static void ips_freescb(ips_ha_t *, ips_scb_t *);
|
| 436 |
|
|
static void ips_setup_funclist(ips_ha_t *);
|
| 437 |
|
|
static void ips_statinit(ips_ha_t *);
|
| 438 |
|
|
static void ips_statinit_memio(ips_ha_t *);
|
| 439 |
|
|
static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
|
| 440 |
|
|
static void ips_ffdc_reset(ips_ha_t *, int);
|
| 441 |
|
|
static void ips_ffdc_time(ips_ha_t *);
|
| 442 |
|
|
static uint32_t ips_statupd_copperhead(ips_ha_t *);
|
| 443 |
|
|
static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
|
| 444 |
|
|
static uint32_t ips_statupd_morpheus(ips_ha_t *);
|
| 445 |
|
|
static ips_scb_t *ips_getscb(ips_ha_t *);
|
| 446 |
|
|
static inline void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
|
| 447 |
|
|
static inline void ips_putq_scb_tail(ips_scb_queue_t *, ips_scb_t *);
|
| 448 |
|
|
static inline void ips_putq_wait_head(ips_wait_queue_t *, Scsi_Cmnd *);
|
| 449 |
|
|
static inline void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
|
| 450 |
|
|
static inline void ips_putq_copp_head(ips_copp_queue_t *,
|
| 451 |
|
|
ips_copp_wait_item_t *);
|
| 452 |
|
|
static inline void ips_putq_copp_tail(ips_copp_queue_t *,
|
| 453 |
|
|
ips_copp_wait_item_t *);
|
| 454 |
|
|
static inline ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
|
| 455 |
|
|
static inline ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
|
| 456 |
|
|
static inline Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
|
| 457 |
|
|
static inline Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
|
| 458 |
|
|
static inline ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
|
| 459 |
|
|
ips_copp_wait_item_t *);
|
| 460 |
|
|
static inline ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
|
| 461 |
|
|
|
| 462 |
|
|
static int ips_is_passthru(Scsi_Cmnd *);
|
| 463 |
|
|
static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
|
| 464 |
|
|
static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
|
| 465 |
|
|
static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
|
| 466 |
|
|
static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
|
| 467 |
|
|
unsigned int count);
|
| 468 |
|
|
static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
|
| 469 |
|
|
|
| 470 |
|
|
int ips_proc_info(char *, char **, off_t, int, int, int);
|
| 471 |
|
|
static int ips_host_info(ips_ha_t *, char *, off_t, int);
|
| 472 |
|
|
static void copy_mem_info(IPS_INFOSTR *, char *, int);
|
| 473 |
|
|
static int copy_info(IPS_INFOSTR *, char *, ...);
|
| 474 |
|
|
static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
|
| 475 |
|
|
static void ips_version_check(ips_ha_t * ha, int intr);
|
| 476 |
|
|
static int ips_abort_init(ips_ha_t * ha, int index);
|
| 477 |
|
|
static int ips_init_phase2(int index);
|
| 478 |
|
|
|
| 479 |
|
|
static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
|
| 480 |
|
|
static int ips_register_scsi(int index);
|
| 481 |
|
|
/*--------------------------------------------------------------------------*/
|
| 482 |
|
|
/* Exported Functions */
|
| 483 |
|
|
/*--------------------------------------------------------------------------*/
|
| 484 |
|
|
|
| 485 |
|
|
/****************************************************************************/
|
| 486 |
|
|
/* */
|
| 487 |
|
|
/* Routine Name: ips_setup */
|
| 488 |
|
|
/* */
|
| 489 |
|
|
/* Routine Description: */
|
| 490 |
|
|
/* */
|
| 491 |
|
|
/* setup parameters to the driver */
|
| 492 |
|
|
/* */
|
| 493 |
|
|
/****************************************************************************/
|
| 494 |
|
|
static int
|
| 495 |
|
|
ips_setup(char *ips_str)
|
| 496 |
|
|
{
|
| 497 |
|
|
|
| 498 |
|
|
int i;
|
| 499 |
|
|
char *key;
|
| 500 |
|
|
char *value;
|
| 501 |
|
|
IPS_OPTION options[] = {
|
| 502 |
|
|
{"noi2o", &ips_force_i2o, 0},
|
| 503 |
|
|
{"nommap", &ips_force_memio, 0},
|
| 504 |
|
|
{"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
|
| 505 |
|
|
{"cdboot", &ips_cd_boot, 0},
|
| 506 |
|
|
{"maxcmds", &MaxLiteCmds, 32},
|
| 507 |
|
|
};
|
| 508 |
|
|
|
| 509 |
|
|
/* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
|
| 510 |
|
|
/* Search for value */
|
| 511 |
|
|
while ((key = strsep(&ips_str, ",."))) {
|
| 512 |
|
|
if (!*key)
|
| 513 |
|
|
continue;
|
| 514 |
|
|
value = strchr(key, ':');
|
| 515 |
|
|
if (value)
|
| 516 |
|
|
*value++ = '\0';
|
| 517 |
|
|
/*
|
| 518 |
|
|
* We now have key/value pairs.
|
| 519 |
|
|
* Update the variables
|
| 520 |
|
|
*/
|
| 521 |
|
|
for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
|
| 522 |
|
|
if (strnicmp
|
| 523 |
|
|
(key, options[i].option_name,
|
| 524 |
|
|
strlen(options[i].option_name)) == 0) {
|
| 525 |
|
|
if (value)
|
| 526 |
|
|
*options[i].option_flag =
|
| 527 |
|
|
simple_strtoul(value, NULL, 0);
|
| 528 |
|
|
else
|
| 529 |
|
|
*options[i].option_flag =
|
| 530 |
|
|
options[i].option_value;
|
| 531 |
|
|
break;
|
| 532 |
|
|
}
|
| 533 |
|
|
}
|
| 534 |
|
|
}
|
| 535 |
|
|
|
| 536 |
|
|
return (1);
|
| 537 |
|
|
}
|
| 538 |
|
|
|
| 539 |
|
|
__setup("ips=", ips_setup);
|
| 540 |
|
|
|
| 541 |
|
|
/****************************************************************************/
|
| 542 |
|
|
/* */
|
| 543 |
|
|
/* Routine Name: ips_detect */
|
| 544 |
|
|
/* */
|
| 545 |
|
|
/* Routine Description: */
|
| 546 |
|
|
/* */
|
| 547 |
|
|
/* Detect and initialize the driver */
|
| 548 |
|
|
/* */
|
| 549 |
|
|
/* NOTE: this routine is called under the io_request_lock spinlock */
|
| 550 |
|
|
/* */
|
| 551 |
|
|
/****************************************************************************/
|
| 552 |
|
|
int
|
| 553 |
|
|
ips_detect(Scsi_Host_Template * SHT)
|
| 554 |
|
|
{
|
| 555 |
|
|
int i;
|
| 556 |
|
|
|
| 557 |
|
|
METHOD_TRACE("ips_detect", 1);
|
| 558 |
|
|
|
| 559 |
|
|
#ifdef MODULE
|
| 560 |
|
|
if (ips)
|
| 561 |
|
|
ips_setup(ips);
|
| 562 |
|
|
#endif
|
| 563 |
|
|
|
| 564 |
|
|
SHT->proc_info = ips_proc_info;
|
| 565 |
|
|
SHT->proc_name = "ips";
|
| 566 |
|
|
|
| 567 |
|
|
for (i = 0; i < ips_num_controllers; i++) {
|
| 568 |
|
|
if (ips_register_scsi(i))
|
| 569 |
|
|
ips_free(ips_ha[i]);
|
| 570 |
|
|
ips_released_controllers++;
|
| 571 |
|
|
}
|
| 572 |
|
|
|
| 573 |
|
|
return (ips_num_controllers);
|
| 574 |
|
|
}
|
| 575 |
|
|
|
| 576 |
|
|
/****************************************************************************/
|
| 577 |
|
|
/* configure the function pointers to use the functions that will work */
|
| 578 |
|
|
/* with the found version of the adapter */
|
| 579 |
|
|
/****************************************************************************/
|
| 580 |
|
|
static void
|
| 581 |
|
|
ips_setup_funclist(ips_ha_t * ha)
|
| 582 |
|
|
{
|
| 583 |
|
|
|
| 584 |
|
|
/*
|
| 585 |
|
|
* Setup Functions
|
| 586 |
|
|
*/
|
| 587 |
|
|
if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
|
| 588 |
|
|
/* morpheus / marco / sebring */
|
| 589 |
|
|
ha->func.isintr = ips_isintr_morpheus;
|
| 590 |
|
|
ha->func.isinit = ips_isinit_morpheus;
|
| 591 |
|
|
ha->func.issue = ips_issue_i2o_memio;
|
| 592 |
|
|
ha->func.init = ips_init_morpheus;
|
| 593 |
|
|
ha->func.statupd = ips_statupd_morpheus;
|
| 594 |
|
|
ha->func.reset = ips_reset_morpheus;
|
| 595 |
|
|
ha->func.intr = ips_intr_morpheus;
|
| 596 |
|
|
ha->func.enableint = ips_enable_int_morpheus;
|
| 597 |
|
|
} else if (IPS_USE_MEMIO(ha)) {
|
| 598 |
|
|
/* copperhead w/MEMIO */
|
| 599 |
|
|
ha->func.isintr = ips_isintr_copperhead_memio;
|
| 600 |
|
|
ha->func.isinit = ips_isinit_copperhead_memio;
|
| 601 |
|
|
ha->func.init = ips_init_copperhead_memio;
|
| 602 |
|
|
ha->func.statupd = ips_statupd_copperhead_memio;
|
| 603 |
|
|
ha->func.statinit = ips_statinit_memio;
|
| 604 |
|
|
ha->func.reset = ips_reset_copperhead_memio;
|
| 605 |
|
|
ha->func.intr = ips_intr_copperhead;
|
| 606 |
|
|
ha->func.erasebios = ips_erase_bios_memio;
|
| 607 |
|
|
ha->func.programbios = ips_program_bios_memio;
|
| 608 |
|
|
ha->func.verifybios = ips_verify_bios_memio;
|
| 609 |
|
|
ha->func.enableint = ips_enable_int_copperhead_memio;
|
| 610 |
|
|
if (IPS_USE_I2O_DELIVER(ha))
|
| 611 |
|
|
ha->func.issue = ips_issue_i2o_memio;
|
| 612 |
|
|
else
|
| 613 |
|
|
ha->func.issue = ips_issue_copperhead_memio;
|
| 614 |
|
|
} else {
|
| 615 |
|
|
/* copperhead */
|
| 616 |
|
|
ha->func.isintr = ips_isintr_copperhead;
|
| 617 |
|
|
ha->func.isinit = ips_isinit_copperhead;
|
| 618 |
|
|
ha->func.init = ips_init_copperhead;
|
| 619 |
|
|
ha->func.statupd = ips_statupd_copperhead;
|
| 620 |
|
|
ha->func.statinit = ips_statinit;
|
| 621 |
|
|
ha->func.reset = ips_reset_copperhead;
|
| 622 |
|
|
ha->func.intr = ips_intr_copperhead;
|
| 623 |
|
|
ha->func.erasebios = ips_erase_bios;
|
| 624 |
|
|
ha->func.programbios = ips_program_bios;
|
| 625 |
|
|
ha->func.verifybios = ips_verify_bios;
|
| 626 |
|
|
ha->func.enableint = ips_enable_int_copperhead;
|
| 627 |
|
|
|
| 628 |
|
|
if (IPS_USE_I2O_DELIVER(ha))
|
| 629 |
|
|
ha->func.issue = ips_issue_i2o;
|
| 630 |
|
|
else
|
| 631 |
|
|
ha->func.issue = ips_issue_copperhead;
|
| 632 |
|
|
}
|
| 633 |
|
|
}
|
| 634 |
|
|
|
| 635 |
|
|
/****************************************************************************/
|
| 636 |
|
|
/* */
|
| 637 |
|
|
/* Routine Name: ips_release */
|
| 638 |
|
|
/* */
|
| 639 |
|
|
/* Routine Description: */
|
| 640 |
|
|
/* */
|
| 641 |
|
|
/* Remove a driver */
|
| 642 |
|
|
/* */
|
| 643 |
|
|
/****************************************************************************/
|
| 644 |
|
|
int
|
| 645 |
|
|
ips_release(struct Scsi_Host *sh)
|
| 646 |
|
|
{
|
| 647 |
|
|
ips_scb_t *scb;
|
| 648 |
|
|
ips_ha_t *ha;
|
| 649 |
|
|
int i;
|
| 650 |
|
|
|
| 651 |
|
|
METHOD_TRACE("ips_release", 1);
|
| 652 |
|
|
|
| 653 |
|
|
for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
|
| 654 |
|
|
|
| 655 |
|
|
if (i == IPS_MAX_ADAPTERS) {
|
| 656 |
|
|
printk(KERN_WARNING
|
| 657 |
|
|
"(%s) release, invalid Scsi_Host pointer.\n", ips_name);
|
| 658 |
|
|
BUG();
|
| 659 |
|
|
return (FALSE);
|
| 660 |
|
|
}
|
| 661 |
|
|
|
| 662 |
|
|
ha = IPS_HA(sh);
|
| 663 |
|
|
|
| 664 |
|
|
if (!ha)
|
| 665 |
|
|
return (FALSE);
|
| 666 |
|
|
|
| 667 |
|
|
/* flush the cache on the controller */
|
| 668 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 669 |
|
|
|
| 670 |
|
|
ips_init_scb(ha, scb);
|
| 671 |
|
|
|
| 672 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 673 |
|
|
scb->cdb[0] = IPS_CMD_FLUSH;
|
| 674 |
|
|
|
| 675 |
|
|
scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
|
| 676 |
|
|
scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
|
| 677 |
|
|
scb->cmd.flush_cache.state = IPS_NORM_STATE;
|
| 678 |
|
|
scb->cmd.flush_cache.reserved = 0;
|
| 679 |
|
|
scb->cmd.flush_cache.reserved2 = 0;
|
| 680 |
|
|
scb->cmd.flush_cache.reserved3 = 0;
|
| 681 |
|
|
scb->cmd.flush_cache.reserved4 = 0;
|
| 682 |
|
|
|
| 683 |
|
|
printk(KERN_NOTICE "(%s%d) Flushing Cache.\n", ips_name, ha->host_num);
|
| 684 |
|
|
|
| 685 |
|
|
/* send command */
|
| 686 |
|
|
if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
|
| 687 |
|
|
printk(KERN_NOTICE "(%s%d) Incomplete Flush.\n", ips_name,
|
| 688 |
|
|
ha->host_num);
|
| 689 |
|
|
|
| 690 |
|
|
printk(KERN_NOTICE "(%s%d) Flushing Complete.\n", ips_name,
|
| 691 |
|
|
ha->host_num);
|
| 692 |
|
|
|
| 693 |
|
|
ips_sh[i] = NULL;
|
| 694 |
|
|
ips_ha[i] = NULL;
|
| 695 |
|
|
|
| 696 |
|
|
/* free extra memory */
|
| 697 |
|
|
ips_free(ha);
|
| 698 |
|
|
|
| 699 |
|
|
/* Free I/O Region */
|
| 700 |
|
|
if (ha->io_addr)
|
| 701 |
|
|
release_region(ha->io_addr, ha->io_len);
|
| 702 |
|
|
|
| 703 |
|
|
/* free IRQ */
|
| 704 |
|
|
free_irq(ha->irq, ha);
|
| 705 |
|
|
|
| 706 |
|
|
scsi_unregister(sh);
|
| 707 |
|
|
|
| 708 |
|
|
ips_released_controllers++;
|
| 709 |
|
|
|
| 710 |
|
|
return (FALSE);
|
| 711 |
|
|
}
|
| 712 |
|
|
|
| 713 |
|
|
/****************************************************************************/
|
| 714 |
|
|
/* */
|
| 715 |
|
|
/* Routine Name: ips_halt */
|
| 716 |
|
|
/* */
|
| 717 |
|
|
/* Routine Description: */
|
| 718 |
|
|
/* */
|
| 719 |
|
|
/* Perform cleanup when the system reboots */
|
| 720 |
|
|
/* */
|
| 721 |
|
|
/****************************************************************************/
|
| 722 |
|
|
static int
|
| 723 |
|
|
ips_halt(struct notifier_block *nb, ulong event, void *buf)
|
| 724 |
|
|
{
|
| 725 |
|
|
ips_scb_t *scb;
|
| 726 |
|
|
ips_ha_t *ha;
|
| 727 |
|
|
int i;
|
| 728 |
|
|
|
| 729 |
|
|
if ((event != SYS_RESTART) && (event != SYS_HALT) &&
|
| 730 |
|
|
(event != SYS_POWER_OFF)) return (NOTIFY_DONE);
|
| 731 |
|
|
|
| 732 |
|
|
for (i = 0; i < ips_next_controller; i++) {
|
| 733 |
|
|
ha = (ips_ha_t *) ips_ha[i];
|
| 734 |
|
|
|
| 735 |
|
|
if (!ha)
|
| 736 |
|
|
continue;
|
| 737 |
|
|
|
| 738 |
|
|
if (!ha->active)
|
| 739 |
|
|
continue;
|
| 740 |
|
|
|
| 741 |
|
|
/* flush the cache on the controller */
|
| 742 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 743 |
|
|
|
| 744 |
|
|
ips_init_scb(ha, scb);
|
| 745 |
|
|
|
| 746 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 747 |
|
|
scb->cdb[0] = IPS_CMD_FLUSH;
|
| 748 |
|
|
|
| 749 |
|
|
scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
|
| 750 |
|
|
scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
|
| 751 |
|
|
scb->cmd.flush_cache.state = IPS_NORM_STATE;
|
| 752 |
|
|
scb->cmd.flush_cache.reserved = 0;
|
| 753 |
|
|
scb->cmd.flush_cache.reserved2 = 0;
|
| 754 |
|
|
scb->cmd.flush_cache.reserved3 = 0;
|
| 755 |
|
|
scb->cmd.flush_cache.reserved4 = 0;
|
| 756 |
|
|
|
| 757 |
|
|
printk(KERN_NOTICE "(%s%d) Flushing Cache.\n", ips_name,
|
| 758 |
|
|
ha->host_num);
|
| 759 |
|
|
|
| 760 |
|
|
/* send command */
|
| 761 |
|
|
if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
|
| 762 |
|
|
IPS_FAILURE) printk(KERN_NOTICE
|
| 763 |
|
|
"(%s%d) Incomplete Flush.\n", ips_name,
|
| 764 |
|
|
ha->host_num);
|
| 765 |
|
|
else
|
| 766 |
|
|
printk(KERN_NOTICE "(%s%d) Flushing Complete.\n",
|
| 767 |
|
|
ips_name, ha->host_num);
|
| 768 |
|
|
}
|
| 769 |
|
|
|
| 770 |
|
|
return (NOTIFY_OK);
|
| 771 |
|
|
}
|
| 772 |
|
|
|
| 773 |
|
|
/****************************************************************************/
|
| 774 |
|
|
/* */
|
| 775 |
|
|
/* Routine Name: ips_eh_abort */
|
| 776 |
|
|
/* */
|
| 777 |
|
|
/* Routine Description: */
|
| 778 |
|
|
/* */
|
| 779 |
|
|
/* Abort a command (using the new error code stuff) */
|
| 780 |
|
|
/* Note: this routine is called under the io_request_lock */
|
| 781 |
|
|
/****************************************************************************/
|
| 782 |
|
|
int
|
| 783 |
|
|
ips_eh_abort(Scsi_Cmnd * SC)
|
| 784 |
|
|
{
|
| 785 |
|
|
ips_ha_t *ha;
|
| 786 |
|
|
ips_copp_wait_item_t *item;
|
| 787 |
|
|
int ret;
|
| 788 |
|
|
|
| 789 |
|
|
METHOD_TRACE("ips_eh_abort", 1);
|
| 790 |
|
|
|
| 791 |
|
|
if (!SC)
|
| 792 |
|
|
return (FAILED);
|
| 793 |
|
|
|
| 794 |
|
|
ha = (ips_ha_t *) SC->host->hostdata;
|
| 795 |
|
|
|
| 796 |
|
|
if (!ha)
|
| 797 |
|
|
return (FAILED);
|
| 798 |
|
|
|
| 799 |
|
|
if (!ha->active)
|
| 800 |
|
|
return (FAILED);
|
| 801 |
|
|
|
| 802 |
|
|
if (SC->serial_number != SC->serial_number_at_timeout) {
|
| 803 |
|
|
/* HMM, looks like a bogus command */
|
| 804 |
|
|
DEBUG(1, "Abort called with bogus scsi command");
|
| 805 |
|
|
|
| 806 |
|
|
return (FAILED);
|
| 807 |
|
|
}
|
| 808 |
|
|
|
| 809 |
|
|
/* See if the command is on the copp queue */
|
| 810 |
|
|
item = ha->copp_waitlist.head;
|
| 811 |
|
|
while ((item) && (item->scsi_cmd != SC))
|
| 812 |
|
|
item = item->next;
|
| 813 |
|
|
|
| 814 |
|
|
if (item) {
|
| 815 |
|
|
/* Found it */
|
| 816 |
|
|
ips_removeq_copp(&ha->copp_waitlist, item);
|
| 817 |
|
|
ret = (SUCCESS);
|
| 818 |
|
|
|
| 819 |
|
|
/* See if the command is on the wait queue */
|
| 820 |
|
|
} else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
|
| 821 |
|
|
/* command not sent yet */
|
| 822 |
|
|
ret = (SUCCESS);
|
| 823 |
|
|
} else {
|
| 824 |
|
|
/* command must have already been sent */
|
| 825 |
|
|
ret = (FAILED);
|
| 826 |
|
|
}
|
| 827 |
|
|
return ret;
|
| 828 |
|
|
}
|
| 829 |
|
|
|
| 830 |
|
|
/****************************************************************************/
|
| 831 |
|
|
/* */
|
| 832 |
|
|
/* Routine Name: ips_eh_reset */
|
| 833 |
|
|
/* */
|
| 834 |
|
|
/* Routine Description: */
|
| 835 |
|
|
/* */
|
| 836 |
|
|
/* Reset the controller (with new eh error code) */
|
| 837 |
|
|
/* */
|
| 838 |
|
|
/* NOTE: this routine is called under the io_request_lock spinlock */
|
| 839 |
|
|
/* */
|
| 840 |
|
|
/****************************************************************************/
|
| 841 |
|
|
int
|
| 842 |
|
|
ips_eh_reset(Scsi_Cmnd * SC)
|
| 843 |
|
|
{
|
| 844 |
|
|
int ret;
|
| 845 |
|
|
int i;
|
| 846 |
|
|
ips_ha_t *ha;
|
| 847 |
|
|
ips_scb_t *scb;
|
| 848 |
|
|
ips_copp_wait_item_t *item;
|
| 849 |
|
|
|
| 850 |
|
|
METHOD_TRACE("ips_eh_reset", 1);
|
| 851 |
|
|
|
| 852 |
|
|
#ifdef NO_IPS_RESET
|
| 853 |
|
|
return (FAILED);
|
| 854 |
|
|
#else
|
| 855 |
|
|
|
| 856 |
|
|
if (!SC) {
|
| 857 |
|
|
DEBUG(1, "Reset called with NULL scsi command");
|
| 858 |
|
|
|
| 859 |
|
|
return (FAILED);
|
| 860 |
|
|
}
|
| 861 |
|
|
|
| 862 |
|
|
ha = (ips_ha_t *) SC->host->hostdata;
|
| 863 |
|
|
|
| 864 |
|
|
if (!ha) {
|
| 865 |
|
|
DEBUG(1, "Reset called with NULL ha struct");
|
| 866 |
|
|
|
| 867 |
|
|
return (FAILED);
|
| 868 |
|
|
}
|
| 869 |
|
|
|
| 870 |
|
|
if (!ha->active)
|
| 871 |
|
|
return (FAILED);
|
| 872 |
|
|
|
| 873 |
|
|
/* See if the command is on the copp queue */
|
| 874 |
|
|
item = ha->copp_waitlist.head;
|
| 875 |
|
|
while ((item) && (item->scsi_cmd != SC))
|
| 876 |
|
|
item = item->next;
|
| 877 |
|
|
|
| 878 |
|
|
if (item) {
|
| 879 |
|
|
/* Found it */
|
| 880 |
|
|
ips_removeq_copp(&ha->copp_waitlist, item);
|
| 881 |
|
|
return (SUCCESS);
|
| 882 |
|
|
}
|
| 883 |
|
|
|
| 884 |
|
|
/* See if the command is on the wait queue */
|
| 885 |
|
|
if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
|
| 886 |
|
|
/* command not sent yet */
|
| 887 |
|
|
return (SUCCESS);
|
| 888 |
|
|
}
|
| 889 |
|
|
|
| 890 |
|
|
/* An explanation for the casual observer: */
|
| 891 |
|
|
/* Part of the function of a RAID controller is automatic error */
|
| 892 |
|
|
/* detection and recovery. As such, the only problem that physically */
|
| 893 |
|
|
/* resetting an adapter will ever fix is when, for some reason, */
|
| 894 |
|
|
/* the driver is not successfully communicating with the adapter. */
|
| 895 |
|
|
/* Therefore, we will attempt to flush this adapter. If that succeeds, */
|
| 896 |
|
|
/* then there's no real purpose in a physical reset. This will complete */
|
| 897 |
|
|
/* much faster and avoids any problems that might be caused by a */
|
| 898 |
|
|
/* physical reset ( such as having to fail all the outstanding I/O's ). */
|
| 899 |
|
|
|
| 900 |
|
|
if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
|
| 901 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 902 |
|
|
|
| 903 |
|
|
ips_init_scb(ha, scb);
|
| 904 |
|
|
|
| 905 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 906 |
|
|
scb->cdb[0] = IPS_CMD_FLUSH;
|
| 907 |
|
|
|
| 908 |
|
|
scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
|
| 909 |
|
|
scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
|
| 910 |
|
|
scb->cmd.flush_cache.state = IPS_NORM_STATE;
|
| 911 |
|
|
scb->cmd.flush_cache.reserved = 0;
|
| 912 |
|
|
scb->cmd.flush_cache.reserved2 = 0;
|
| 913 |
|
|
scb->cmd.flush_cache.reserved3 = 0;
|
| 914 |
|
|
scb->cmd.flush_cache.reserved4 = 0;
|
| 915 |
|
|
|
| 916 |
|
|
/* Attempt the flush command */
|
| 917 |
|
|
ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
|
| 918 |
|
|
if (ret == IPS_SUCCESS) {
|
| 919 |
|
|
printk(KERN_NOTICE
|
| 920 |
|
|
"(%s%d) Reset Request - Flushed Cache\n",
|
| 921 |
|
|
ips_name, ha->host_num);
|
| 922 |
|
|
return (SUCCESS);
|
| 923 |
|
|
}
|
| 924 |
|
|
}
|
| 925 |
|
|
|
| 926 |
|
|
/* Either we can't communicate with the adapter or it's an IOCTL request */
|
| 927 |
|
|
/* from a utility. A physical reset is needed at this point. */
|
| 928 |
|
|
|
| 929 |
|
|
ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
|
| 930 |
|
|
|
| 931 |
|
|
/*
|
| 932 |
|
|
* command must have already been sent
|
| 933 |
|
|
* reset the controller
|
| 934 |
|
|
*/
|
| 935 |
|
|
printk(KERN_NOTICE "(%s%d) Resetting controller.\n",
|
| 936 |
|
|
ips_name, ha->host_num);
|
| 937 |
|
|
ret = (*ha->func.reset) (ha);
|
| 938 |
|
|
|
| 939 |
|
|
if (!ret) {
|
| 940 |
|
|
Scsi_Cmnd *scsi_cmd;
|
| 941 |
|
|
|
| 942 |
|
|
printk(KERN_NOTICE
|
| 943 |
|
|
"(%s%d) Controller reset failed - controller now offline.\n",
|
| 944 |
|
|
ips_name, ha->host_num);
|
| 945 |
|
|
|
| 946 |
|
|
/* Now fail all of the active commands */
|
| 947 |
|
|
DEBUG_VAR(1, "(%s%d) Failing active commands",
|
| 948 |
|
|
ips_name, ha->host_num);
|
| 949 |
|
|
|
| 950 |
|
|
while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
|
| 951 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 952 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 953 |
|
|
ips_freescb(ha, scb);
|
| 954 |
|
|
}
|
| 955 |
|
|
|
| 956 |
|
|
/* Now fail all of the pending commands */
|
| 957 |
|
|
DEBUG_VAR(1, "(%s%d) Failing pending commands",
|
| 958 |
|
|
ips_name, ha->host_num);
|
| 959 |
|
|
|
| 960 |
|
|
while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
|
| 961 |
|
|
scsi_cmd->result = DID_ERROR;
|
| 962 |
|
|
scsi_cmd->scsi_done(scsi_cmd);
|
| 963 |
|
|
}
|
| 964 |
|
|
|
| 965 |
|
|
ha->active = FALSE;
|
| 966 |
|
|
return (FAILED);
|
| 967 |
|
|
}
|
| 968 |
|
|
|
| 969 |
|
|
if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
|
| 970 |
|
|
Scsi_Cmnd *scsi_cmd;
|
| 971 |
|
|
|
| 972 |
|
|
printk(KERN_NOTICE
|
| 973 |
|
|
"(%s%d) Controller reset failed - controller now offline.\n",
|
| 974 |
|
|
ips_name, ha->host_num);
|
| 975 |
|
|
|
| 976 |
|
|
/* Now fail all of the active commands */
|
| 977 |
|
|
DEBUG_VAR(1, "(%s%d) Failing active commands",
|
| 978 |
|
|
ips_name, ha->host_num);
|
| 979 |
|
|
|
| 980 |
|
|
while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
|
| 981 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 982 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 983 |
|
|
ips_freescb(ha, scb);
|
| 984 |
|
|
}
|
| 985 |
|
|
|
| 986 |
|
|
/* Now fail all of the pending commands */
|
| 987 |
|
|
DEBUG_VAR(1, "(%s%d) Failing pending commands",
|
| 988 |
|
|
ips_name, ha->host_num);
|
| 989 |
|
|
|
| 990 |
|
|
while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
|
| 991 |
|
|
scsi_cmd->result = DID_ERROR << 16;
|
| 992 |
|
|
scsi_cmd->scsi_done(scsi_cmd);
|
| 993 |
|
|
}
|
| 994 |
|
|
|
| 995 |
|
|
ha->active = FALSE;
|
| 996 |
|
|
return (FAILED);
|
| 997 |
|
|
}
|
| 998 |
|
|
|
| 999 |
|
|
/* FFDC */
|
| 1000 |
|
|
if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
|
| 1001 |
|
|
struct timeval tv;
|
| 1002 |
|
|
|
| 1003 |
|
|
do_gettimeofday(&tv);
|
| 1004 |
|
|
ha->last_ffdc = tv.tv_sec;
|
| 1005 |
|
|
ha->reset_count++;
|
| 1006 |
|
|
ips_ffdc_reset(ha, IPS_INTR_IORL);
|
| 1007 |
|
|
}
|
| 1008 |
|
|
|
| 1009 |
|
|
/* Now fail all of the active commands */
|
| 1010 |
|
|
DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
|
| 1011 |
|
|
|
| 1012 |
|
|
while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
|
| 1013 |
|
|
scb->scsi_cmd->result =
|
| 1014 |
|
|
(DID_RESET << 16) | (SUGGEST_RETRY << 24);
|
| 1015 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 1016 |
|
|
ips_freescb(ha, scb);
|
| 1017 |
|
|
}
|
| 1018 |
|
|
|
| 1019 |
|
|
/* Reset DCDB active command bits */
|
| 1020 |
|
|
for (i = 1; i < ha->nbus; i++)
|
| 1021 |
|
|
ha->dcdb_active[i - 1] = 0;
|
| 1022 |
|
|
|
| 1023 |
|
|
/* Reset the number of active IOCTLs */
|
| 1024 |
|
|
ha->num_ioctl = 0;
|
| 1025 |
|
|
|
| 1026 |
|
|
ips_next(ha, IPS_INTR_IORL);
|
| 1027 |
|
|
|
| 1028 |
|
|
return (SUCCESS);
|
| 1029 |
|
|
#endif /* NO_IPS_RESET */
|
| 1030 |
|
|
|
| 1031 |
|
|
}
|
| 1032 |
|
|
|
| 1033 |
|
|
/****************************************************************************/
|
| 1034 |
|
|
/* */
|
| 1035 |
|
|
/* Routine Name: ips_queue */
|
| 1036 |
|
|
/* */
|
| 1037 |
|
|
/* Routine Description: */
|
| 1038 |
|
|
/* */
|
| 1039 |
|
|
/* Send a command to the controller */
|
| 1040 |
|
|
/* */
|
| 1041 |
|
|
/* NOTE: */
|
| 1042 |
|
|
/* Linux obtains io_request_lock before calling this function */
|
| 1043 |
|
|
/* */
|
| 1044 |
|
|
/****************************************************************************/
|
| 1045 |
|
|
int
|
| 1046 |
|
|
ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
|
| 1047 |
|
|
{
|
| 1048 |
|
|
ips_ha_t *ha;
|
| 1049 |
|
|
ips_passthru_t *pt;
|
| 1050 |
|
|
|
| 1051 |
|
|
METHOD_TRACE("ips_queue", 1);
|
| 1052 |
|
|
|
| 1053 |
|
|
ha = (ips_ha_t *) SC->host->hostdata;
|
| 1054 |
|
|
|
| 1055 |
|
|
if (!ha)
|
| 1056 |
|
|
return (1);
|
| 1057 |
|
|
|
| 1058 |
|
|
if (!ha->active)
|
| 1059 |
|
|
return (DID_ERROR);
|
| 1060 |
|
|
|
| 1061 |
|
|
if (ips_is_passthru(SC)) {
|
| 1062 |
|
|
if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
|
| 1063 |
|
|
SC->result = DID_BUS_BUSY << 16;
|
| 1064 |
|
|
done(SC);
|
| 1065 |
|
|
|
| 1066 |
|
|
return (0);
|
| 1067 |
|
|
}
|
| 1068 |
|
|
} else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
|
| 1069 |
|
|
SC->result = DID_BUS_BUSY << 16;
|
| 1070 |
|
|
done(SC);
|
| 1071 |
|
|
|
| 1072 |
|
|
return (0);
|
| 1073 |
|
|
}
|
| 1074 |
|
|
|
| 1075 |
|
|
SC->scsi_done = done;
|
| 1076 |
|
|
|
| 1077 |
|
|
DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
|
| 1078 |
|
|
ips_name,
|
| 1079 |
|
|
ha->host_num, SC->cmnd[0], SC->channel, SC->target, SC->lun);
|
| 1080 |
|
|
|
| 1081 |
|
|
/* Check for command to initiator IDs */
|
| 1082 |
|
|
if ((SC->channel > 0) && (SC->target == ha->ha_id[SC->channel])) {
|
| 1083 |
|
|
SC->result = DID_NO_CONNECT << 16;
|
| 1084 |
|
|
done(SC);
|
| 1085 |
|
|
|
| 1086 |
|
|
return (0);
|
| 1087 |
|
|
}
|
| 1088 |
|
|
|
| 1089 |
|
|
if (ips_is_passthru(SC)) {
|
| 1090 |
|
|
|
| 1091 |
|
|
ips_copp_wait_item_t *scratch;
|
| 1092 |
|
|
|
| 1093 |
|
|
/* A Reset IOCTL is only sent by the boot CD in extreme cases. */
|
| 1094 |
|
|
/* There can never be any system activity ( network or disk ), but check */
|
| 1095 |
|
|
/* anyway just as a good practice. */
|
| 1096 |
|
|
pt = (ips_passthru_t *) SC->request_buffer;
|
| 1097 |
|
|
if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
|
| 1098 |
|
|
(pt->CoppCP.cmd.reset.adapter_flag == 1)) {
|
| 1099 |
|
|
if (ha->scb_activelist.count != 0) {
|
| 1100 |
|
|
SC->result = DID_BUS_BUSY << 16;
|
| 1101 |
|
|
done(SC);
|
| 1102 |
|
|
return (0);
|
| 1103 |
|
|
}
|
| 1104 |
|
|
ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
|
| 1105 |
|
|
ips_eh_reset(SC);
|
| 1106 |
|
|
SC->result = DID_OK << 16;
|
| 1107 |
|
|
SC->scsi_done(SC);
|
| 1108 |
|
|
return (0);
|
| 1109 |
|
|
}
|
| 1110 |
|
|
|
| 1111 |
|
|
/* allocate space for the scribble */
|
| 1112 |
|
|
scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
|
| 1113 |
|
|
|
| 1114 |
|
|
if (!scratch) {
|
| 1115 |
|
|
SC->result = DID_ERROR << 16;
|
| 1116 |
|
|
done(SC);
|
| 1117 |
|
|
|
| 1118 |
|
|
return (0);
|
| 1119 |
|
|
}
|
| 1120 |
|
|
|
| 1121 |
|
|
scratch->scsi_cmd = SC;
|
| 1122 |
|
|
scratch->next = NULL;
|
| 1123 |
|
|
|
| 1124 |
|
|
ips_putq_copp_tail(&ha->copp_waitlist, scratch);
|
| 1125 |
|
|
} else {
|
| 1126 |
|
|
ips_putq_wait_tail(&ha->scb_waitlist, SC);
|
| 1127 |
|
|
}
|
| 1128 |
|
|
|
| 1129 |
|
|
ips_next(ha, IPS_INTR_IORL);
|
| 1130 |
|
|
|
| 1131 |
|
|
return (0);
|
| 1132 |
|
|
}
|
| 1133 |
|
|
|
| 1134 |
|
|
/****************************************************************************/
|
| 1135 |
|
|
/* */
|
| 1136 |
|
|
/* Routine Name: ips_biosparam */
|
| 1137 |
|
|
/* */
|
| 1138 |
|
|
/* Routine Description: */
|
| 1139 |
|
|
/* */
|
| 1140 |
|
|
/* Set bios geometry for the controller */
|
| 1141 |
|
|
/* */
|
| 1142 |
|
|
/****************************************************************************/
|
| 1143 |
|
|
int
|
| 1144 |
|
|
ips_biosparam(Disk * disk, kdev_t dev, int geom[])
|
| 1145 |
|
|
{
|
| 1146 |
|
|
ips_ha_t *ha;
|
| 1147 |
|
|
int heads;
|
| 1148 |
|
|
int sectors;
|
| 1149 |
|
|
int cylinders;
|
| 1150 |
|
|
|
| 1151 |
|
|
METHOD_TRACE("ips_biosparam", 1);
|
| 1152 |
|
|
|
| 1153 |
|
|
ha = (ips_ha_t *) disk->device->host->hostdata;
|
| 1154 |
|
|
|
| 1155 |
|
|
if (!ha)
|
| 1156 |
|
|
/* ?!?! host adater info invalid */
|
| 1157 |
|
|
return (0);
|
| 1158 |
|
|
|
| 1159 |
|
|
if (!ha->active)
|
| 1160 |
|
|
return (0);
|
| 1161 |
|
|
|
| 1162 |
|
|
if (!ips_read_adapter_status(ha, IPS_INTR_ON))
|
| 1163 |
|
|
/* ?!?! Enquiry command failed */
|
| 1164 |
|
|
return (0);
|
| 1165 |
|
|
|
| 1166 |
|
|
if ((disk->capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
|
| 1167 |
|
|
heads = IPS_NORM_HEADS;
|
| 1168 |
|
|
sectors = IPS_NORM_SECTORS;
|
| 1169 |
|
|
} else {
|
| 1170 |
|
|
heads = IPS_COMP_HEADS;
|
| 1171 |
|
|
sectors = IPS_COMP_SECTORS;
|
| 1172 |
|
|
}
|
| 1173 |
|
|
|
| 1174 |
|
|
cylinders = disk->capacity / (heads * sectors);
|
| 1175 |
|
|
|
| 1176 |
|
|
DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
|
| 1177 |
|
|
heads, sectors, cylinders);
|
| 1178 |
|
|
|
| 1179 |
|
|
geom[0] = heads;
|
| 1180 |
|
|
geom[1] = sectors;
|
| 1181 |
|
|
geom[2] = cylinders;
|
| 1182 |
|
|
|
| 1183 |
|
|
return (0);
|
| 1184 |
|
|
}
|
| 1185 |
|
|
|
| 1186 |
|
|
#if LINUX_VERSION_CODE < LinuxVersionCode(2,5,0)
|
| 1187 |
|
|
/****************************************************************************/
|
| 1188 |
|
|
/* */
|
| 1189 |
|
|
/* Routine Name: ips_select_queue_depth */
|
| 1190 |
|
|
/* */
|
| 1191 |
|
|
/* Routine Description: */
|
| 1192 |
|
|
/* */
|
| 1193 |
|
|
/* Select queue depths for the devices on the contoller */
|
| 1194 |
|
|
/* */
|
| 1195 |
|
|
/****************************************************************************/
|
| 1196 |
|
|
static void
|
| 1197 |
|
|
ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
|
| 1198 |
|
|
{
|
| 1199 |
|
|
Scsi_Device *device;
|
| 1200 |
|
|
ips_ha_t *ha;
|
| 1201 |
|
|
int count = 0;
|
| 1202 |
|
|
int min;
|
| 1203 |
|
|
|
| 1204 |
|
|
ha = IPS_HA(host);
|
| 1205 |
|
|
min = ha->max_cmds / 4;
|
| 1206 |
|
|
|
| 1207 |
|
|
for (device = scsi_devs; device; device = device->next) {
|
| 1208 |
|
|
if (device->host == host) {
|
| 1209 |
|
|
if ((device->channel == 0) && (device->type == 0))
|
| 1210 |
|
|
count++;
|
| 1211 |
|
|
}
|
| 1212 |
|
|
}
|
| 1213 |
|
|
|
| 1214 |
|
|
for (device = scsi_devs; device; device = device->next) {
|
| 1215 |
|
|
if (device->host == host) {
|
| 1216 |
|
|
if ((device->channel == 0) && (device->type == 0)) {
|
| 1217 |
|
|
device->queue_depth =
|
| 1218 |
|
|
(ha->max_cmds - 1) / count;
|
| 1219 |
|
|
if (device->queue_depth < min)
|
| 1220 |
|
|
device->queue_depth = min;
|
| 1221 |
|
|
} else {
|
| 1222 |
|
|
device->queue_depth = 2;
|
| 1223 |
|
|
}
|
| 1224 |
|
|
|
| 1225 |
|
|
if (device->queue_depth < 2)
|
| 1226 |
|
|
device->queue_depth = 2;
|
| 1227 |
|
|
}
|
| 1228 |
|
|
}
|
| 1229 |
|
|
}
|
| 1230 |
|
|
|
| 1231 |
|
|
#else
|
| 1232 |
|
|
/****************************************************************************/
|
| 1233 |
|
|
/* */
|
| 1234 |
|
|
/* Routine Name: ips_slave_configure */
|
| 1235 |
|
|
/* */
|
| 1236 |
|
|
/* Routine Description: */
|
| 1237 |
|
|
/* */
|
| 1238 |
|
|
/* Set queue depths on devices once scan is complete */
|
| 1239 |
|
|
/* */
|
| 1240 |
|
|
/****************************************************************************/
|
| 1241 |
|
|
int
|
| 1242 |
|
|
ips_slave_configure(Scsi_Device * SDptr)
|
| 1243 |
|
|
{
|
| 1244 |
|
|
ips_ha_t *ha;
|
| 1245 |
|
|
int min;
|
| 1246 |
|
|
|
| 1247 |
|
|
ha = IPS_HA(SDptr->host);
|
| 1248 |
|
|
if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
|
| 1249 |
|
|
min = ha->max_cmds / 2;
|
| 1250 |
|
|
if (ha->enq->ucLogDriveCount <= 2)
|
| 1251 |
|
|
min = ha->max_cmds - 1;
|
| 1252 |
|
|
scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
|
| 1253 |
|
|
}
|
| 1254 |
|
|
return 0;
|
| 1255 |
|
|
}
|
| 1256 |
|
|
#endif
|
| 1257 |
|
|
|
| 1258 |
|
|
/****************************************************************************/
|
| 1259 |
|
|
/* */
|
| 1260 |
|
|
/* Routine Name: do_ipsintr */
|
| 1261 |
|
|
/* */
|
| 1262 |
|
|
/* Routine Description: */
|
| 1263 |
|
|
/* */
|
| 1264 |
|
|
/* Wrapper for the interrupt handler */
|
| 1265 |
|
|
/* */
|
| 1266 |
|
|
/****************************************************************************/
|
| 1267 |
|
|
void
|
| 1268 |
|
|
do_ipsintr(int irq, void *dev_id, struct pt_regs *regs)
|
| 1269 |
|
|
{
|
| 1270 |
|
|
ips_ha_t *ha;
|
| 1271 |
|
|
unsigned long cpu_flags;
|
| 1272 |
|
|
struct Scsi_Host *host;
|
| 1273 |
|
|
|
| 1274 |
|
|
METHOD_TRACE("do_ipsintr", 2);
|
| 1275 |
|
|
|
| 1276 |
|
|
ha = (ips_ha_t *) dev_id;
|
| 1277 |
|
|
if (!ha)
|
| 1278 |
|
|
return;
|
| 1279 |
|
|
host = ips_sh[ha->host_num];
|
| 1280 |
|
|
/* interrupt during initialization */
|
| 1281 |
|
|
if (!host) {
|
| 1282 |
|
|
(*ha->func.intr) (ha);
|
| 1283 |
|
|
return;
|
| 1284 |
|
|
}
|
| 1285 |
|
|
|
| 1286 |
|
|
IPS_LOCK_SAVE(host->host_lock, cpu_flags);
|
| 1287 |
|
|
|
| 1288 |
|
|
if (!ha->active) {
|
| 1289 |
|
|
IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
|
| 1290 |
|
|
return;
|
| 1291 |
|
|
}
|
| 1292 |
|
|
|
| 1293 |
|
|
(*ha->func.intr) (ha);
|
| 1294 |
|
|
|
| 1295 |
|
|
IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
|
| 1296 |
|
|
|
| 1297 |
|
|
/* start the next command */
|
| 1298 |
|
|
ips_next(ha, IPS_INTR_ON);
|
| 1299 |
|
|
}
|
| 1300 |
|
|
|
| 1301 |
|
|
/****************************************************************************/
|
| 1302 |
|
|
/* */
|
| 1303 |
|
|
/* Routine Name: ips_intr_copperhead */
|
| 1304 |
|
|
/* */
|
| 1305 |
|
|
/* Routine Description: */
|
| 1306 |
|
|
/* */
|
| 1307 |
|
|
/* Polling interrupt handler */
|
| 1308 |
|
|
/* */
|
| 1309 |
|
|
/* ASSUMES interrupts are disabled */
|
| 1310 |
|
|
/* */
|
| 1311 |
|
|
/****************************************************************************/
|
| 1312 |
|
|
void
|
| 1313 |
|
|
ips_intr_copperhead(ips_ha_t * ha)
|
| 1314 |
|
|
{
|
| 1315 |
|
|
ips_stat_t *sp;
|
| 1316 |
|
|
ips_scb_t *scb;
|
| 1317 |
|
|
IPS_STATUS cstatus;
|
| 1318 |
|
|
int intrstatus;
|
| 1319 |
|
|
|
| 1320 |
|
|
METHOD_TRACE("ips_intr", 2);
|
| 1321 |
|
|
|
| 1322 |
|
|
if (!ha)
|
| 1323 |
|
|
return;
|
| 1324 |
|
|
|
| 1325 |
|
|
if (!ha->active)
|
| 1326 |
|
|
return;
|
| 1327 |
|
|
|
| 1328 |
|
|
intrstatus = (*ha->func.isintr) (ha);
|
| 1329 |
|
|
|
| 1330 |
|
|
if (!intrstatus) {
|
| 1331 |
|
|
/*
|
| 1332 |
|
|
* Unexpected/Shared interrupt
|
| 1333 |
|
|
*/
|
| 1334 |
|
|
|
| 1335 |
|
|
return;
|
| 1336 |
|
|
}
|
| 1337 |
|
|
|
| 1338 |
|
|
while (TRUE) {
|
| 1339 |
|
|
sp = &ha->sp;
|
| 1340 |
|
|
|
| 1341 |
|
|
intrstatus = (*ha->func.isintr) (ha);
|
| 1342 |
|
|
|
| 1343 |
|
|
if (!intrstatus)
|
| 1344 |
|
|
break;
|
| 1345 |
|
|
else
|
| 1346 |
|
|
cstatus.value = (*ha->func.statupd) (ha);
|
| 1347 |
|
|
|
| 1348 |
|
|
if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
|
| 1349 |
|
|
/* Spurious Interupt ? */
|
| 1350 |
|
|
continue;
|
| 1351 |
|
|
}
|
| 1352 |
|
|
|
| 1353 |
|
|
ips_chkstatus(ha, &cstatus);
|
| 1354 |
|
|
scb = (ips_scb_t *) sp->scb_addr;
|
| 1355 |
|
|
|
| 1356 |
|
|
/*
|
| 1357 |
|
|
* use the callback function to finish things up
|
| 1358 |
|
|
* NOTE: interrupts are OFF for this
|
| 1359 |
|
|
*/
|
| 1360 |
|
|
(*scb->callback) (ha, scb);
|
| 1361 |
|
|
} /* end while */
|
| 1362 |
|
|
}
|
| 1363 |
|
|
|
| 1364 |
|
|
/****************************************************************************/
|
| 1365 |
|
|
/* */
|
| 1366 |
|
|
/* Routine Name: ips_intr_morpheus */
|
| 1367 |
|
|
/* */
|
| 1368 |
|
|
/* Routine Description: */
|
| 1369 |
|
|
/* */
|
| 1370 |
|
|
/* Polling interrupt handler */
|
| 1371 |
|
|
/* */
|
| 1372 |
|
|
/* ASSUMES interrupts are disabled */
|
| 1373 |
|
|
/* */
|
| 1374 |
|
|
/****************************************************************************/
|
| 1375 |
|
|
void
|
| 1376 |
|
|
ips_intr_morpheus(ips_ha_t * ha)
|
| 1377 |
|
|
{
|
| 1378 |
|
|
ips_stat_t *sp;
|
| 1379 |
|
|
ips_scb_t *scb;
|
| 1380 |
|
|
IPS_STATUS cstatus;
|
| 1381 |
|
|
int intrstatus;
|
| 1382 |
|
|
|
| 1383 |
|
|
METHOD_TRACE("ips_intr_morpheus", 2);
|
| 1384 |
|
|
|
| 1385 |
|
|
if (!ha)
|
| 1386 |
|
|
return;
|
| 1387 |
|
|
|
| 1388 |
|
|
if (!ha->active)
|
| 1389 |
|
|
return;
|
| 1390 |
|
|
|
| 1391 |
|
|
intrstatus = (*ha->func.isintr) (ha);
|
| 1392 |
|
|
|
| 1393 |
|
|
if (!intrstatus) {
|
| 1394 |
|
|
/*
|
| 1395 |
|
|
* Unexpected/Shared interrupt
|
| 1396 |
|
|
*/
|
| 1397 |
|
|
|
| 1398 |
|
|
return;
|
| 1399 |
|
|
}
|
| 1400 |
|
|
|
| 1401 |
|
|
while (TRUE) {
|
| 1402 |
|
|
sp = &ha->sp;
|
| 1403 |
|
|
|
| 1404 |
|
|
intrstatus = (*ha->func.isintr) (ha);
|
| 1405 |
|
|
|
| 1406 |
|
|
if (!intrstatus)
|
| 1407 |
|
|
break;
|
| 1408 |
|
|
else
|
| 1409 |
|
|
cstatus.value = (*ha->func.statupd) (ha);
|
| 1410 |
|
|
|
| 1411 |
|
|
if (cstatus.value == 0xffffffff)
|
| 1412 |
|
|
/* No more to process */
|
| 1413 |
|
|
break;
|
| 1414 |
|
|
|
| 1415 |
|
|
if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
|
| 1416 |
|
|
printk(KERN_WARNING
|
| 1417 |
|
|
"(%s%d) Spurious interrupt; no ccb.\n", ips_name,
|
| 1418 |
|
|
ha->host_num);
|
| 1419 |
|
|
|
| 1420 |
|
|
continue;
|
| 1421 |
|
|
}
|
| 1422 |
|
|
|
| 1423 |
|
|
ips_chkstatus(ha, &cstatus);
|
| 1424 |
|
|
scb = (ips_scb_t *) sp->scb_addr;
|
| 1425 |
|
|
|
| 1426 |
|
|
/*
|
| 1427 |
|
|
* use the callback function to finish things up
|
| 1428 |
|
|
* NOTE: interrupts are OFF for this
|
| 1429 |
|
|
*/
|
| 1430 |
|
|
(*scb->callback) (ha, scb);
|
| 1431 |
|
|
} /* end while */
|
| 1432 |
|
|
}
|
| 1433 |
|
|
|
| 1434 |
|
|
/****************************************************************************/
|
| 1435 |
|
|
/* */
|
| 1436 |
|
|
/* Routine Name: ips_info */
|
| 1437 |
|
|
/* */
|
| 1438 |
|
|
/* Routine Description: */
|
| 1439 |
|
|
/* */
|
| 1440 |
|
|
/* Return info about the driver */
|
| 1441 |
|
|
/* */
|
| 1442 |
|
|
/****************************************************************************/
|
| 1443 |
|
|
const char *
|
| 1444 |
|
|
ips_info(struct Scsi_Host *SH)
|
| 1445 |
|
|
{
|
| 1446 |
|
|
static char buffer[256];
|
| 1447 |
|
|
char *bp;
|
| 1448 |
|
|
ips_ha_t *ha;
|
| 1449 |
|
|
|
| 1450 |
|
|
METHOD_TRACE("ips_info", 1);
|
| 1451 |
|
|
|
| 1452 |
|
|
ha = IPS_HA(SH);
|
| 1453 |
|
|
|
| 1454 |
|
|
if (!ha)
|
| 1455 |
|
|
return (NULL);
|
| 1456 |
|
|
|
| 1457 |
|
|
bp = &buffer[0];
|
| 1458 |
|
|
memset(bp, 0, sizeof (buffer));
|
| 1459 |
|
|
|
| 1460 |
|
|
sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
|
| 1461 |
|
|
IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
|
| 1462 |
|
|
|
| 1463 |
|
|
if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
|
| 1464 |
|
|
strcat(bp, " <");
|
| 1465 |
|
|
strcat(bp, ips_adapter_name[ha->ad_type - 1]);
|
| 1466 |
|
|
strcat(bp, ">");
|
| 1467 |
|
|
}
|
| 1468 |
|
|
|
| 1469 |
|
|
return (bp);
|
| 1470 |
|
|
}
|
| 1471 |
|
|
|
| 1472 |
|
|
/****************************************************************************/
|
| 1473 |
|
|
/* */
|
| 1474 |
|
|
/* Routine Name: ips_proc_info */
|
| 1475 |
|
|
/* */
|
| 1476 |
|
|
/* Routine Description: */
|
| 1477 |
|
|
/* */
|
| 1478 |
|
|
/* The passthru interface for the driver */
|
| 1479 |
|
|
/* */
|
| 1480 |
|
|
/****************************************************************************/
|
| 1481 |
|
|
int
|
| 1482 |
|
|
ips_proc_info(char *buffer, char **start, off_t offset,
|
| 1483 |
|
|
int length, int hostno, int func)
|
| 1484 |
|
|
{
|
| 1485 |
|
|
int i;
|
| 1486 |
|
|
int ret;
|
| 1487 |
|
|
ips_ha_t *ha = NULL;
|
| 1488 |
|
|
|
| 1489 |
|
|
METHOD_TRACE("ips_proc_info", 1);
|
| 1490 |
|
|
|
| 1491 |
|
|
/* Find our host structure */
|
| 1492 |
|
|
for (i = 0; i < ips_next_controller; i++) {
|
| 1493 |
|
|
if (ips_sh[i]) {
|
| 1494 |
|
|
if (ips_sh[i]->host_no == hostno) {
|
| 1495 |
|
|
ha = (ips_ha_t *) ips_sh[i]->hostdata;
|
| 1496 |
|
|
break;
|
| 1497 |
|
|
}
|
| 1498 |
|
|
}
|
| 1499 |
|
|
}
|
| 1500 |
|
|
|
| 1501 |
|
|
if (!ha)
|
| 1502 |
|
|
return (-EINVAL);
|
| 1503 |
|
|
|
| 1504 |
|
|
if (func) {
|
| 1505 |
|
|
/* write */
|
| 1506 |
|
|
return (0);
|
| 1507 |
|
|
} else {
|
| 1508 |
|
|
/* read */
|
| 1509 |
|
|
if (start)
|
| 1510 |
|
|
*start = buffer;
|
| 1511 |
|
|
|
| 1512 |
|
|
ret = ips_host_info(ha, buffer, offset, length);
|
| 1513 |
|
|
|
| 1514 |
|
|
return (ret);
|
| 1515 |
|
|
}
|
| 1516 |
|
|
}
|
| 1517 |
|
|
|
| 1518 |
|
|
/*--------------------------------------------------------------------------*/
|
| 1519 |
|
|
/* Helper Functions */
|
| 1520 |
|
|
/*--------------------------------------------------------------------------*/
|
| 1521 |
|
|
|
| 1522 |
|
|
/****************************************************************************/
|
| 1523 |
|
|
/* */
|
| 1524 |
|
|
/* Routine Name: ips_is_passthru */
|
| 1525 |
|
|
/* */
|
| 1526 |
|
|
/* Routine Description: */
|
| 1527 |
|
|
/* */
|
| 1528 |
|
|
/* Determine if the specified SCSI command is really a passthru command */
|
| 1529 |
|
|
/* */
|
| 1530 |
|
|
/****************************************************************************/
|
| 1531 |
|
|
static int
|
| 1532 |
|
|
ips_is_passthru(Scsi_Cmnd * SC)
|
| 1533 |
|
|
{
|
| 1534 |
|
|
METHOD_TRACE("ips_is_passthru", 1);
|
| 1535 |
|
|
|
| 1536 |
|
|
if (!SC)
|
| 1537 |
|
|
return (0);
|
| 1538 |
|
|
|
| 1539 |
|
|
if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
|
| 1540 |
|
|
(SC->channel == 0) &&
|
| 1541 |
|
|
(SC->target == IPS_ADAPTER_ID) &&
|
| 1542 |
|
|
(SC->lun == 0) && SC->request_buffer) {
|
| 1543 |
|
|
if ((!SC->use_sg) && SC->request_bufflen &&
|
| 1544 |
|
|
(((char *) SC->request_buffer)[0] == 'C') &&
|
| 1545 |
|
|
(((char *) SC->request_buffer)[1] == 'O') &&
|
| 1546 |
|
|
(((char *) SC->request_buffer)[2] == 'P') &&
|
| 1547 |
|
|
(((char *) SC->request_buffer)[3] == 'P'))
|
| 1548 |
|
|
return 1;
|
| 1549 |
|
|
else if (SC->use_sg) {
|
| 1550 |
|
|
struct scatterlist *sg = SC->request_buffer;
|
| 1551 |
|
|
char *buffer = IPS_SG_ADDRESS(sg);
|
| 1552 |
|
|
if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
|
| 1553 |
|
|
buffer[2] == 'P' && buffer[3] == 'P')
|
| 1554 |
|
|
return 1;
|
| 1555 |
|
|
}
|
| 1556 |
|
|
}
|
| 1557 |
|
|
return 0;
|
| 1558 |
|
|
}
|
| 1559 |
|
|
|
| 1560 |
|
|
/****************************************************************************/
|
| 1561 |
|
|
/* */
|
| 1562 |
|
|
/* Routine Name: ips_alloc_passthru_buffer */
|
| 1563 |
|
|
/* */
|
| 1564 |
|
|
/* Routine Description: */
|
| 1565 |
|
|
/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
|
| 1566 |
|
|
/* is too small or doesn't exist */
|
| 1567 |
|
|
/****************************************************************************/
|
| 1568 |
|
|
static int
|
| 1569 |
|
|
ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
|
| 1570 |
|
|
{
|
| 1571 |
|
|
void *bigger_buf;
|
| 1572 |
|
|
dma_addr_t dma_busaddr;
|
| 1573 |
|
|
|
| 1574 |
|
|
if (ha->ioctl_data && length <= ha->ioctl_len)
|
| 1575 |
|
|
return 0;
|
| 1576 |
|
|
/* there is no buffer or it's not big enough, allocate a new one */
|
| 1577 |
|
|
bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
|
| 1578 |
|
|
if (bigger_buf) {
|
| 1579 |
|
|
/* free the old memory */
|
| 1580 |
|
|
pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
|
| 1581 |
|
|
ha->ioctl_busaddr);
|
| 1582 |
|
|
/* use the new memory */
|
| 1583 |
|
|
ha->ioctl_data = (char *) bigger_buf;
|
| 1584 |
|
|
ha->ioctl_len = length;
|
| 1585 |
|
|
ha->ioctl_busaddr = dma_busaddr;
|
| 1586 |
|
|
} else {
|
| 1587 |
|
|
return -1;
|
| 1588 |
|
|
}
|
| 1589 |
|
|
return 0;
|
| 1590 |
|
|
}
|
| 1591 |
|
|
|
| 1592 |
|
|
/****************************************************************************/
|
| 1593 |
|
|
/* */
|
| 1594 |
|
|
/* Routine Name: ips_make_passthru */
|
| 1595 |
|
|
/* */
|
| 1596 |
|
|
/* Routine Description: */
|
| 1597 |
|
|
/* */
|
| 1598 |
|
|
/* Make a passthru command out of the info in the Scsi block */
|
| 1599 |
|
|
/* */
|
| 1600 |
|
|
/****************************************************************************/
|
| 1601 |
|
|
static int
|
| 1602 |
|
|
ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
|
| 1603 |
|
|
{
|
| 1604 |
|
|
ips_passthru_t *pt;
|
| 1605 |
|
|
int length = 0;
|
| 1606 |
|
|
int ret;
|
| 1607 |
|
|
|
| 1608 |
|
|
METHOD_TRACE("ips_make_passthru", 1);
|
| 1609 |
|
|
|
| 1610 |
|
|
if (!SC->use_sg) {
|
| 1611 |
|
|
length = SC->request_bufflen;
|
| 1612 |
|
|
} else {
|
| 1613 |
|
|
struct scatterlist *sg = SC->request_buffer;
|
| 1614 |
|
|
int i;
|
| 1615 |
|
|
for (i = 0; i < SC->use_sg; i++)
|
| 1616 |
|
|
length += sg[i].length;
|
| 1617 |
|
|
}
|
| 1618 |
|
|
if (length < sizeof (ips_passthru_t)) {
|
| 1619 |
|
|
/* wrong size */
|
| 1620 |
|
|
DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
|
| 1621 |
|
|
ips_name, ha->host_num);
|
| 1622 |
|
|
return (IPS_FAILURE);
|
| 1623 |
|
|
}
|
| 1624 |
|
|
if (ips_alloc_passthru_buffer(ha, length)) {
|
| 1625 |
|
|
/* allocation failure! If ha->ioctl_data exists, use it to return
|
| 1626 |
|
|
some error codes. Return a failed command to the scsi layer. */
|
| 1627 |
|
|
if (ha->ioctl_data) {
|
| 1628 |
|
|
pt = (ips_passthru_t *) ha->ioctl_data;
|
| 1629 |
|
|
ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
|
| 1630 |
|
|
pt->BasicStatus = 0x0B;
|
| 1631 |
|
|
pt->ExtendedStatus = 0x00;
|
| 1632 |
|
|
ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
|
| 1633 |
|
|
}
|
| 1634 |
|
|
return IPS_FAILURE;
|
| 1635 |
|
|
}
|
| 1636 |
|
|
ha->ioctl_datasize = length;
|
| 1637 |
|
|
|
| 1638 |
|
|
ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
|
| 1639 |
|
|
pt = (ips_passthru_t *) ha->ioctl_data;
|
| 1640 |
|
|
|
| 1641 |
|
|
/*
|
| 1642 |
|
|
* Some notes about the passthru interface used
|
| 1643 |
|
|
*
|
| 1644 |
|
|
* IF the scsi op_code == 0x0d then we assume
|
| 1645 |
|
|
* that the data came along with/goes with the
|
| 1646 |
|
|
* packet we received from the sg driver. In this
|
| 1647 |
|
|
* case the CmdBSize field of the pt structure is
|
| 1648 |
|
|
* used for the size of the buffer.
|
| 1649 |
|
|
*/
|
| 1650 |
|
|
|
| 1651 |
|
|
switch (pt->CoppCmd) {
|
| 1652 |
|
|
case IPS_NUMCTRLS:
|
| 1653 |
|
|
memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
|
| 1654 |
|
|
&ips_num_controllers, sizeof (int));
|
| 1655 |
|
|
ips_scmd_buf_write(SC, ha->ioctl_data,
|
| 1656 |
|
|
sizeof (ips_passthru_t) + sizeof (int));
|
| 1657 |
|
|
SC->result = DID_OK << 16;
|
| 1658 |
|
|
|
| 1659 |
|
|
return (IPS_SUCCESS_IMM);
|
| 1660 |
|
|
|
| 1661 |
|
|
case IPS_COPPUSRCMD:
|
| 1662 |
|
|
case IPS_COPPIOCCMD:
|
| 1663 |
|
|
if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
|
| 1664 |
|
|
if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
|
| 1665 |
|
|
/* wrong size */
|
| 1666 |
|
|
DEBUG_VAR(1,
|
| 1667 |
|
|
"(%s%d) Passthru structure wrong size",
|
| 1668 |
|
|
ips_name, ha->host_num);
|
| 1669 |
|
|
|
| 1670 |
|
|
return (IPS_FAILURE);
|
| 1671 |
|
|
}
|
| 1672 |
|
|
|
| 1673 |
|
|
if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
|
| 1674 |
|
|
pt->CoppCP.cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW) {
|
| 1675 |
|
|
ret = ips_flash_copperhead(ha, pt, scb);
|
| 1676 |
|
|
ips_scmd_buf_write(SC, ha->ioctl_data,
|
| 1677 |
|
|
sizeof (ips_passthru_t));
|
| 1678 |
|
|
return ret;
|
| 1679 |
|
|
}
|
| 1680 |
|
|
if (ips_usrcmd(ha, pt, scb))
|
| 1681 |
|
|
return (IPS_SUCCESS);
|
| 1682 |
|
|
else
|
| 1683 |
|
|
return (IPS_FAILURE);
|
| 1684 |
|
|
}
|
| 1685 |
|
|
|
| 1686 |
|
|
break;
|
| 1687 |
|
|
|
| 1688 |
|
|
} /* end switch */
|
| 1689 |
|
|
|
| 1690 |
|
|
return (IPS_FAILURE);
|
| 1691 |
|
|
}
|
| 1692 |
|
|
|
| 1693 |
|
|
/****************************************************************************/
|
| 1694 |
|
|
/* Routine Name: ips_flash_copperhead */
|
| 1695 |
|
|
/* Routine Description: */
|
| 1696 |
|
|
/* Flash the BIOS/FW on a Copperhead style controller */
|
| 1697 |
|
|
/****************************************************************************/
|
| 1698 |
|
|
static int
|
| 1699 |
|
|
ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
|
| 1700 |
|
|
{
|
| 1701 |
|
|
int datasize;
|
| 1702 |
|
|
|
| 1703 |
|
|
/* Trombone is the only copperhead that can do packet flash, but only
|
| 1704 |
|
|
* for firmware. No one said it had to make sence. */
|
| 1705 |
|
|
if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
|
| 1706 |
|
|
if (ips_usrcmd(ha, pt, scb))
|
| 1707 |
|
|
return IPS_SUCCESS;
|
| 1708 |
|
|
else
|
| 1709 |
|
|
return IPS_FAILURE;
|
| 1710 |
|
|
}
|
| 1711 |
|
|
pt->BasicStatus = 0x0B;
|
| 1712 |
|
|
pt->ExtendedStatus = 0;
|
| 1713 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 1714 |
|
|
/* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
|
| 1715 |
|
|
/* avoid allocating a huge buffer per adapter ( which can fail ). */
|
| 1716 |
|
|
if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
|
| 1717 |
|
|
pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
|
| 1718 |
|
|
pt->BasicStatus = 0;
|
| 1719 |
|
|
return ips_flash_bios(ha, pt, scb);
|
| 1720 |
|
|
} else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
|
| 1721 |
|
|
if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
|
| 1722 |
|
|
ha->flash_data = ips_FlashData;
|
| 1723 |
|
|
ha->flash_busaddr = ips_flashbusaddr;
|
| 1724 |
|
|
ha->flash_len = PAGE_SIZE << 7;
|
| 1725 |
|
|
ha->flash_datasize = 0;
|
| 1726 |
|
|
} else if (!ha->flash_data) {
|
| 1727 |
|
|
datasize = pt->CoppCP.cmd.flashfw.total_packets *
|
| 1728 |
|
|
pt->CoppCP.cmd.flashfw.count;
|
| 1729 |
|
|
ha->flash_data = pci_alloc_consistent(ha->pcidev,
|
| 1730 |
|
|
datasize,
|
| 1731 |
|
|
&ha->flash_busaddr);
|
| 1732 |
|
|
if (!ha->flash_data){
|
| 1733 |
|
|
printk(KERN_WARNING "Unable to allocate a flash buffer\n");
|
| 1734 |
|
|
return IPS_FAILURE;
|
| 1735 |
|
|
}
|
| 1736 |
|
|
ha->flash_datasize = 0;
|
| 1737 |
|
|
ha->flash_len = datasize;
|
| 1738 |
|
|
} else
|
| 1739 |
|
|
return IPS_FAILURE;
|
| 1740 |
|
|
} else {
|
| 1741 |
|
|
if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
|
| 1742 |
|
|
ha->flash_len) {
|
| 1743 |
|
|
ips_free_flash_copperhead(ha);
|
| 1744 |
|
|
printk(KERN_WARNING "failed size sanity check\n");
|
| 1745 |
|
|
return IPS_FAILURE;
|
| 1746 |
|
|
}
|
| 1747 |
|
|
}
|
| 1748 |
|
|
if (!ha->flash_data)
|
| 1749 |
|
|
return IPS_FAILURE;
|
| 1750 |
|
|
pt->BasicStatus = 0;
|
| 1751 |
|
|
memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
|
| 1752 |
|
|
pt->CoppCP.cmd.flashfw.count);
|
| 1753 |
|
|
ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
|
| 1754 |
|
|
if (pt->CoppCP.cmd.flashfw.packet_num ==
|
| 1755 |
|
|
pt->CoppCP.cmd.flashfw.total_packets - 1) {
|
| 1756 |
|
|
if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
|
| 1757 |
|
|
return ips_flash_bios(ha, pt, scb);
|
| 1758 |
|
|
else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
|
| 1759 |
|
|
return ips_flash_firmware(ha, pt, scb);
|
| 1760 |
|
|
}
|
| 1761 |
|
|
return IPS_SUCCESS_IMM;
|
| 1762 |
|
|
}
|
| 1763 |
|
|
|
| 1764 |
|
|
/****************************************************************************/
|
| 1765 |
|
|
/* Routine Name: ips_flash_bios */
|
| 1766 |
|
|
/* Routine Description: */
|
| 1767 |
|
|
/* flashes the bios of a copperhead adapter */
|
| 1768 |
|
|
/****************************************************************************/
|
| 1769 |
|
|
static int
|
| 1770 |
|
|
ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
|
| 1771 |
|
|
{
|
| 1772 |
|
|
|
| 1773 |
|
|
if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
|
| 1774 |
|
|
pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
|
| 1775 |
|
|
if ((!ha->func.programbios) || (!ha->func.erasebios) ||
|
| 1776 |
|
|
(!ha->func.verifybios)) goto error;
|
| 1777 |
|
|
if ((*ha->func.erasebios) (ha)) {
|
| 1778 |
|
|
DEBUG_VAR(1,
|
| 1779 |
|
|
"(%s%d) flash bios failed - unable to erase flash",
|
| 1780 |
|
|
ips_name, ha->host_num);
|
| 1781 |
|
|
goto error;
|
| 1782 |
|
|
} else
|
| 1783 |
|
|
if ((*ha->func.programbios)
|
| 1784 |
|
|
(ha, ha->flash_data + IPS_BIOS_HEADER,
|
| 1785 |
|
|
ha->flash_datasize - IPS_BIOS_HEADER, 0)) {
|
| 1786 |
|
|
DEBUG_VAR(1,
|
| 1787 |
|
|
"(%s%d) flash bios failed - unable to flash",
|
| 1788 |
|
|
ips_name, ha->host_num);
|
| 1789 |
|
|
goto error;
|
| 1790 |
|
|
} else
|
| 1791 |
|
|
if ((*ha->func.verifybios)
|
| 1792 |
|
|
(ha, ha->flash_data + IPS_BIOS_HEADER,
|
| 1793 |
|
|
ha->flash_datasize - IPS_BIOS_HEADER, 0)) {
|
| 1794 |
|
|
DEBUG_VAR(1,
|
| 1795 |
|
|
"(%s%d) flash bios failed - unable to verify flash",
|
| 1796 |
|
|
ips_name, ha->host_num);
|
| 1797 |
|
|
goto error;
|
| 1798 |
|
|
}
|
| 1799 |
|
|
ips_free_flash_copperhead(ha);
|
| 1800 |
|
|
return IPS_SUCCESS_IMM;
|
| 1801 |
|
|
} else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
|
| 1802 |
|
|
pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
|
| 1803 |
|
|
if (!ha->func.erasebios)
|
| 1804 |
|
|
goto error;
|
| 1805 |
|
|
if ((*ha->func.erasebios) (ha)) {
|
| 1806 |
|
|
DEBUG_VAR(1,
|
| 1807 |
|
|
"(%s%d) flash bios failed - unable to erase flash",
|
| 1808 |
|
|
ips_name, ha->host_num);
|
| 1809 |
|
|
goto error;
|
| 1810 |
|
|
}
|
| 1811 |
|
|
return IPS_SUCCESS_IMM;
|
| 1812 |
|
|
}
|
| 1813 |
|
|
error:
|
| 1814 |
|
|
pt->BasicStatus = 0x0B;
|
| 1815 |
|
|
pt->ExtendedStatus = 0x00;
|
| 1816 |
|
|
ips_free_flash_copperhead(ha);
|
| 1817 |
|
|
return IPS_FAILURE;
|
| 1818 |
|
|
}
|
| 1819 |
|
|
|
| 1820 |
|
|
/****************************************************************************/
|
| 1821 |
|
|
/* */
|
| 1822 |
|
|
/* Routine Name: ips_fill_scb_sg_single */
|
| 1823 |
|
|
/* */
|
| 1824 |
|
|
/* Routine Description: */
|
| 1825 |
|
|
/* Fill in a single scb sg_list element from an address */
|
| 1826 |
|
|
/* return a -1 if a breakup occured */
|
| 1827 |
|
|
/****************************************************************************/
|
| 1828 |
|
|
static inline int
|
| 1829 |
|
|
ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
|
| 1830 |
|
|
ips_scb_t * scb, int indx, unsigned int e_len)
|
| 1831 |
|
|
{
|
| 1832 |
|
|
|
| 1833 |
|
|
int ret_val = 0;
|
| 1834 |
|
|
|
| 1835 |
|
|
if ((scb->data_len + e_len) > ha->max_xfer) {
|
| 1836 |
|
|
e_len = ha->max_xfer - scb->data_len;
|
| 1837 |
|
|
scb->breakup = indx;
|
| 1838 |
|
|
++scb->sg_break;
|
| 1839 |
|
|
ret_val = -1;
|
| 1840 |
|
|
} else {
|
| 1841 |
|
|
scb->breakup = 0;
|
| 1842 |
|
|
scb->sg_break = 0;
|
| 1843 |
|
|
}
|
| 1844 |
|
|
if (IPS_USE_ENH_SGLIST(ha)) {
|
| 1845 |
|
|
scb->sg_list.enh_list[indx].address_lo =
|
| 1846 |
|
|
cpu_to_le32(pci_dma_lo32(busaddr));
|
| 1847 |
|
|
scb->sg_list.enh_list[indx].address_hi =
|
| 1848 |
|
|
cpu_to_le32(pci_dma_hi32(busaddr));
|
| 1849 |
|
|
scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
|
| 1850 |
|
|
} else {
|
| 1851 |
|
|
scb->sg_list.std_list[indx].address =
|
| 1852 |
|
|
cpu_to_le32(pci_dma_lo32(busaddr));
|
| 1853 |
|
|
scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
|
| 1854 |
|
|
}
|
| 1855 |
|
|
|
| 1856 |
|
|
++scb->sg_len;
|
| 1857 |
|
|
scb->data_len += e_len;
|
| 1858 |
|
|
return ret_val;
|
| 1859 |
|
|
}
|
| 1860 |
|
|
|
| 1861 |
|
|
/****************************************************************************/
|
| 1862 |
|
|
/* Routine Name: ips_flash_firmware */
|
| 1863 |
|
|
/* Routine Description: */
|
| 1864 |
|
|
/* flashes the firmware of a copperhead adapter */
|
| 1865 |
|
|
/****************************************************************************/
|
| 1866 |
|
|
static int
|
| 1867 |
|
|
ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
|
| 1868 |
|
|
{
|
| 1869 |
|
|
IPS_SG_LIST sg_list;
|
| 1870 |
|
|
uint32_t cmd_busaddr;
|
| 1871 |
|
|
|
| 1872 |
|
|
if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
|
| 1873 |
|
|
pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
|
| 1874 |
|
|
memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
|
| 1875 |
|
|
pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
|
| 1876 |
|
|
pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
|
| 1877 |
|
|
} else {
|
| 1878 |
|
|
pt->BasicStatus = 0x0B;
|
| 1879 |
|
|
pt->ExtendedStatus = 0x00;
|
| 1880 |
|
|
ips_free_flash_copperhead(ha);
|
| 1881 |
|
|
return IPS_FAILURE;
|
| 1882 |
|
|
}
|
| 1883 |
|
|
/* Save the S/G list pointer so it doesn't get clobbered */
|
| 1884 |
|
|
sg_list.list = scb->sg_list.list;
|
| 1885 |
|
|
cmd_busaddr = scb->scb_busaddr;
|
| 1886 |
|
|
/* copy in the CP */
|
| 1887 |
|
|
memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
|
| 1888 |
|
|
/* FIX stuff that might be wrong */
|
| 1889 |
|
|
scb->sg_list.list = sg_list.list;
|
| 1890 |
|
|
scb->scb_busaddr = cmd_busaddr;
|
| 1891 |
|
|
scb->bus = scb->scsi_cmd->channel;
|
| 1892 |
|
|
scb->target_id = scb->scsi_cmd->target;
|
| 1893 |
|
|
scb->lun = scb->scsi_cmd->lun;
|
| 1894 |
|
|
scb->sg_len = 0;
|
| 1895 |
|
|
scb->data_len = 0;
|
| 1896 |
|
|
scb->flags = 0;
|
| 1897 |
|
|
scb->op_code = 0;
|
| 1898 |
|
|
scb->callback = ipsintr_done;
|
| 1899 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 1900 |
|
|
|
| 1901 |
|
|
scb->data_len = ha->flash_datasize;
|
| 1902 |
|
|
scb->data_busaddr =
|
| 1903 |
|
|
pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
|
| 1904 |
|
|
IPS_DMA_DIR(scb));
|
| 1905 |
|
|
scb->flags |= IPS_SCB_MAP_SINGLE;
|
| 1906 |
|
|
scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
|
| 1907 |
|
|
scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
|
| 1908 |
|
|
if (pt->TimeOut)
|
| 1909 |
|
|
scb->timeout = pt->TimeOut;
|
| 1910 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 1911 |
|
|
return IPS_SUCCESS;
|
| 1912 |
|
|
}
|
| 1913 |
|
|
|
| 1914 |
|
|
/****************************************************************************/
|
| 1915 |
|
|
/* Routine Name: ips_free_flash_copperhead */
|
| 1916 |
|
|
/* Routine Description: */
|
| 1917 |
|
|
/* release the memory resources used to hold the flash image */
|
| 1918 |
|
|
/****************************************************************************/
|
| 1919 |
|
|
static void
|
| 1920 |
|
|
ips_free_flash_copperhead(ips_ha_t * ha)
|
| 1921 |
|
|
{
|
| 1922 |
|
|
if (ha->flash_data == ips_FlashData)
|
| 1923 |
|
|
test_and_clear_bit(0, &ips_FlashDataInUse);
|
| 1924 |
|
|
else if (ha->flash_data)
|
| 1925 |
|
|
pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
|
| 1926 |
|
|
ha->flash_busaddr);
|
| 1927 |
|
|
ha->flash_data = NULL;
|
| 1928 |
|
|
}
|
| 1929 |
|
|
|
| 1930 |
|
|
/****************************************************************************/
|
| 1931 |
|
|
/* */
|
| 1932 |
|
|
/* Routine Name: ips_usrcmd */
|
| 1933 |
|
|
/* */
|
| 1934 |
|
|
/* Routine Description: */
|
| 1935 |
|
|
/* */
|
| 1936 |
|
|
/* Process a user command and make it ready to send */
|
| 1937 |
|
|
/* */
|
| 1938 |
|
|
/****************************************************************************/
|
| 1939 |
|
|
static int
|
| 1940 |
|
|
ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
|
| 1941 |
|
|
{
|
| 1942 |
|
|
IPS_SG_LIST sg_list;
|
| 1943 |
|
|
uint32_t cmd_busaddr;
|
| 1944 |
|
|
|
| 1945 |
|
|
METHOD_TRACE("ips_usrcmd", 1);
|
| 1946 |
|
|
|
| 1947 |
|
|
if ((!scb) || (!pt) || (!ha))
|
| 1948 |
|
|
return (0);
|
| 1949 |
|
|
|
| 1950 |
|
|
/* Save the S/G list pointer so it doesn't get clobbered */
|
| 1951 |
|
|
sg_list.list = scb->sg_list.list;
|
| 1952 |
|
|
cmd_busaddr = scb->scb_busaddr;
|
| 1953 |
|
|
/* copy in the CP */
|
| 1954 |
|
|
memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
|
| 1955 |
|
|
memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
|
| 1956 |
|
|
|
| 1957 |
|
|
/* FIX stuff that might be wrong */
|
| 1958 |
|
|
scb->sg_list.list = sg_list.list;
|
| 1959 |
|
|
scb->scb_busaddr = cmd_busaddr;
|
| 1960 |
|
|
scb->bus = scb->scsi_cmd->channel;
|
| 1961 |
|
|
scb->target_id = scb->scsi_cmd->target;
|
| 1962 |
|
|
scb->lun = scb->scsi_cmd->lun;
|
| 1963 |
|
|
scb->sg_len = 0;
|
| 1964 |
|
|
scb->data_len = 0;
|
| 1965 |
|
|
scb->flags = 0;
|
| 1966 |
|
|
scb->op_code = 0;
|
| 1967 |
|
|
scb->callback = ipsintr_done;
|
| 1968 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 1969 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 1970 |
|
|
|
| 1971 |
|
|
/* we don't support DCDB/READ/WRITE Scatter Gather */
|
| 1972 |
|
|
if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
|
| 1973 |
|
|
(scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
|
| 1974 |
|
|
(scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
|
| 1975 |
|
|
return (0);
|
| 1976 |
|
|
|
| 1977 |
|
|
if (pt->CmdBSize) {
|
| 1978 |
|
|
scb->data_len = pt->CmdBSize;
|
| 1979 |
|
|
scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
|
| 1980 |
|
|
} else {
|
| 1981 |
|
|
scb->data_busaddr = 0L;
|
| 1982 |
|
|
}
|
| 1983 |
|
|
|
| 1984 |
|
|
if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
|
| 1985 |
|
|
scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
|
| 1986 |
|
|
(unsigned long) &scb->
|
| 1987 |
|
|
dcdb -
|
| 1988 |
|
|
(unsigned long) scb);
|
| 1989 |
|
|
|
| 1990 |
|
|
if (pt->CmdBSize) {
|
| 1991 |
|
|
if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
|
| 1992 |
|
|
scb->dcdb.buffer_pointer =
|
| 1993 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 1994 |
|
|
else
|
| 1995 |
|
|
scb->cmd.basic_io.sg_addr =
|
| 1996 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 1997 |
|
|
}
|
| 1998 |
|
|
|
| 1999 |
|
|
/* set timeouts */
|
| 2000 |
|
|
if (pt->TimeOut) {
|
| 2001 |
|
|
scb->timeout = pt->TimeOut;
|
| 2002 |
|
|
|
| 2003 |
|
|
if (pt->TimeOut <= 10)
|
| 2004 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
|
| 2005 |
|
|
else if (pt->TimeOut <= 60)
|
| 2006 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
|
| 2007 |
|
|
else
|
| 2008 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
|
| 2009 |
|
|
}
|
| 2010 |
|
|
|
| 2011 |
|
|
/* assume success */
|
| 2012 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 2013 |
|
|
|
| 2014 |
|
|
/* success */
|
| 2015 |
|
|
return (1);
|
| 2016 |
|
|
}
|
| 2017 |
|
|
|
| 2018 |
|
|
/****************************************************************************/
|
| 2019 |
|
|
/* */
|
| 2020 |
|
|
/* Routine Name: ips_cleanup_passthru */
|
| 2021 |
|
|
/* */
|
| 2022 |
|
|
/* Routine Description: */
|
| 2023 |
|
|
/* */
|
| 2024 |
|
|
/* Cleanup after a passthru command */
|
| 2025 |
|
|
/* */
|
| 2026 |
|
|
/****************************************************************************/
|
| 2027 |
|
|
static void
|
| 2028 |
|
|
ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
|
| 2029 |
|
|
{
|
| 2030 |
|
|
ips_passthru_t *pt;
|
| 2031 |
|
|
|
| 2032 |
|
|
METHOD_TRACE("ips_cleanup_passthru", 1);
|
| 2033 |
|
|
|
| 2034 |
|
|
if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
|
| 2035 |
|
|
DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
|
| 2036 |
|
|
ips_name, ha->host_num);
|
| 2037 |
|
|
|
| 2038 |
|
|
return;
|
| 2039 |
|
|
}
|
| 2040 |
|
|
pt = (ips_passthru_t *) ha->ioctl_data;
|
| 2041 |
|
|
|
| 2042 |
|
|
/* Copy data back to the user */
|
| 2043 |
|
|
if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
|
| 2044 |
|
|
memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
|
| 2045 |
|
|
|
| 2046 |
|
|
pt->BasicStatus = scb->basic_status;
|
| 2047 |
|
|
pt->ExtendedStatus = scb->extended_status;
|
| 2048 |
|
|
pt->AdapterType = ha->ad_type;
|
| 2049 |
|
|
|
| 2050 |
|
|
if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
|
| 2051 |
|
|
(scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
|
| 2052 |
|
|
scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
|
| 2053 |
|
|
ips_free_flash_copperhead(ha);
|
| 2054 |
|
|
|
| 2055 |
|
|
ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
|
| 2056 |
|
|
}
|
| 2057 |
|
|
|
| 2058 |
|
|
/****************************************************************************/
|
| 2059 |
|
|
/* */
|
| 2060 |
|
|
/* Routine Name: ips_host_info */
|
| 2061 |
|
|
/* */
|
| 2062 |
|
|
/* Routine Description: */
|
| 2063 |
|
|
/* */
|
| 2064 |
|
|
/* The passthru interface for the driver */
|
| 2065 |
|
|
/* */
|
| 2066 |
|
|
/****************************************************************************/
|
| 2067 |
|
|
static int
|
| 2068 |
|
|
ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
|
| 2069 |
|
|
{
|
| 2070 |
|
|
IPS_INFOSTR info;
|
| 2071 |
|
|
|
| 2072 |
|
|
METHOD_TRACE("ips_host_info", 1);
|
| 2073 |
|
|
|
| 2074 |
|
|
info.buffer = ptr;
|
| 2075 |
|
|
info.length = len;
|
| 2076 |
|
|
info.offset = offset;
|
| 2077 |
|
|
info.pos = 0;
|
| 2078 |
|
|
info.localpos = 0;
|
| 2079 |
|
|
|
| 2080 |
|
|
copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
|
| 2081 |
|
|
|
| 2082 |
|
|
if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
|
| 2083 |
|
|
(le16_to_cpu(ha->nvram->adapter_type) != 0))
|
| 2084 |
|
|
copy_info(&info, "\tController Type : %s\n",
|
| 2085 |
|
|
ips_adapter_name[ha->ad_type - 1]);
|
| 2086 |
|
|
else
|
| 2087 |
|
|
copy_info(&info,
|
| 2088 |
|
|
"\tController Type : Unknown\n");
|
| 2089 |
|
|
|
| 2090 |
|
|
if (ha->io_addr)
|
| 2091 |
|
|
copy_info(&info,
|
| 2092 |
|
|
"\tIO region : 0x%lx (%d bytes)\n",
|
| 2093 |
|
|
ha->io_addr, ha->io_len);
|
| 2094 |
|
|
|
| 2095 |
|
|
if (ha->mem_addr) {
|
| 2096 |
|
|
copy_info(&info,
|
| 2097 |
|
|
"\tMemory region : 0x%lx (%d bytes)\n",
|
| 2098 |
|
|
ha->mem_addr, ha->mem_len);
|
| 2099 |
|
|
copy_info(&info,
|
| 2100 |
|
|
"\tShared memory address : 0x%lx\n",
|
| 2101 |
|
|
ha->mem_ptr);
|
| 2102 |
|
|
}
|
| 2103 |
|
|
|
| 2104 |
|
|
copy_info(&info, "\tIRQ number : %d\n", ha->irq);
|
| 2105 |
|
|
|
| 2106 |
|
|
if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG)
|
| 2107 |
|
|
copy_info(&info,
|
| 2108 |
|
|
"\tBIOS Version : %c%c%c%c%c%c%c%c\n",
|
| 2109 |
|
|
ha->nvram->bios_high[0], ha->nvram->bios_high[1],
|
| 2110 |
|
|
ha->nvram->bios_high[2], ha->nvram->bios_high[3],
|
| 2111 |
|
|
ha->nvram->bios_low[0], ha->nvram->bios_low[1],
|
| 2112 |
|
|
ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
|
| 2113 |
|
|
|
| 2114 |
|
|
copy_info(&info,
|
| 2115 |
|
|
"\tFirmware Version : %c%c%c%c%c%c%c%c\n",
|
| 2116 |
|
|
ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
|
| 2117 |
|
|
ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
|
| 2118 |
|
|
ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
|
| 2119 |
|
|
ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
|
| 2120 |
|
|
|
| 2121 |
|
|
copy_info(&info,
|
| 2122 |
|
|
"\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
|
| 2123 |
|
|
ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
|
| 2124 |
|
|
ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
|
| 2125 |
|
|
ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
|
| 2126 |
|
|
ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
|
| 2127 |
|
|
|
| 2128 |
|
|
copy_info(&info, "\tDriver Version : %s%s\n",
|
| 2129 |
|
|
IPS_VERSION_HIGH, IPS_VERSION_LOW);
|
| 2130 |
|
|
|
| 2131 |
|
|
copy_info(&info, "\tDriver Build : %d\n",
|
| 2132 |
|
|
IPS_BUILD_IDENT);
|
| 2133 |
|
|
|
| 2134 |
|
|
copy_info(&info, "\tMax Physical Devices : %d\n",
|
| 2135 |
|
|
ha->enq->ucMaxPhysicalDevices);
|
| 2136 |
|
|
copy_info(&info, "\tMax Active Commands : %d\n",
|
| 2137 |
|
|
ha->max_cmds);
|
| 2138 |
|
|
copy_info(&info, "\tCurrent Queued Commands : %d\n",
|
| 2139 |
|
|
ha->scb_waitlist.count);
|
| 2140 |
|
|
copy_info(&info, "\tCurrent Active Commands : %d\n",
|
| 2141 |
|
|
ha->scb_activelist.count - ha->num_ioctl);
|
| 2142 |
|
|
copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
|
| 2143 |
|
|
ha->copp_waitlist.count);
|
| 2144 |
|
|
copy_info(&info, "\tCurrent Active PT Commands : %d\n",
|
| 2145 |
|
|
ha->num_ioctl);
|
| 2146 |
|
|
|
| 2147 |
|
|
copy_info(&info, "\n");
|
| 2148 |
|
|
|
| 2149 |
|
|
return (info.localpos);
|
| 2150 |
|
|
}
|
| 2151 |
|
|
|
| 2152 |
|
|
/****************************************************************************/
|
| 2153 |
|
|
/* */
|
| 2154 |
|
|
/* Routine Name: copy_mem_info */
|
| 2155 |
|
|
/* */
|
| 2156 |
|
|
/* Routine Description: */
|
| 2157 |
|
|
/* */
|
| 2158 |
|
|
/* Copy data into an IPS_INFOSTR structure */
|
| 2159 |
|
|
/* */
|
| 2160 |
|
|
/****************************************************************************/
|
| 2161 |
|
|
static void
|
| 2162 |
|
|
copy_mem_info(IPS_INFOSTR * info, char *data, int len)
|
| 2163 |
|
|
{
|
| 2164 |
|
|
METHOD_TRACE("copy_mem_info", 1);
|
| 2165 |
|
|
|
| 2166 |
|
|
if (info->pos + len < info->offset) {
|
| 2167 |
|
|
info->pos += len;
|
| 2168 |
|
|
return;
|
| 2169 |
|
|
}
|
| 2170 |
|
|
|
| 2171 |
|
|
if (info->pos < info->offset) {
|
| 2172 |
|
|
data += (info->offset - info->pos);
|
| 2173 |
|
|
len -= (info->offset - info->pos);
|
| 2174 |
|
|
info->pos += (info->offset - info->pos);
|
| 2175 |
|
|
}
|
| 2176 |
|
|
|
| 2177 |
|
|
if (info->localpos + len > info->length)
|
| 2178 |
|
|
len = info->length - info->localpos;
|
| 2179 |
|
|
|
| 2180 |
|
|
if (len > 0) {
|
| 2181 |
|
|
memcpy(info->buffer + info->localpos, data, len);
|
| 2182 |
|
|
info->pos += len;
|
| 2183 |
|
|
info->localpos += len;
|
| 2184 |
|
|
}
|
| 2185 |
|
|
}
|
| 2186 |
|
|
|
| 2187 |
|
|
/****************************************************************************/
|
| 2188 |
|
|
/* */
|
| 2189 |
|
|
/* Routine Name: copy_info */
|
| 2190 |
|
|
/* */
|
| 2191 |
|
|
/* Routine Description: */
|
| 2192 |
|
|
/* */
|
| 2193 |
|
|
/* printf style wrapper for an info structure */
|
| 2194 |
|
|
/* */
|
| 2195 |
|
|
/****************************************************************************/
|
| 2196 |
|
|
static int
|
| 2197 |
|
|
copy_info(IPS_INFOSTR * info, char *fmt, ...)
|
| 2198 |
|
|
{
|
| 2199 |
|
|
va_list args;
|
| 2200 |
|
|
char buf[128];
|
| 2201 |
|
|
int len;
|
| 2202 |
|
|
|
| 2203 |
|
|
METHOD_TRACE("copy_info", 1);
|
| 2204 |
|
|
|
| 2205 |
|
|
va_start(args, fmt);
|
| 2206 |
|
|
len = vsprintf(buf, fmt, args);
|
| 2207 |
|
|
va_end(args);
|
| 2208 |
|
|
|
| 2209 |
|
|
copy_mem_info(info, buf, len);
|
| 2210 |
|
|
|
| 2211 |
|
|
return (len);
|
| 2212 |
|
|
}
|
| 2213 |
|
|
|
| 2214 |
|
|
/****************************************************************************/
|
| 2215 |
|
|
/* */
|
| 2216 |
|
|
/* Routine Name: ips_identify_controller */
|
| 2217 |
|
|
/* */
|
| 2218 |
|
|
/* Routine Description: */
|
| 2219 |
|
|
/* */
|
| 2220 |
|
|
/* Identify this controller */
|
| 2221 |
|
|
/* */
|
| 2222 |
|
|
/****************************************************************************/
|
| 2223 |
|
|
static void
|
| 2224 |
|
|
ips_identify_controller(ips_ha_t * ha)
|
| 2225 |
|
|
{
|
| 2226 |
|
|
METHOD_TRACE("ips_identify_controller", 1);
|
| 2227 |
|
|
|
| 2228 |
|
|
switch (ha->device_id) {
|
| 2229 |
|
|
case IPS_DEVICEID_COPPERHEAD:
|
| 2230 |
|
|
if (ha->revision_id <= IPS_REVID_SERVERAID) {
|
| 2231 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID;
|
| 2232 |
|
|
} else if (ha->revision_id == IPS_REVID_SERVERAID2) {
|
| 2233 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID2;
|
| 2234 |
|
|
} else if (ha->revision_id == IPS_REVID_NAVAJO) {
|
| 2235 |
|
|
ha->ad_type = IPS_ADTYPE_NAVAJO;
|
| 2236 |
|
|
} else if ((ha->revision_id == IPS_REVID_SERVERAID2)
|
| 2237 |
|
|
&& (ha->slot_num == 0)) {
|
| 2238 |
|
|
ha->ad_type = IPS_ADTYPE_KIOWA;
|
| 2239 |
|
|
} else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
|
| 2240 |
|
|
(ha->revision_id <= IPS_REVID_CLARINETP3)) {
|
| 2241 |
|
|
if (ha->enq->ucMaxPhysicalDevices == 15)
|
| 2242 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID3L;
|
| 2243 |
|
|
else
|
| 2244 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID3;
|
| 2245 |
|
|
} else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
|
| 2246 |
|
|
(ha->revision_id <= IPS_REVID_TROMBONE64)) {
|
| 2247 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID4H;
|
| 2248 |
|
|
}
|
| 2249 |
|
|
break;
|
| 2250 |
|
|
|
| 2251 |
|
|
case IPS_DEVICEID_MORPHEUS:
|
| 2252 |
|
|
switch (ha->subdevice_id) {
|
| 2253 |
|
|
case IPS_SUBDEVICEID_4L:
|
| 2254 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID4L;
|
| 2255 |
|
|
break;
|
| 2256 |
|
|
|
| 2257 |
|
|
case IPS_SUBDEVICEID_4M:
|
| 2258 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID4M;
|
| 2259 |
|
|
break;
|
| 2260 |
|
|
|
| 2261 |
|
|
case IPS_SUBDEVICEID_4MX:
|
| 2262 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
|
| 2263 |
|
|
break;
|
| 2264 |
|
|
|
| 2265 |
|
|
case IPS_SUBDEVICEID_4LX:
|
| 2266 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
|
| 2267 |
|
|
break;
|
| 2268 |
|
|
|
| 2269 |
|
|
case IPS_SUBDEVICEID_5I2:
|
| 2270 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
|
| 2271 |
|
|
break;
|
| 2272 |
|
|
|
| 2273 |
|
|
case IPS_SUBDEVICEID_5I1:
|
| 2274 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
|
| 2275 |
|
|
break;
|
| 2276 |
|
|
}
|
| 2277 |
|
|
|
| 2278 |
|
|
break;
|
| 2279 |
|
|
|
| 2280 |
|
|
case IPS_DEVICEID_MARCO:
|
| 2281 |
|
|
switch (ha->subdevice_id) {
|
| 2282 |
|
|
case IPS_SUBDEVICEID_6M:
|
| 2283 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID6M;
|
| 2284 |
|
|
break;
|
| 2285 |
|
|
case IPS_SUBDEVICEID_6I:
|
| 2286 |
|
|
ha->ad_type = IPS_ADTYPE_SERVERAID6I;
|
| 2287 |
|
|
break;
|
| 2288 |
|
|
}
|
| 2289 |
|
|
break;
|
| 2290 |
|
|
}
|
| 2291 |
|
|
}
|
| 2292 |
|
|
|
| 2293 |
|
|
/****************************************************************************/
|
| 2294 |
|
|
/* */
|
| 2295 |
|
|
/* Routine Name: ips_get_bios_version */
|
| 2296 |
|
|
/* */
|
| 2297 |
|
|
/* Routine Description: */
|
| 2298 |
|
|
/* */
|
| 2299 |
|
|
/* Get the BIOS revision number */
|
| 2300 |
|
|
/* */
|
| 2301 |
|
|
/****************************************************************************/
|
| 2302 |
|
|
static void
|
| 2303 |
|
|
ips_get_bios_version(ips_ha_t * ha, int intr)
|
| 2304 |
|
|
{
|
| 2305 |
|
|
ips_scb_t *scb;
|
| 2306 |
|
|
int ret;
|
| 2307 |
|
|
uint8_t major;
|
| 2308 |
|
|
uint8_t minor;
|
| 2309 |
|
|
uint8_t subminor;
|
| 2310 |
|
|
uint8_t *buffer;
|
| 2311 |
|
|
char hexDigits[] =
|
| 2312 |
|
|
{ '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
|
| 2313 |
|
|
'D', 'E', 'F' };
|
| 2314 |
|
|
|
| 2315 |
|
|
METHOD_TRACE("ips_get_bios_version", 1);
|
| 2316 |
|
|
|
| 2317 |
|
|
major = 0;
|
| 2318 |
|
|
minor = 0;
|
| 2319 |
|
|
|
| 2320 |
|
|
strncpy(ha->bios_version, " ?", 8);
|
| 2321 |
|
|
|
| 2322 |
|
|
if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
|
| 2323 |
|
|
if (IPS_USE_MEMIO(ha)) {
|
| 2324 |
|
|
/* Memory Mapped I/O */
|
| 2325 |
|
|
|
| 2326 |
|
|
/* test 1st byte */
|
| 2327 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 2328 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2329 |
|
|
udelay(25); /* 25 us */
|
| 2330 |
|
|
|
| 2331 |
|
|
if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
|
| 2332 |
|
|
return;
|
| 2333 |
|
|
|
| 2334 |
|
|
writel(1, ha->mem_ptr + IPS_REG_FLAP);
|
| 2335 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2336 |
|
|
udelay(25); /* 25 us */
|
| 2337 |
|
|
|
| 2338 |
|
|
if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
|
| 2339 |
|
|
return;
|
| 2340 |
|
|
|
| 2341 |
|
|
/* Get Major version */
|
| 2342 |
|
|
writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
|
| 2343 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2344 |
|
|
udelay(25); /* 25 us */
|
| 2345 |
|
|
|
| 2346 |
|
|
major = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 2347 |
|
|
|
| 2348 |
|
|
/* Get Minor version */
|
| 2349 |
|
|
writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
|
| 2350 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2351 |
|
|
udelay(25); /* 25 us */
|
| 2352 |
|
|
minor = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 2353 |
|
|
|
| 2354 |
|
|
/* Get SubMinor version */
|
| 2355 |
|
|
writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
|
| 2356 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2357 |
|
|
udelay(25); /* 25 us */
|
| 2358 |
|
|
subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 2359 |
|
|
|
| 2360 |
|
|
} else {
|
| 2361 |
|
|
/* Programmed I/O */
|
| 2362 |
|
|
|
| 2363 |
|
|
/* test 1st byte */
|
| 2364 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 2365 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2366 |
|
|
udelay(25); /* 25 us */
|
| 2367 |
|
|
|
| 2368 |
|
|
if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
|
| 2369 |
|
|
return;
|
| 2370 |
|
|
|
| 2371 |
|
|
outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
|
| 2372 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2373 |
|
|
udelay(25); /* 25 us */
|
| 2374 |
|
|
|
| 2375 |
|
|
if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
|
| 2376 |
|
|
return;
|
| 2377 |
|
|
|
| 2378 |
|
|
/* Get Major version */
|
| 2379 |
|
|
outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
|
| 2380 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2381 |
|
|
udelay(25); /* 25 us */
|
| 2382 |
|
|
|
| 2383 |
|
|
major = inb(ha->io_addr + IPS_REG_FLDP);
|
| 2384 |
|
|
|
| 2385 |
|
|
/* Get Minor version */
|
| 2386 |
|
|
outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
|
| 2387 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2388 |
|
|
udelay(25); /* 25 us */
|
| 2389 |
|
|
|
| 2390 |
|
|
minor = inb(ha->io_addr + IPS_REG_FLDP);
|
| 2391 |
|
|
|
| 2392 |
|
|
/* Get SubMinor version */
|
| 2393 |
|
|
outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
|
| 2394 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 2395 |
|
|
udelay(25); /* 25 us */
|
| 2396 |
|
|
|
| 2397 |
|
|
subminor = inb(ha->io_addr + IPS_REG_FLDP);
|
| 2398 |
|
|
|
| 2399 |
|
|
}
|
| 2400 |
|
|
} else {
|
| 2401 |
|
|
/* Morpheus Family - Send Command to the card */
|
| 2402 |
|
|
|
| 2403 |
|
|
buffer = ha->ioctl_data;
|
| 2404 |
|
|
|
| 2405 |
|
|
memset(buffer, 0, 0x1000);
|
| 2406 |
|
|
|
| 2407 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 2408 |
|
|
|
| 2409 |
|
|
ips_init_scb(ha, scb);
|
| 2410 |
|
|
|
| 2411 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 2412 |
|
|
scb->cdb[0] = IPS_CMD_RW_BIOSFW;
|
| 2413 |
|
|
|
| 2414 |
|
|
scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
|
| 2415 |
|
|
scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
|
| 2416 |
|
|
scb->cmd.flashfw.type = 1;
|
| 2417 |
|
|
scb->cmd.flashfw.direction = 0;
|
| 2418 |
|
|
scb->cmd.flashfw.count = cpu_to_le32(0x800);
|
| 2419 |
|
|
scb->cmd.flashfw.total_packets = 1;
|
| 2420 |
|
|
scb->cmd.flashfw.packet_num = 0;
|
| 2421 |
|
|
scb->data_len = 0x1000;
|
| 2422 |
|
|
scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
|
| 2423 |
|
|
|
| 2424 |
|
|
/* issue the command */
|
| 2425 |
|
|
if (
|
| 2426 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 2427 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 2428 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
|
| 2429 |
|
|
/* Error occurred */
|
| 2430 |
|
|
|
| 2431 |
|
|
return;
|
| 2432 |
|
|
}
|
| 2433 |
|
|
|
| 2434 |
|
|
if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
|
| 2435 |
|
|
major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
|
| 2436 |
|
|
minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
|
| 2437 |
|
|
subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
|
| 2438 |
|
|
} else {
|
| 2439 |
|
|
return;
|
| 2440 |
|
|
}
|
| 2441 |
|
|
}
|
| 2442 |
|
|
|
| 2443 |
|
|
ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
|
| 2444 |
|
|
ha->bios_version[1] = '.';
|
| 2445 |
|
|
ha->bios_version[2] = hexDigits[major & 0x0F];
|
| 2446 |
|
|
ha->bios_version[3] = hexDigits[subminor];
|
| 2447 |
|
|
ha->bios_version[4] = '.';
|
| 2448 |
|
|
ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
|
| 2449 |
|
|
ha->bios_version[6] = hexDigits[minor & 0x0F];
|
| 2450 |
|
|
ha->bios_version[7] = 0;
|
| 2451 |
|
|
}
|
| 2452 |
|
|
|
| 2453 |
|
|
/****************************************************************************/
|
| 2454 |
|
|
/* */
|
| 2455 |
|
|
/* Routine Name: ips_hainit */
|
| 2456 |
|
|
/* */
|
| 2457 |
|
|
/* Routine Description: */
|
| 2458 |
|
|
/* */
|
| 2459 |
|
|
/* Initialize the controller */
|
| 2460 |
|
|
/* */
|
| 2461 |
|
|
/* NOTE: Assumes to be called from with a lock */
|
| 2462 |
|
|
/* */
|
| 2463 |
|
|
/****************************************************************************/
|
| 2464 |
|
|
static int
|
| 2465 |
|
|
ips_hainit(ips_ha_t * ha)
|
| 2466 |
|
|
{
|
| 2467 |
|
|
int i;
|
| 2468 |
|
|
struct timeval tv;
|
| 2469 |
|
|
|
| 2470 |
|
|
METHOD_TRACE("ips_hainit", 1);
|
| 2471 |
|
|
|
| 2472 |
|
|
if (!ha)
|
| 2473 |
|
|
return (0);
|
| 2474 |
|
|
|
| 2475 |
|
|
if (ha->func.statinit)
|
| 2476 |
|
|
(*ha->func.statinit) (ha);
|
| 2477 |
|
|
|
| 2478 |
|
|
if (ha->func.enableint)
|
| 2479 |
|
|
(*ha->func.enableint) (ha);
|
| 2480 |
|
|
|
| 2481 |
|
|
/* Send FFDC */
|
| 2482 |
|
|
ha->reset_count = 1;
|
| 2483 |
|
|
do_gettimeofday(&tv);
|
| 2484 |
|
|
ha->last_ffdc = tv.tv_sec;
|
| 2485 |
|
|
ips_ffdc_reset(ha, IPS_INTR_IORL);
|
| 2486 |
|
|
|
| 2487 |
|
|
if (!ips_read_config(ha, IPS_INTR_IORL)) {
|
| 2488 |
|
|
printk(KERN_WARNING
|
| 2489 |
|
|
"(%s%d) unable to read config from controller.\n",
|
| 2490 |
|
|
ips_name, ha->host_num);
|
| 2491 |
|
|
|
| 2492 |
|
|
return (0);
|
| 2493 |
|
|
}
|
| 2494 |
|
|
/* end if */
|
| 2495 |
|
|
if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
|
| 2496 |
|
|
printk(KERN_WARNING
|
| 2497 |
|
|
"(%s%d) unable to read controller status.\n", ips_name,
|
| 2498 |
|
|
ha->host_num);
|
| 2499 |
|
|
|
| 2500 |
|
|
return (0);
|
| 2501 |
|
|
}
|
| 2502 |
|
|
|
| 2503 |
|
|
/* Identify this controller */
|
| 2504 |
|
|
ips_identify_controller(ha);
|
| 2505 |
|
|
|
| 2506 |
|
|
if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
|
| 2507 |
|
|
printk(KERN_WARNING
|
| 2508 |
|
|
"(%s%d) unable to read subsystem parameters.\n",
|
| 2509 |
|
|
ips_name, ha->host_num);
|
| 2510 |
|
|
|
| 2511 |
|
|
return (0);
|
| 2512 |
|
|
}
|
| 2513 |
|
|
|
| 2514 |
|
|
/* write nvram user page 5 */
|
| 2515 |
|
|
if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
|
| 2516 |
|
|
printk(KERN_WARNING
|
| 2517 |
|
|
"(%s%d) unable to write driver info to controller.\n",
|
| 2518 |
|
|
ips_name, ha->host_num);
|
| 2519 |
|
|
|
| 2520 |
|
|
return (0);
|
| 2521 |
|
|
}
|
| 2522 |
|
|
|
| 2523 |
|
|
/* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
|
| 2524 |
|
|
if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
|
| 2525 |
|
|
ips_clear_adapter(ha, IPS_INTR_IORL);
|
| 2526 |
|
|
|
| 2527 |
|
|
/* set limits on SID, LUN, BUS */
|
| 2528 |
|
|
ha->ntargets = IPS_MAX_TARGETS + 1;
|
| 2529 |
|
|
ha->nlun = 1;
|
| 2530 |
|
|
ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
|
| 2531 |
|
|
|
| 2532 |
|
|
switch (ha->conf->logical_drive[0].ucStripeSize) {
|
| 2533 |
|
|
case 4:
|
| 2534 |
|
|
ha->max_xfer = 0x10000;
|
| 2535 |
|
|
break;
|
| 2536 |
|
|
|
| 2537 |
|
|
case 5:
|
| 2538 |
|
|
ha->max_xfer = 0x20000;
|
| 2539 |
|
|
break;
|
| 2540 |
|
|
|
| 2541 |
|
|
case 6:
|
| 2542 |
|
|
ha->max_xfer = 0x40000;
|
| 2543 |
|
|
break;
|
| 2544 |
|
|
|
| 2545 |
|
|
case 7:
|
| 2546 |
|
|
default:
|
| 2547 |
|
|
ha->max_xfer = 0x80000;
|
| 2548 |
|
|
break;
|
| 2549 |
|
|
}
|
| 2550 |
|
|
|
| 2551 |
|
|
/* setup max concurrent commands */
|
| 2552 |
|
|
if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
|
| 2553 |
|
|
/* Use the new method */
|
| 2554 |
|
|
ha->max_cmds = ha->enq->ucConcurrentCmdCount;
|
| 2555 |
|
|
} else {
|
| 2556 |
|
|
/* use the old method */
|
| 2557 |
|
|
switch (ha->conf->logical_drive[0].ucStripeSize) {
|
| 2558 |
|
|
case 4:
|
| 2559 |
|
|
ha->max_cmds = 32;
|
| 2560 |
|
|
break;
|
| 2561 |
|
|
|
| 2562 |
|
|
case 5:
|
| 2563 |
|
|
ha->max_cmds = 16;
|
| 2564 |
|
|
break;
|
| 2565 |
|
|
|
| 2566 |
|
|
case 6:
|
| 2567 |
|
|
ha->max_cmds = 8;
|
| 2568 |
|
|
break;
|
| 2569 |
|
|
|
| 2570 |
|
|
case 7:
|
| 2571 |
|
|
default:
|
| 2572 |
|
|
ha->max_cmds = 4;
|
| 2573 |
|
|
break;
|
| 2574 |
|
|
}
|
| 2575 |
|
|
}
|
| 2576 |
|
|
|
| 2577 |
|
|
/* Limit the Active Commands on a Lite Adapter */
|
| 2578 |
|
|
if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
|
| 2579 |
|
|
(ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
|
| 2580 |
|
|
(ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
|
| 2581 |
|
|
if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
|
| 2582 |
|
|
ha->max_cmds = MaxLiteCmds;
|
| 2583 |
|
|
}
|
| 2584 |
|
|
|
| 2585 |
|
|
/* set controller IDs */
|
| 2586 |
|
|
ha->ha_id[0] = IPS_ADAPTER_ID;
|
| 2587 |
|
|
for (i = 1; i < ha->nbus; i++) {
|
| 2588 |
|
|
ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
|
| 2589 |
|
|
ha->dcdb_active[i - 1] = 0;
|
| 2590 |
|
|
}
|
| 2591 |
|
|
|
| 2592 |
|
|
return (1);
|
| 2593 |
|
|
}
|
| 2594 |
|
|
|
| 2595 |
|
|
/****************************************************************************/
|
| 2596 |
|
|
/* */
|
| 2597 |
|
|
/* Routine Name: ips_next */
|
| 2598 |
|
|
/* */
|
| 2599 |
|
|
/* Routine Description: */
|
| 2600 |
|
|
/* */
|
| 2601 |
|
|
/* Take the next command off the queue and send it to the controller */
|
| 2602 |
|
|
/* */
|
| 2603 |
|
|
/****************************************************************************/
|
| 2604 |
|
|
static void
|
| 2605 |
|
|
ips_next(ips_ha_t * ha, int intr)
|
| 2606 |
|
|
{
|
| 2607 |
|
|
ips_scb_t *scb;
|
| 2608 |
|
|
Scsi_Cmnd *SC;
|
| 2609 |
|
|
Scsi_Cmnd *p;
|
| 2610 |
|
|
Scsi_Cmnd *q;
|
| 2611 |
|
|
ips_copp_wait_item_t *item;
|
| 2612 |
|
|
int ret;
|
| 2613 |
|
|
unsigned long cpu_flags = 0;
|
| 2614 |
|
|
struct Scsi_Host *host;
|
| 2615 |
|
|
METHOD_TRACE("ips_next", 1);
|
| 2616 |
|
|
|
| 2617 |
|
|
if (!ha)
|
| 2618 |
|
|
return;
|
| 2619 |
|
|
host = ips_sh[ha->host_num];
|
| 2620 |
|
|
/*
|
| 2621 |
|
|
* Block access to the queue function so
|
| 2622 |
|
|
* this command won't time out
|
| 2623 |
|
|
*/
|
| 2624 |
|
|
if (intr == IPS_INTR_ON)
|
| 2625 |
|
|
IPS_LOCK_SAVE(host->host_lock, cpu_flags);
|
| 2626 |
|
|
|
| 2627 |
|
|
if ((ha->subsys->param[3] & 0x300000)
|
| 2628 |
|
|
&& (ha->scb_activelist.count == 0)) {
|
| 2629 |
|
|
struct timeval tv;
|
| 2630 |
|
|
|
| 2631 |
|
|
do_gettimeofday(&tv);
|
| 2632 |
|
|
|
| 2633 |
|
|
if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
|
| 2634 |
|
|
ha->last_ffdc = tv.tv_sec;
|
| 2635 |
|
|
ips_ffdc_time(ha);
|
| 2636 |
|
|
}
|
| 2637 |
|
|
}
|
| 2638 |
|
|
|
| 2639 |
|
|
/*
|
| 2640 |
|
|
* Send passthru commands
|
| 2641 |
|
|
* These have priority over normal I/O
|
| 2642 |
|
|
* but shouldn't affect performance too much
|
| 2643 |
|
|
* since we limit the number that can be active
|
| 2644 |
|
|
* on the card at any one time
|
| 2645 |
|
|
*/
|
| 2646 |
|
|
while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
|
| 2647 |
|
|
(ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
|
| 2648 |
|
|
|
| 2649 |
|
|
item = ips_removeq_copp_head(&ha->copp_waitlist);
|
| 2650 |
|
|
ha->num_ioctl++;
|
| 2651 |
|
|
if (intr == IPS_INTR_ON)
|
| 2652 |
|
|
IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
|
| 2653 |
|
|
scb->scsi_cmd = item->scsi_cmd;
|
| 2654 |
|
|
kfree(item);
|
| 2655 |
|
|
|
| 2656 |
|
|
ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
|
| 2657 |
|
|
|
| 2658 |
|
|
if (intr == IPS_INTR_ON)
|
| 2659 |
|
|
IPS_LOCK_SAVE(host->host_lock, cpu_flags);
|
| 2660 |
|
|
switch (ret) {
|
| 2661 |
|
|
case IPS_FAILURE:
|
| 2662 |
|
|
if (scb->scsi_cmd) {
|
| 2663 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 2664 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 2665 |
|
|
}
|
| 2666 |
|
|
|
| 2667 |
|
|
ips_freescb(ha, scb);
|
| 2668 |
|
|
break;
|
| 2669 |
|
|
case IPS_SUCCESS_IMM:
|
| 2670 |
|
|
if (scb->scsi_cmd) {
|
| 2671 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 2672 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 2673 |
|
|
}
|
| 2674 |
|
|
|
| 2675 |
|
|
ips_freescb(ha, scb);
|
| 2676 |
|
|
break;
|
| 2677 |
|
|
default:
|
| 2678 |
|
|
break;
|
| 2679 |
|
|
} /* end case */
|
| 2680 |
|
|
|
| 2681 |
|
|
if (ret != IPS_SUCCESS) {
|
| 2682 |
|
|
ha->num_ioctl--;
|
| 2683 |
|
|
continue;
|
| 2684 |
|
|
}
|
| 2685 |
|
|
|
| 2686 |
|
|
ret = ips_send_cmd(ha, scb);
|
| 2687 |
|
|
|
| 2688 |
|
|
if (ret == IPS_SUCCESS)
|
| 2689 |
|
|
ips_putq_scb_head(&ha->scb_activelist, scb);
|
| 2690 |
|
|
else
|
| 2691 |
|
|
ha->num_ioctl--;
|
| 2692 |
|
|
|
| 2693 |
|
|
switch (ret) {
|
| 2694 |
|
|
case IPS_FAILURE:
|
| 2695 |
|
|
if (scb->scsi_cmd) {
|
| 2696 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 2697 |
|
|
}
|
| 2698 |
|
|
|
| 2699 |
|
|
ips_freescb(ha, scb);
|
| 2700 |
|
|
break;
|
| 2701 |
|
|
case IPS_SUCCESS_IMM:
|
| 2702 |
|
|
ips_freescb(ha, scb);
|
| 2703 |
|
|
break;
|
| 2704 |
|
|
default:
|
| 2705 |
|
|
break;
|
| 2706 |
|
|
} /* end case */
|
| 2707 |
|
|
|
| 2708 |
|
|
}
|
| 2709 |
|
|
|
| 2710 |
|
|
/*
|
| 2711 |
|
|
* Send "Normal" I/O commands
|
| 2712 |
|
|
*/
|
| 2713 |
|
|
|
| 2714 |
|
|
p = ha->scb_waitlist.head;
|
| 2715 |
|
|
while ((p) && (scb = ips_getscb(ha))) {
|
| 2716 |
|
|
if ((p->channel > 0)
|
| 2717 |
|
|
&& (ha->dcdb_active[p->channel - 1] & (1 << p->target))) {
|
| 2718 |
|
|
ips_freescb(ha, scb);
|
| 2719 |
|
|
p = (Scsi_Cmnd *) p->host_scribble;
|
| 2720 |
|
|
continue;
|
| 2721 |
|
|
}
|
| 2722 |
|
|
|
| 2723 |
|
|
q = p;
|
| 2724 |
|
|
SC = ips_removeq_wait(&ha->scb_waitlist, q);
|
| 2725 |
|
|
|
| 2726 |
|
|
if (intr == IPS_INTR_ON)
|
| 2727 |
|
|
IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
|
| 2728 |
|
|
|
| 2729 |
|
|
SC->result = DID_OK;
|
| 2730 |
|
|
SC->host_scribble = NULL;
|
| 2731 |
|
|
|
| 2732 |
|
|
memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
|
| 2733 |
|
|
|
| 2734 |
|
|
scb->target_id = SC->target;
|
| 2735 |
|
|
scb->lun = SC->lun;
|
| 2736 |
|
|
scb->bus = SC->channel;
|
| 2737 |
|
|
scb->scsi_cmd = SC;
|
| 2738 |
|
|
scb->breakup = 0;
|
| 2739 |
|
|
scb->data_len = 0;
|
| 2740 |
|
|
scb->callback = ipsintr_done;
|
| 2741 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 2742 |
|
|
memset(&scb->cmd, 0, 16);
|
| 2743 |
|
|
|
| 2744 |
|
|
/* copy in the CDB */
|
| 2745 |
|
|
memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
|
| 2746 |
|
|
|
| 2747 |
|
|
/* Now handle the data buffer */
|
| 2748 |
|
|
if (SC->use_sg) {
|
| 2749 |
|
|
struct scatterlist *sg;
|
| 2750 |
|
|
int i;
|
| 2751 |
|
|
|
| 2752 |
|
|
sg = SC->request_buffer;
|
| 2753 |
|
|
scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
|
| 2754 |
|
|
scsi_to_pci_dma_dir(SC->
|
| 2755 |
|
|
sc_data_direction));
|
| 2756 |
|
|
scb->flags |= IPS_SCB_MAP_SG;
|
| 2757 |
|
|
for (i = 0; i < scb->sg_count; i++) {
|
| 2758 |
|
|
if (ips_fill_scb_sg_single
|
| 2759 |
|
|
(ha, sg_dma_address(&sg[i]), scb, i,
|
| 2760 |
|
|
sg_dma_len(&sg[i])) < 0)
|
| 2761 |
|
|
break;
|
| 2762 |
|
|
}
|
| 2763 |
|
|
scb->dcdb.transfer_length = scb->data_len;
|
| 2764 |
|
|
} else {
|
| 2765 |
|
|
if (SC->request_bufflen) {
|
| 2766 |
|
|
scb->data_busaddr =
|
| 2767 |
|
|
pci_map_single(ha->pcidev,
|
| 2768 |
|
|
SC->request_buffer,
|
| 2769 |
|
|
SC->request_bufflen,
|
| 2770 |
|
|
scsi_to_pci_dma_dir(SC->
|
| 2771 |
|
|
sc_data_direction));
|
| 2772 |
|
|
scb->flags |= IPS_SCB_MAP_SINGLE;
|
| 2773 |
|
|
ips_fill_scb_sg_single(ha, scb->data_busaddr,
|
| 2774 |
|
|
scb, 0,
|
| 2775 |
|
|
SC->request_bufflen);
|
| 2776 |
|
|
scb->dcdb.transfer_length = scb->data_len;
|
| 2777 |
|
|
} else {
|
| 2778 |
|
|
scb->data_busaddr = 0L;
|
| 2779 |
|
|
scb->sg_len = 0;
|
| 2780 |
|
|
scb->data_len = 0;
|
| 2781 |
|
|
scb->dcdb.transfer_length = 0;
|
| 2782 |
|
|
}
|
| 2783 |
|
|
|
| 2784 |
|
|
}
|
| 2785 |
|
|
|
| 2786 |
|
|
scb->dcdb.cmd_attribute =
|
| 2787 |
|
|
ips_command_direction[scb->scsi_cmd->cmnd[0]];
|
| 2788 |
|
|
|
| 2789 |
|
|
/* Allow a WRITE BUFFER Command to Have no Data */
|
| 2790 |
|
|
/* This is Used by Tape Flash Utilites */
|
| 2791 |
|
|
if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
|
| 2792 |
|
|
scb->dcdb.cmd_attribute = 0;
|
| 2793 |
|
|
|
| 2794 |
|
|
if (!(scb->dcdb.cmd_attribute & 0x3))
|
| 2795 |
|
|
scb->dcdb.transfer_length = 0;
|
| 2796 |
|
|
|
| 2797 |
|
|
if (scb->data_len >= IPS_MAX_XFER) {
|
| 2798 |
|
|
scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
|
| 2799 |
|
|
scb->dcdb.transfer_length = 0;
|
| 2800 |
|
|
}
|
| 2801 |
|
|
if (intr == IPS_INTR_ON)
|
| 2802 |
|
|
IPS_LOCK_SAVE(host->host_lock, cpu_flags);
|
| 2803 |
|
|
|
| 2804 |
|
|
ret = ips_send_cmd(ha, scb);
|
| 2805 |
|
|
|
| 2806 |
|
|
switch (ret) {
|
| 2807 |
|
|
case IPS_SUCCESS:
|
| 2808 |
|
|
ips_putq_scb_head(&ha->scb_activelist, scb);
|
| 2809 |
|
|
break;
|
| 2810 |
|
|
case IPS_FAILURE:
|
| 2811 |
|
|
if (scb->scsi_cmd) {
|
| 2812 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 2813 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 2814 |
|
|
}
|
| 2815 |
|
|
|
| 2816 |
|
|
if (scb->bus)
|
| 2817 |
|
|
ha->dcdb_active[scb->bus - 1] &=
|
| 2818 |
|
|
~(1 << scb->target_id);
|
| 2819 |
|
|
|
| 2820 |
|
|
ips_freescb(ha, scb);
|
| 2821 |
|
|
break;
|
| 2822 |
|
|
case IPS_SUCCESS_IMM:
|
| 2823 |
|
|
if (scb->scsi_cmd)
|
| 2824 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 2825 |
|
|
|
| 2826 |
|
|
if (scb->bus)
|
| 2827 |
|
|
ha->dcdb_active[scb->bus - 1] &=
|
| 2828 |
|
|
~(1 << scb->target_id);
|
| 2829 |
|
|
|
| 2830 |
|
|
ips_freescb(ha, scb);
|
| 2831 |
|
|
break;
|
| 2832 |
|
|
default:
|
| 2833 |
|
|
break;
|
| 2834 |
|
|
} /* end case */
|
| 2835 |
|
|
|
| 2836 |
|
|
p = (Scsi_Cmnd *) p->host_scribble;
|
| 2837 |
|
|
|
| 2838 |
|
|
} /* end while */
|
| 2839 |
|
|
|
| 2840 |
|
|
if (intr == IPS_INTR_ON)
|
| 2841 |
|
|
IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
|
| 2842 |
|
|
}
|
| 2843 |
|
|
|
| 2844 |
|
|
/****************************************************************************/
|
| 2845 |
|
|
/* */
|
| 2846 |
|
|
/* Routine Name: ips_putq_scb_head */
|
| 2847 |
|
|
/* */
|
| 2848 |
|
|
/* Routine Description: */
|
| 2849 |
|
|
/* */
|
| 2850 |
|
|
/* Add an item to the head of the queue */
|
| 2851 |
|
|
/* */
|
| 2852 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 2853 |
|
|
/* */
|
| 2854 |
|
|
/****************************************************************************/
|
| 2855 |
|
|
static inline void
|
| 2856 |
|
|
ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
|
| 2857 |
|
|
{
|
| 2858 |
|
|
METHOD_TRACE("ips_putq_scb_head", 1);
|
| 2859 |
|
|
|
| 2860 |
|
|
if (!item)
|
| 2861 |
|
|
return;
|
| 2862 |
|
|
|
| 2863 |
|
|
item->q_next = queue->head;
|
| 2864 |
|
|
queue->head = item;
|
| 2865 |
|
|
|
| 2866 |
|
|
if (!queue->tail)
|
| 2867 |
|
|
queue->tail = item;
|
| 2868 |
|
|
|
| 2869 |
|
|
queue->count++;
|
| 2870 |
|
|
}
|
| 2871 |
|
|
|
| 2872 |
|
|
/****************************************************************************/
|
| 2873 |
|
|
/* */
|
| 2874 |
|
|
/* Routine Name: ips_putq_scb_tail */
|
| 2875 |
|
|
/* */
|
| 2876 |
|
|
/* Routine Description: */
|
| 2877 |
|
|
/* */
|
| 2878 |
|
|
/* Add an item to the tail of the queue */
|
| 2879 |
|
|
/* */
|
| 2880 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 2881 |
|
|
/* */
|
| 2882 |
|
|
/****************************************************************************/
|
| 2883 |
|
|
static inline void
|
| 2884 |
|
|
ips_putq_scb_tail(ips_scb_queue_t * queue, ips_scb_t * item)
|
| 2885 |
|
|
{
|
| 2886 |
|
|
METHOD_TRACE("ips_putq_scb_tail", 1);
|
| 2887 |
|
|
|
| 2888 |
|
|
if (!item)
|
| 2889 |
|
|
return;
|
| 2890 |
|
|
|
| 2891 |
|
|
item->q_next = NULL;
|
| 2892 |
|
|
|
| 2893 |
|
|
if (queue->tail)
|
| 2894 |
|
|
queue->tail->q_next = item;
|
| 2895 |
|
|
|
| 2896 |
|
|
queue->tail = item;
|
| 2897 |
|
|
|
| 2898 |
|
|
if (!queue->head)
|
| 2899 |
|
|
queue->head = item;
|
| 2900 |
|
|
|
| 2901 |
|
|
queue->count++;
|
| 2902 |
|
|
}
|
| 2903 |
|
|
|
| 2904 |
|
|
/****************************************************************************/
|
| 2905 |
|
|
/* */
|
| 2906 |
|
|
/* Routine Name: ips_removeq_scb_head */
|
| 2907 |
|
|
/* */
|
| 2908 |
|
|
/* Routine Description: */
|
| 2909 |
|
|
/* */
|
| 2910 |
|
|
/* Remove the head of the queue */
|
| 2911 |
|
|
/* */
|
| 2912 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 2913 |
|
|
/* */
|
| 2914 |
|
|
/****************************************************************************/
|
| 2915 |
|
|
static inline ips_scb_t *
|
| 2916 |
|
|
ips_removeq_scb_head(ips_scb_queue_t * queue)
|
| 2917 |
|
|
{
|
| 2918 |
|
|
ips_scb_t *item;
|
| 2919 |
|
|
|
| 2920 |
|
|
METHOD_TRACE("ips_removeq_scb_head", 1);
|
| 2921 |
|
|
|
| 2922 |
|
|
item = queue->head;
|
| 2923 |
|
|
|
| 2924 |
|
|
if (!item) {
|
| 2925 |
|
|
return (NULL);
|
| 2926 |
|
|
}
|
| 2927 |
|
|
|
| 2928 |
|
|
queue->head = item->q_next;
|
| 2929 |
|
|
item->q_next = NULL;
|
| 2930 |
|
|
|
| 2931 |
|
|
if (queue->tail == item)
|
| 2932 |
|
|
queue->tail = NULL;
|
| 2933 |
|
|
|
| 2934 |
|
|
queue->count--;
|
| 2935 |
|
|
|
| 2936 |
|
|
return (item);
|
| 2937 |
|
|
}
|
| 2938 |
|
|
|
| 2939 |
|
|
/****************************************************************************/
|
| 2940 |
|
|
/* */
|
| 2941 |
|
|
/* Routine Name: ips_removeq_scb */
|
| 2942 |
|
|
/* */
|
| 2943 |
|
|
/* Routine Description: */
|
| 2944 |
|
|
/* */
|
| 2945 |
|
|
/* Remove an item from a queue */
|
| 2946 |
|
|
/* */
|
| 2947 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 2948 |
|
|
/* */
|
| 2949 |
|
|
/****************************************************************************/
|
| 2950 |
|
|
static inline ips_scb_t *
|
| 2951 |
|
|
ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
|
| 2952 |
|
|
{
|
| 2953 |
|
|
ips_scb_t *p;
|
| 2954 |
|
|
|
| 2955 |
|
|
METHOD_TRACE("ips_removeq_scb", 1);
|
| 2956 |
|
|
|
| 2957 |
|
|
if (!item)
|
| 2958 |
|
|
return (NULL);
|
| 2959 |
|
|
|
| 2960 |
|
|
if (item == queue->head) {
|
| 2961 |
|
|
return (ips_removeq_scb_head(queue));
|
| 2962 |
|
|
}
|
| 2963 |
|
|
|
| 2964 |
|
|
p = queue->head;
|
| 2965 |
|
|
|
| 2966 |
|
|
while ((p) && (item != p->q_next))
|
| 2967 |
|
|
p = p->q_next;
|
| 2968 |
|
|
|
| 2969 |
|
|
if (p) {
|
| 2970 |
|
|
/* found a match */
|
| 2971 |
|
|
p->q_next = item->q_next;
|
| 2972 |
|
|
|
| 2973 |
|
|
if (!item->q_next)
|
| 2974 |
|
|
queue->tail = p;
|
| 2975 |
|
|
|
| 2976 |
|
|
item->q_next = NULL;
|
| 2977 |
|
|
queue->count--;
|
| 2978 |
|
|
|
| 2979 |
|
|
return (item);
|
| 2980 |
|
|
}
|
| 2981 |
|
|
|
| 2982 |
|
|
return (NULL);
|
| 2983 |
|
|
}
|
| 2984 |
|
|
|
| 2985 |
|
|
/****************************************************************************/
|
| 2986 |
|
|
/* */
|
| 2987 |
|
|
/* Routine Name: ips_putq_wait_head */
|
| 2988 |
|
|
/* */
|
| 2989 |
|
|
/* Routine Description: */
|
| 2990 |
|
|
/* */
|
| 2991 |
|
|
/* Add an item to the head of the queue */
|
| 2992 |
|
|
/* */
|
| 2993 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 2994 |
|
|
/* */
|
| 2995 |
|
|
/****************************************************************************/
|
| 2996 |
|
|
static inline void
|
| 2997 |
|
|
ips_putq_wait_head(ips_wait_queue_t * queue, Scsi_Cmnd * item)
|
| 2998 |
|
|
{
|
| 2999 |
|
|
METHOD_TRACE("ips_putq_wait_head", 1);
|
| 3000 |
|
|
|
| 3001 |
|
|
if (!item)
|
| 3002 |
|
|
return;
|
| 3003 |
|
|
|
| 3004 |
|
|
item->host_scribble = (char *) queue->head;
|
| 3005 |
|
|
queue->head = item;
|
| 3006 |
|
|
|
| 3007 |
|
|
if (!queue->tail)
|
| 3008 |
|
|
queue->tail = item;
|
| 3009 |
|
|
|
| 3010 |
|
|
queue->count++;
|
| 3011 |
|
|
}
|
| 3012 |
|
|
|
| 3013 |
|
|
/****************************************************************************/
|
| 3014 |
|
|
/* */
|
| 3015 |
|
|
/* Routine Name: ips_putq_wait_tail */
|
| 3016 |
|
|
/* */
|
| 3017 |
|
|
/* Routine Description: */
|
| 3018 |
|
|
/* */
|
| 3019 |
|
|
/* Add an item to the tail of the queue */
|
| 3020 |
|
|
/* */
|
| 3021 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3022 |
|
|
/* */
|
| 3023 |
|
|
/****************************************************************************/
|
| 3024 |
|
|
static inline void
|
| 3025 |
|
|
ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
|
| 3026 |
|
|
{
|
| 3027 |
|
|
METHOD_TRACE("ips_putq_wait_tail", 1);
|
| 3028 |
|
|
|
| 3029 |
|
|
if (!item)
|
| 3030 |
|
|
return;
|
| 3031 |
|
|
|
| 3032 |
|
|
item->host_scribble = NULL;
|
| 3033 |
|
|
|
| 3034 |
|
|
if (queue->tail)
|
| 3035 |
|
|
queue->tail->host_scribble = (char *) item;
|
| 3036 |
|
|
|
| 3037 |
|
|
queue->tail = item;
|
| 3038 |
|
|
|
| 3039 |
|
|
if (!queue->head)
|
| 3040 |
|
|
queue->head = item;
|
| 3041 |
|
|
|
| 3042 |
|
|
queue->count++;
|
| 3043 |
|
|
}
|
| 3044 |
|
|
|
| 3045 |
|
|
/****************************************************************************/
|
| 3046 |
|
|
/* */
|
| 3047 |
|
|
/* Routine Name: ips_removeq_wait_head */
|
| 3048 |
|
|
/* */
|
| 3049 |
|
|
/* Routine Description: */
|
| 3050 |
|
|
/* */
|
| 3051 |
|
|
/* Remove the head of the queue */
|
| 3052 |
|
|
/* */
|
| 3053 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3054 |
|
|
/* */
|
| 3055 |
|
|
/****************************************************************************/
|
| 3056 |
|
|
static inline Scsi_Cmnd *
|
| 3057 |
|
|
ips_removeq_wait_head(ips_wait_queue_t * queue)
|
| 3058 |
|
|
{
|
| 3059 |
|
|
Scsi_Cmnd *item;
|
| 3060 |
|
|
|
| 3061 |
|
|
METHOD_TRACE("ips_removeq_wait_head", 1);
|
| 3062 |
|
|
|
| 3063 |
|
|
item = queue->head;
|
| 3064 |
|
|
|
| 3065 |
|
|
if (!item) {
|
| 3066 |
|
|
return (NULL);
|
| 3067 |
|
|
}
|
| 3068 |
|
|
|
| 3069 |
|
|
queue->head = (Scsi_Cmnd *) item->host_scribble;
|
| 3070 |
|
|
item->host_scribble = NULL;
|
| 3071 |
|
|
|
| 3072 |
|
|
if (queue->tail == item)
|
| 3073 |
|
|
queue->tail = NULL;
|
| 3074 |
|
|
|
| 3075 |
|
|
queue->count--;
|
| 3076 |
|
|
|
| 3077 |
|
|
return (item);
|
| 3078 |
|
|
}
|
| 3079 |
|
|
|
| 3080 |
|
|
/****************************************************************************/
|
| 3081 |
|
|
/* */
|
| 3082 |
|
|
/* Routine Name: ips_removeq_wait */
|
| 3083 |
|
|
/* */
|
| 3084 |
|
|
/* Routine Description: */
|
| 3085 |
|
|
/* */
|
| 3086 |
|
|
/* Remove an item from a queue */
|
| 3087 |
|
|
/* */
|
| 3088 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3089 |
|
|
/* */
|
| 3090 |
|
|
/****************************************************************************/
|
| 3091 |
|
|
static inline Scsi_Cmnd *
|
| 3092 |
|
|
ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
|
| 3093 |
|
|
{
|
| 3094 |
|
|
Scsi_Cmnd *p;
|
| 3095 |
|
|
|
| 3096 |
|
|
METHOD_TRACE("ips_removeq_wait", 1);
|
| 3097 |
|
|
|
| 3098 |
|
|
if (!item)
|
| 3099 |
|
|
return (NULL);
|
| 3100 |
|
|
|
| 3101 |
|
|
if (item == queue->head) {
|
| 3102 |
|
|
return (ips_removeq_wait_head(queue));
|
| 3103 |
|
|
}
|
| 3104 |
|
|
|
| 3105 |
|
|
p = queue->head;
|
| 3106 |
|
|
|
| 3107 |
|
|
while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
|
| 3108 |
|
|
p = (Scsi_Cmnd *) p->host_scribble;
|
| 3109 |
|
|
|
| 3110 |
|
|
if (p) {
|
| 3111 |
|
|
/* found a match */
|
| 3112 |
|
|
p->host_scribble = item->host_scribble;
|
| 3113 |
|
|
|
| 3114 |
|
|
if (!item->host_scribble)
|
| 3115 |
|
|
queue->tail = p;
|
| 3116 |
|
|
|
| 3117 |
|
|
item->host_scribble = NULL;
|
| 3118 |
|
|
queue->count--;
|
| 3119 |
|
|
|
| 3120 |
|
|
return (item);
|
| 3121 |
|
|
}
|
| 3122 |
|
|
|
| 3123 |
|
|
return (NULL);
|
| 3124 |
|
|
}
|
| 3125 |
|
|
|
| 3126 |
|
|
/****************************************************************************/
|
| 3127 |
|
|
/* */
|
| 3128 |
|
|
/* Routine Name: ips_putq_copp_head */
|
| 3129 |
|
|
/* */
|
| 3130 |
|
|
/* Routine Description: */
|
| 3131 |
|
|
/* */
|
| 3132 |
|
|
/* Add an item to the head of the queue */
|
| 3133 |
|
|
/* */
|
| 3134 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3135 |
|
|
/* */
|
| 3136 |
|
|
/****************************************************************************/
|
| 3137 |
|
|
static inline void
|
| 3138 |
|
|
ips_putq_copp_head(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
|
| 3139 |
|
|
{
|
| 3140 |
|
|
METHOD_TRACE("ips_putq_copp_head", 1);
|
| 3141 |
|
|
|
| 3142 |
|
|
if (!item)
|
| 3143 |
|
|
return;
|
| 3144 |
|
|
|
| 3145 |
|
|
item->next = queue->head;
|
| 3146 |
|
|
queue->head = item;
|
| 3147 |
|
|
|
| 3148 |
|
|
if (!queue->tail)
|
| 3149 |
|
|
queue->tail = item;
|
| 3150 |
|
|
|
| 3151 |
|
|
queue->count++;
|
| 3152 |
|
|
}
|
| 3153 |
|
|
|
| 3154 |
|
|
/****************************************************************************/
|
| 3155 |
|
|
/* */
|
| 3156 |
|
|
/* Routine Name: ips_putq_copp_tail */
|
| 3157 |
|
|
/* */
|
| 3158 |
|
|
/* Routine Description: */
|
| 3159 |
|
|
/* */
|
| 3160 |
|
|
/* Add an item to the tail of the queue */
|
| 3161 |
|
|
/* */
|
| 3162 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3163 |
|
|
/* */
|
| 3164 |
|
|
/****************************************************************************/
|
| 3165 |
|
|
static inline void
|
| 3166 |
|
|
ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
|
| 3167 |
|
|
{
|
| 3168 |
|
|
METHOD_TRACE("ips_putq_copp_tail", 1);
|
| 3169 |
|
|
|
| 3170 |
|
|
if (!item)
|
| 3171 |
|
|
return;
|
| 3172 |
|
|
|
| 3173 |
|
|
item->next = NULL;
|
| 3174 |
|
|
|
| 3175 |
|
|
if (queue->tail)
|
| 3176 |
|
|
queue->tail->next = item;
|
| 3177 |
|
|
|
| 3178 |
|
|
queue->tail = item;
|
| 3179 |
|
|
|
| 3180 |
|
|
if (!queue->head)
|
| 3181 |
|
|
queue->head = item;
|
| 3182 |
|
|
|
| 3183 |
|
|
queue->count++;
|
| 3184 |
|
|
}
|
| 3185 |
|
|
|
| 3186 |
|
|
/****************************************************************************/
|
| 3187 |
|
|
/* */
|
| 3188 |
|
|
/* Routine Name: ips_removeq_copp_head */
|
| 3189 |
|
|
/* */
|
| 3190 |
|
|
/* Routine Description: */
|
| 3191 |
|
|
/* */
|
| 3192 |
|
|
/* Remove the head of the queue */
|
| 3193 |
|
|
/* */
|
| 3194 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3195 |
|
|
/* */
|
| 3196 |
|
|
/****************************************************************************/
|
| 3197 |
|
|
static inline ips_copp_wait_item_t *
|
| 3198 |
|
|
ips_removeq_copp_head(ips_copp_queue_t * queue)
|
| 3199 |
|
|
{
|
| 3200 |
|
|
ips_copp_wait_item_t *item;
|
| 3201 |
|
|
|
| 3202 |
|
|
METHOD_TRACE("ips_removeq_copp_head", 1);
|
| 3203 |
|
|
|
| 3204 |
|
|
item = queue->head;
|
| 3205 |
|
|
|
| 3206 |
|
|
if (!item) {
|
| 3207 |
|
|
return (NULL);
|
| 3208 |
|
|
}
|
| 3209 |
|
|
|
| 3210 |
|
|
queue->head = item->next;
|
| 3211 |
|
|
item->next = NULL;
|
| 3212 |
|
|
|
| 3213 |
|
|
if (queue->tail == item)
|
| 3214 |
|
|
queue->tail = NULL;
|
| 3215 |
|
|
|
| 3216 |
|
|
queue->count--;
|
| 3217 |
|
|
|
| 3218 |
|
|
return (item);
|
| 3219 |
|
|
}
|
| 3220 |
|
|
|
| 3221 |
|
|
/****************************************************************************/
|
| 3222 |
|
|
/* */
|
| 3223 |
|
|
/* Routine Name: ips_removeq_copp */
|
| 3224 |
|
|
/* */
|
| 3225 |
|
|
/* Routine Description: */
|
| 3226 |
|
|
/* */
|
| 3227 |
|
|
/* Remove an item from a queue */
|
| 3228 |
|
|
/* */
|
| 3229 |
|
|
/* ASSUMED to be called from within the HA lock */
|
| 3230 |
|
|
/* */
|
| 3231 |
|
|
/****************************************************************************/
|
| 3232 |
|
|
static inline ips_copp_wait_item_t *
|
| 3233 |
|
|
ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
|
| 3234 |
|
|
{
|
| 3235 |
|
|
ips_copp_wait_item_t *p;
|
| 3236 |
|
|
|
| 3237 |
|
|
METHOD_TRACE("ips_removeq_copp", 1);
|
| 3238 |
|
|
|
| 3239 |
|
|
if (!item)
|
| 3240 |
|
|
return (NULL);
|
| 3241 |
|
|
|
| 3242 |
|
|
if (item == queue->head) {
|
| 3243 |
|
|
return (ips_removeq_copp_head(queue));
|
| 3244 |
|
|
}
|
| 3245 |
|
|
|
| 3246 |
|
|
p = queue->head;
|
| 3247 |
|
|
|
| 3248 |
|
|
while ((p) && (item != p->next))
|
| 3249 |
|
|
p = p->next;
|
| 3250 |
|
|
|
| 3251 |
|
|
if (p) {
|
| 3252 |
|
|
/* found a match */
|
| 3253 |
|
|
p->next = item->next;
|
| 3254 |
|
|
|
| 3255 |
|
|
if (!item->next)
|
| 3256 |
|
|
queue->tail = p;
|
| 3257 |
|
|
|
| 3258 |
|
|
item->next = NULL;
|
| 3259 |
|
|
queue->count--;
|
| 3260 |
|
|
|
| 3261 |
|
|
return (item);
|
| 3262 |
|
|
}
|
| 3263 |
|
|
|
| 3264 |
|
|
return (NULL);
|
| 3265 |
|
|
}
|
| 3266 |
|
|
|
| 3267 |
|
|
/****************************************************************************/
|
| 3268 |
|
|
/* */
|
| 3269 |
|
|
/* Routine Name: ipsintr_blocking */
|
| 3270 |
|
|
/* */
|
| 3271 |
|
|
/* Routine Description: */
|
| 3272 |
|
|
/* */
|
| 3273 |
|
|
/* Finalize an interrupt for internal commands */
|
| 3274 |
|
|
/* */
|
| 3275 |
|
|
/****************************************************************************/
|
| 3276 |
|
|
static void
|
| 3277 |
|
|
ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
|
| 3278 |
|
|
{
|
| 3279 |
|
|
METHOD_TRACE("ipsintr_blocking", 2);
|
| 3280 |
|
|
|
| 3281 |
|
|
ips_freescb(ha, scb);
|
| 3282 |
|
|
if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
|
| 3283 |
|
|
ha->waitflag = FALSE;
|
| 3284 |
|
|
|
| 3285 |
|
|
return;
|
| 3286 |
|
|
}
|
| 3287 |
|
|
}
|
| 3288 |
|
|
|
| 3289 |
|
|
/****************************************************************************/
|
| 3290 |
|
|
/* */
|
| 3291 |
|
|
/* Routine Name: ipsintr_done */
|
| 3292 |
|
|
/* */
|
| 3293 |
|
|
/* Routine Description: */
|
| 3294 |
|
|
/* */
|
| 3295 |
|
|
/* Finalize an interrupt for non-internal commands */
|
| 3296 |
|
|
/* */
|
| 3297 |
|
|
/****************************************************************************/
|
| 3298 |
|
|
static void
|
| 3299 |
|
|
ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
|
| 3300 |
|
|
{
|
| 3301 |
|
|
METHOD_TRACE("ipsintr_done", 2);
|
| 3302 |
|
|
|
| 3303 |
|
|
if (!scb) {
|
| 3304 |
|
|
printk(KERN_WARNING "(%s%d) Spurious interrupt; scb NULL.\n",
|
| 3305 |
|
|
ips_name, ha->host_num);
|
| 3306 |
|
|
|
| 3307 |
|
|
return;
|
| 3308 |
|
|
}
|
| 3309 |
|
|
|
| 3310 |
|
|
if (scb->scsi_cmd == NULL) {
|
| 3311 |
|
|
/* unexpected interrupt */
|
| 3312 |
|
|
printk(KERN_WARNING
|
| 3313 |
|
|
"(%s%d) Spurious interrupt; scsi_cmd not set.\n",
|
| 3314 |
|
|
ips_name, ha->host_num);
|
| 3315 |
|
|
|
| 3316 |
|
|
return;
|
| 3317 |
|
|
}
|
| 3318 |
|
|
|
| 3319 |
|
|
ips_done(ha, scb);
|
| 3320 |
|
|
}
|
| 3321 |
|
|
|
| 3322 |
|
|
/****************************************************************************/
|
| 3323 |
|
|
/* */
|
| 3324 |
|
|
/* Routine Name: ips_done */
|
| 3325 |
|
|
/* */
|
| 3326 |
|
|
/* Routine Description: */
|
| 3327 |
|
|
/* */
|
| 3328 |
|
|
/* Do housekeeping on completed commands */
|
| 3329 |
|
|
/* ASSUMED to be called form within the request lock */
|
| 3330 |
|
|
/****************************************************************************/
|
| 3331 |
|
|
static void
|
| 3332 |
|
|
ips_done(ips_ha_t * ha, ips_scb_t * scb)
|
| 3333 |
|
|
{
|
| 3334 |
|
|
int ret;
|
| 3335 |
|
|
|
| 3336 |
|
|
METHOD_TRACE("ips_done", 1);
|
| 3337 |
|
|
|
| 3338 |
|
|
if (!scb)
|
| 3339 |
|
|
return;
|
| 3340 |
|
|
|
| 3341 |
|
|
if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
|
| 3342 |
|
|
ips_cleanup_passthru(ha, scb);
|
| 3343 |
|
|
ha->num_ioctl--;
|
| 3344 |
|
|
} else {
|
| 3345 |
|
|
/*
|
| 3346 |
|
|
* Check to see if this command had too much
|
| 3347 |
|
|
* data and had to be broke up. If so, queue
|
| 3348 |
|
|
* the rest of the data and continue.
|
| 3349 |
|
|
*/
|
| 3350 |
|
|
if ((scb->breakup) || (scb->sg_break)) {
|
| 3351 |
|
|
/* we had a data breakup */
|
| 3352 |
|
|
scb->data_len = 0;
|
| 3353 |
|
|
|
| 3354 |
|
|
if (scb->sg_count) {
|
| 3355 |
|
|
/* S/G request */
|
| 3356 |
|
|
struct scatterlist *sg;
|
| 3357 |
|
|
int ips_sg_index = 0;
|
| 3358 |
|
|
int sg_dma_index;
|
| 3359 |
|
|
|
| 3360 |
|
|
sg = scb->scsi_cmd->request_buffer;
|
| 3361 |
|
|
|
| 3362 |
|
|
/* Spin forward to last dma chunk */
|
| 3363 |
|
|
sg_dma_index = scb->breakup;
|
| 3364 |
|
|
|
| 3365 |
|
|
/* Take care of possible partial on last chunk */
|
| 3366 |
|
|
ips_fill_scb_sg_single(ha,
|
| 3367 |
|
|
sg_dma_address(&sg
|
| 3368 |
|
|
[sg_dma_index]),
|
| 3369 |
|
|
scb, ips_sg_index++,
|
| 3370 |
|
|
sg_dma_len(&sg
|
| 3371 |
|
|
[sg_dma_index]));
|
| 3372 |
|
|
|
| 3373 |
|
|
for (; sg_dma_index < scb->sg_count;
|
| 3374 |
|
|
sg_dma_index++) {
|
| 3375 |
|
|
if (ips_fill_scb_sg_single
|
| 3376 |
|
|
(ha,
|
| 3377 |
|
|
sg_dma_address(&sg[sg_dma_index]),
|
| 3378 |
|
|
scb, ips_sg_index++,
|
| 3379 |
|
|
sg_dma_len(&sg[sg_dma_index])) < 0)
|
| 3380 |
|
|
break;
|
| 3381 |
|
|
|
| 3382 |
|
|
}
|
| 3383 |
|
|
|
| 3384 |
|
|
} else {
|
| 3385 |
|
|
/* Non S/G Request */
|
| 3386 |
|
|
(void) ips_fill_scb_sg_single(ha,
|
| 3387 |
|
|
scb->
|
| 3388 |
|
|
data_busaddr +
|
| 3389 |
|
|
(scb->sg_break *
|
| 3390 |
|
|
ha->max_xfer),
|
| 3391 |
|
|
scb, 0,
|
| 3392 |
|
|
scb->scsi_cmd->
|
| 3393 |
|
|
request_bufflen -
|
| 3394 |
|
|
(scb->sg_break *
|
| 3395 |
|
|
ha->max_xfer));
|
| 3396 |
|
|
}
|
| 3397 |
|
|
|
| 3398 |
|
|
scb->dcdb.transfer_length = scb->data_len;
|
| 3399 |
|
|
scb->dcdb.cmd_attribute |=
|
| 3400 |
|
|
ips_command_direction[scb->scsi_cmd->cmnd[0]];
|
| 3401 |
|
|
|
| 3402 |
|
|
if (!(scb->dcdb.cmd_attribute & 0x3))
|
| 3403 |
|
|
scb->dcdb.transfer_length = 0;
|
| 3404 |
|
|
|
| 3405 |
|
|
if (scb->data_len >= IPS_MAX_XFER) {
|
| 3406 |
|
|
scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
|
| 3407 |
|
|
scb->dcdb.transfer_length = 0;
|
| 3408 |
|
|
}
|
| 3409 |
|
|
|
| 3410 |
|
|
ret = ips_send_cmd(ha, scb);
|
| 3411 |
|
|
|
| 3412 |
|
|
switch (ret) {
|
| 3413 |
|
|
case IPS_FAILURE:
|
| 3414 |
|
|
if (scb->scsi_cmd) {
|
| 3415 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 3416 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 3417 |
|
|
}
|
| 3418 |
|
|
|
| 3419 |
|
|
ips_freescb(ha, scb);
|
| 3420 |
|
|
break;
|
| 3421 |
|
|
case IPS_SUCCESS_IMM:
|
| 3422 |
|
|
if (scb->scsi_cmd) {
|
| 3423 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 3424 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 3425 |
|
|
}
|
| 3426 |
|
|
|
| 3427 |
|
|
ips_freescb(ha, scb);
|
| 3428 |
|
|
break;
|
| 3429 |
|
|
default:
|
| 3430 |
|
|
break;
|
| 3431 |
|
|
} /* end case */
|
| 3432 |
|
|
|
| 3433 |
|
|
return;
|
| 3434 |
|
|
}
|
| 3435 |
|
|
} /* end if passthru */
|
| 3436 |
|
|
|
| 3437 |
|
|
if (scb->bus) {
|
| 3438 |
|
|
ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
|
| 3439 |
|
|
}
|
| 3440 |
|
|
|
| 3441 |
|
|
scb->scsi_cmd->scsi_done(scb->scsi_cmd);
|
| 3442 |
|
|
|
| 3443 |
|
|
ips_freescb(ha, scb);
|
| 3444 |
|
|
}
|
| 3445 |
|
|
|
| 3446 |
|
|
/****************************************************************************/
|
| 3447 |
|
|
/* */
|
| 3448 |
|
|
/* Routine Name: ips_map_status */
|
| 3449 |
|
|
/* */
|
| 3450 |
|
|
/* Routine Description: */
|
| 3451 |
|
|
/* */
|
| 3452 |
|
|
/* Map Controller Error codes to Linux Error Codes */
|
| 3453 |
|
|
/* */
|
| 3454 |
|
|
/****************************************************************************/
|
| 3455 |
|
|
static int
|
| 3456 |
|
|
ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
|
| 3457 |
|
|
{
|
| 3458 |
|
|
int errcode;
|
| 3459 |
|
|
int device_error;
|
| 3460 |
|
|
uint32_t transfer_len;
|
| 3461 |
|
|
IPS_DCDB_TABLE_TAPE *tapeDCDB;
|
| 3462 |
|
|
|
| 3463 |
|
|
METHOD_TRACE("ips_map_status", 1);
|
| 3464 |
|
|
|
| 3465 |
|
|
if (scb->bus) {
|
| 3466 |
|
|
DEBUG_VAR(2,
|
| 3467 |
|
|
"(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
|
| 3468 |
|
|
ips_name, ha->host_num, scb->scsi_cmd->channel,
|
| 3469 |
|
|
scb->scsi_cmd->target, scb->scsi_cmd->lun,
|
| 3470 |
|
|
scb->basic_status, scb->extended_status,
|
| 3471 |
|
|
scb->extended_status ==
|
| 3472 |
|
|
IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
|
| 3473 |
|
|
scb->extended_status ==
|
| 3474 |
|
|
IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
|
| 3475 |
|
|
scb->extended_status ==
|
| 3476 |
|
|
IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
|
| 3477 |
|
|
}
|
| 3478 |
|
|
|
| 3479 |
|
|
/* default driver error */
|
| 3480 |
|
|
errcode = DID_ERROR;
|
| 3481 |
|
|
device_error = 0;
|
| 3482 |
|
|
|
| 3483 |
|
|
switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
|
| 3484 |
|
|
case IPS_CMD_TIMEOUT:
|
| 3485 |
|
|
errcode = DID_TIME_OUT;
|
| 3486 |
|
|
break;
|
| 3487 |
|
|
|
| 3488 |
|
|
case IPS_INVAL_OPCO:
|
| 3489 |
|
|
case IPS_INVAL_CMD_BLK:
|
| 3490 |
|
|
case IPS_INVAL_PARM_BLK:
|
| 3491 |
|
|
case IPS_LD_ERROR:
|
| 3492 |
|
|
case IPS_CMD_CMPLT_WERROR:
|
| 3493 |
|
|
break;
|
| 3494 |
|
|
|
| 3495 |
|
|
case IPS_PHYS_DRV_ERROR:
|
| 3496 |
|
|
switch (scb->extended_status) {
|
| 3497 |
|
|
case IPS_ERR_SEL_TO:
|
| 3498 |
|
|
if (scb->bus)
|
| 3499 |
|
|
errcode = DID_NO_CONNECT;
|
| 3500 |
|
|
|
| 3501 |
|
|
break;
|
| 3502 |
|
|
|
| 3503 |
|
|
case IPS_ERR_OU_RUN:
|
| 3504 |
|
|
if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
|
| 3505 |
|
|
(scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)) {
|
| 3506 |
|
|
tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
|
| 3507 |
|
|
transfer_len = tapeDCDB->transfer_length;
|
| 3508 |
|
|
} else {
|
| 3509 |
|
|
transfer_len =
|
| 3510 |
|
|
(uint32_t) scb->dcdb.transfer_length;
|
| 3511 |
|
|
}
|
| 3512 |
|
|
|
| 3513 |
|
|
if ((scb->bus) && (transfer_len < scb->data_len)) {
|
| 3514 |
|
|
/* Underrun - set default to no error */
|
| 3515 |
|
|
errcode = DID_OK;
|
| 3516 |
|
|
|
| 3517 |
|
|
/* Restrict access to physical DASD */
|
| 3518 |
|
|
if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
|
| 3519 |
|
|
((((char
|
| 3520 |
|
|
*) scb->scsi_cmd->buffer)[0] & 0x1f) ==
|
| 3521 |
|
|
TYPE_DISK)) {
|
| 3522 |
|
|
/* underflow -- no error */
|
| 3523 |
|
|
/* restrict access to physical DASD */
|
| 3524 |
|
|
errcode = DID_TIME_OUT;
|
| 3525 |
|
|
break;
|
| 3526 |
|
|
}
|
| 3527 |
|
|
} else
|
| 3528 |
|
|
errcode = DID_ERROR;
|
| 3529 |
|
|
|
| 3530 |
|
|
break;
|
| 3531 |
|
|
|
| 3532 |
|
|
case IPS_ERR_RECOVERY:
|
| 3533 |
|
|
/* don't fail recovered errors */
|
| 3534 |
|
|
if (scb->bus)
|
| 3535 |
|
|
errcode = DID_OK;
|
| 3536 |
|
|
|
| 3537 |
|
|
break;
|
| 3538 |
|
|
|
| 3539 |
|
|
case IPS_ERR_HOST_RESET:
|
| 3540 |
|
|
case IPS_ERR_DEV_RESET:
|
| 3541 |
|
|
errcode = DID_RESET;
|
| 3542 |
|
|
break;
|
| 3543 |
|
|
|
| 3544 |
|
|
case IPS_ERR_CKCOND:
|
| 3545 |
|
|
if (scb->bus) {
|
| 3546 |
|
|
if (
|
| 3547 |
|
|
(scb->cmd.dcdb.op_code ==
|
| 3548 |
|
|
IPS_CMD_EXTENDED_DCDB)
|
| 3549 |
|
|
|| (scb->cmd.dcdb.op_code ==
|
| 3550 |
|
|
IPS_CMD_EXTENDED_DCDB_SG)) {
|
| 3551 |
|
|
tapeDCDB =
|
| 3552 |
|
|
(IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
|
| 3553 |
|
|
memcpy(scb->scsi_cmd->sense_buffer,
|
| 3554 |
|
|
tapeDCDB->sense_info,
|
| 3555 |
|
|
sizeof (scb->scsi_cmd->
|
| 3556 |
|
|
sense_buffer));
|
| 3557 |
|
|
} else {
|
| 3558 |
|
|
memcpy(scb->scsi_cmd->sense_buffer,
|
| 3559 |
|
|
scb->dcdb.sense_info,
|
| 3560 |
|
|
sizeof (scb->scsi_cmd->
|
| 3561 |
|
|
sense_buffer));
|
| 3562 |
|
|
}
|
| 3563 |
|
|
device_error = 2; /* check condition */
|
| 3564 |
|
|
}
|
| 3565 |
|
|
|
| 3566 |
|
|
errcode = DID_OK;
|
| 3567 |
|
|
|
| 3568 |
|
|
break;
|
| 3569 |
|
|
|
| 3570 |
|
|
default:
|
| 3571 |
|
|
errcode = DID_ERROR;
|
| 3572 |
|
|
break;
|
| 3573 |
|
|
|
| 3574 |
|
|
} /* end switch */
|
| 3575 |
|
|
} /* end switch */
|
| 3576 |
|
|
|
| 3577 |
|
|
scb->scsi_cmd->result = device_error | (errcode << 16);
|
| 3578 |
|
|
|
| 3579 |
|
|
return (1);
|
| 3580 |
|
|
}
|
| 3581 |
|
|
|
| 3582 |
|
|
/****************************************************************************/
|
| 3583 |
|
|
/* */
|
| 3584 |
|
|
/* Routine Name: ips_send_wait */
|
| 3585 |
|
|
/* */
|
| 3586 |
|
|
/* Routine Description: */
|
| 3587 |
|
|
/* */
|
| 3588 |
|
|
/* Send a command to the controller and wait for it to return */
|
| 3589 |
|
|
/* */
|
| 3590 |
|
|
/* The FFDC Time Stamp use this function for the callback, but doesn't */
|
| 3591 |
|
|
/* actually need to wait. */
|
| 3592 |
|
|
/****************************************************************************/
|
| 3593 |
|
|
static int
|
| 3594 |
|
|
ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
|
| 3595 |
|
|
{
|
| 3596 |
|
|
int ret;
|
| 3597 |
|
|
|
| 3598 |
|
|
METHOD_TRACE("ips_send_wait", 1);
|
| 3599 |
|
|
|
| 3600 |
|
|
if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
|
| 3601 |
|
|
ha->waitflag = TRUE;
|
| 3602 |
|
|
ha->cmd_in_progress = scb->cdb[0];
|
| 3603 |
|
|
}
|
| 3604 |
|
|
scb->callback = ipsintr_blocking;
|
| 3605 |
|
|
ret = ips_send_cmd(ha, scb);
|
| 3606 |
|
|
|
| 3607 |
|
|
if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
|
| 3608 |
|
|
return (ret);
|
| 3609 |
|
|
|
| 3610 |
|
|
if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
|
| 3611 |
|
|
ret = ips_wait(ha, timeout, intr);
|
| 3612 |
|
|
|
| 3613 |
|
|
return (ret);
|
| 3614 |
|
|
}
|
| 3615 |
|
|
|
| 3616 |
|
|
/****************************************************************************/
|
| 3617 |
|
|
/* */
|
| 3618 |
|
|
/* Routine Name: ips_scmd_buf_write */
|
| 3619 |
|
|
/* */
|
| 3620 |
|
|
/* Routine Description: */
|
| 3621 |
|
|
/* Write data to Scsi_Cmnd request_buffer at proper offsets */
|
| 3622 |
|
|
/****************************************************************************/
|
| 3623 |
|
|
static void
|
| 3624 |
|
|
ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
|
| 3625 |
|
|
int count)
|
| 3626 |
|
|
{
|
| 3627 |
|
|
if (scmd->use_sg) {
|
| 3628 |
|
|
int i;
|
| 3629 |
|
|
unsigned int min_cnt, xfer_cnt;
|
| 3630 |
|
|
char *cdata = (char *) data;
|
| 3631 |
|
|
struct scatterlist *sg = scmd->request_buffer;
|
| 3632 |
|
|
for (i = 0, xfer_cnt = 0;
|
| 3633 |
|
|
(i < scmd->use_sg) && (xfer_cnt < count); i++) {
|
| 3634 |
|
|
if (!IPS_SG_ADDRESS(&sg[i]))
|
| 3635 |
|
|
return;
|
| 3636 |
|
|
min_cnt = min(count - xfer_cnt, sg[i].length);
|
| 3637 |
|
|
memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
|
| 3638 |
|
|
min_cnt);
|
| 3639 |
|
|
xfer_cnt += min_cnt;
|
| 3640 |
|
|
}
|
| 3641 |
|
|
|
| 3642 |
|
|
} else {
|
| 3643 |
|
|
unsigned int min_cnt = min(count, scmd->request_bufflen);
|
| 3644 |
|
|
memcpy(scmd->request_buffer, data, min_cnt);
|
| 3645 |
|
|
}
|
| 3646 |
|
|
}
|
| 3647 |
|
|
|
| 3648 |
|
|
/****************************************************************************/
|
| 3649 |
|
|
/* */
|
| 3650 |
|
|
/* Routine Name: ips_scmd_buf_read */
|
| 3651 |
|
|
/* */
|
| 3652 |
|
|
/* Routine Description: */
|
| 3653 |
|
|
/* Copy data from a Scsi_Cmnd to a new, linear buffer */
|
| 3654 |
|
|
/****************************************************************************/
|
| 3655 |
|
|
static void
|
| 3656 |
|
|
ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
|
| 3657 |
|
|
int count)
|
| 3658 |
|
|
{
|
| 3659 |
|
|
if (scmd->use_sg) {
|
| 3660 |
|
|
int i;
|
| 3661 |
|
|
unsigned int min_cnt, xfer_cnt;
|
| 3662 |
|
|
char *cdata = (char *) data;
|
| 3663 |
|
|
struct scatterlist *sg = scmd->request_buffer;
|
| 3664 |
|
|
for (i = 0, xfer_cnt = 0;
|
| 3665 |
|
|
(i < scmd->use_sg) && (xfer_cnt < count); i++) {
|
| 3666 |
|
|
if (!IPS_SG_ADDRESS(&sg[i]))
|
| 3667 |
|
|
return;
|
| 3668 |
|
|
min_cnt = min(count - xfer_cnt, sg[i].length);
|
| 3669 |
|
|
memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
|
| 3670 |
|
|
min_cnt);
|
| 3671 |
|
|
xfer_cnt += min_cnt;
|
| 3672 |
|
|
}
|
| 3673 |
|
|
|
| 3674 |
|
|
} else {
|
| 3675 |
|
|
unsigned int min_cnt = min(count, scmd->request_bufflen);
|
| 3676 |
|
|
memcpy(data, scmd->request_buffer, min_cnt);
|
| 3677 |
|
|
}
|
| 3678 |
|
|
}
|
| 3679 |
|
|
|
| 3680 |
|
|
/****************************************************************************/
|
| 3681 |
|
|
/* */
|
| 3682 |
|
|
/* Routine Name: ips_send_cmd */
|
| 3683 |
|
|
/* */
|
| 3684 |
|
|
/* Routine Description: */
|
| 3685 |
|
|
/* */
|
| 3686 |
|
|
/* Map SCSI commands to ServeRAID commands for logical drives */
|
| 3687 |
|
|
/* */
|
| 3688 |
|
|
/****************************************************************************/
|
| 3689 |
|
|
static int
|
| 3690 |
|
|
ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
|
| 3691 |
|
|
{
|
| 3692 |
|
|
int ret;
|
| 3693 |
|
|
char *sp;
|
| 3694 |
|
|
int device_error;
|
| 3695 |
|
|
IPS_DCDB_TABLE_TAPE *tapeDCDB;
|
| 3696 |
|
|
int TimeOut;
|
| 3697 |
|
|
|
| 3698 |
|
|
METHOD_TRACE("ips_send_cmd", 1);
|
| 3699 |
|
|
|
| 3700 |
|
|
ret = IPS_SUCCESS;
|
| 3701 |
|
|
|
| 3702 |
|
|
if (!scb->scsi_cmd) {
|
| 3703 |
|
|
/* internal command */
|
| 3704 |
|
|
|
| 3705 |
|
|
if (scb->bus > 0) {
|
| 3706 |
|
|
/* Controller commands can't be issued */
|
| 3707 |
|
|
/* to real devices -- fail them */
|
| 3708 |
|
|
if ((ha->waitflag == TRUE) &&
|
| 3709 |
|
|
(ha->cmd_in_progress == scb->cdb[0])) {
|
| 3710 |
|
|
ha->waitflag = FALSE;
|
| 3711 |
|
|
}
|
| 3712 |
|
|
|
| 3713 |
|
|
return (1);
|
| 3714 |
|
|
}
|
| 3715 |
|
|
} else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
|
| 3716 |
|
|
/* command to logical bus -- interpret */
|
| 3717 |
|
|
ret = IPS_SUCCESS_IMM;
|
| 3718 |
|
|
|
| 3719 |
|
|
switch (scb->scsi_cmd->cmnd[0]) {
|
| 3720 |
|
|
case ALLOW_MEDIUM_REMOVAL:
|
| 3721 |
|
|
case REZERO_UNIT:
|
| 3722 |
|
|
case ERASE:
|
| 3723 |
|
|
case WRITE_FILEMARKS:
|
| 3724 |
|
|
case SPACE:
|
| 3725 |
|
|
scb->scsi_cmd->result = DID_ERROR << 16;
|
| 3726 |
|
|
break;
|
| 3727 |
|
|
|
| 3728 |
|
|
case START_STOP:
|
| 3729 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3730 |
|
|
|
| 3731 |
|
|
case TEST_UNIT_READY:
|
| 3732 |
|
|
case INQUIRY:
|
| 3733 |
|
|
if (scb->target_id == IPS_ADAPTER_ID) {
|
| 3734 |
|
|
/*
|
| 3735 |
|
|
* Either we have a TUR
|
| 3736 |
|
|
* or we have a SCSI inquiry
|
| 3737 |
|
|
*/
|
| 3738 |
|
|
if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
|
| 3739 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3740 |
|
|
|
| 3741 |
|
|
if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
|
| 3742 |
|
|
IPS_SCSI_INQ_DATA inquiry;
|
| 3743 |
|
|
|
| 3744 |
|
|
memset(&inquiry, 0,
|
| 3745 |
|
|
sizeof (IPS_SCSI_INQ_DATA));
|
| 3746 |
|
|
|
| 3747 |
|
|
inquiry.DeviceType =
|
| 3748 |
|
|
IPS_SCSI_INQ_TYPE_PROCESSOR;
|
| 3749 |
|
|
inquiry.DeviceTypeQualifier =
|
| 3750 |
|
|
IPS_SCSI_INQ_LU_CONNECTED;
|
| 3751 |
|
|
inquiry.Version = IPS_SCSI_INQ_REV2;
|
| 3752 |
|
|
inquiry.ResponseDataFormat =
|
| 3753 |
|
|
IPS_SCSI_INQ_RD_REV2;
|
| 3754 |
|
|
inquiry.AdditionalLength = 31;
|
| 3755 |
|
|
inquiry.Flags[0] =
|
| 3756 |
|
|
IPS_SCSI_INQ_Address16;
|
| 3757 |
|
|
inquiry.Flags[1] =
|
| 3758 |
|
|
IPS_SCSI_INQ_WBus16 |
|
| 3759 |
|
|
IPS_SCSI_INQ_Sync;
|
| 3760 |
|
|
strncpy(inquiry.VendorId, "IBM ",
|
| 3761 |
|
|
8);
|
| 3762 |
|
|
strncpy(inquiry.ProductId,
|
| 3763 |
|
|
"SERVERAID ", 16);
|
| 3764 |
|
|
strncpy(inquiry.ProductRevisionLevel,
|
| 3765 |
|
|
"1.00", 4);
|
| 3766 |
|
|
|
| 3767 |
|
|
ips_scmd_buf_write(scb->scsi_cmd,
|
| 3768 |
|
|
&inquiry,
|
| 3769 |
|
|
sizeof (inquiry));
|
| 3770 |
|
|
|
| 3771 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3772 |
|
|
}
|
| 3773 |
|
|
} else {
|
| 3774 |
|
|
scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
|
| 3775 |
|
|
scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3776 |
|
|
scb->cmd.logical_info.reserved = 0;
|
| 3777 |
|
|
scb->cmd.logical_info.reserved2 = 0;
|
| 3778 |
|
|
scb->data_len = sizeof (IPS_LD_INFO);
|
| 3779 |
|
|
scb->data_busaddr = ha->logical_drive_info_dma_addr;
|
| 3780 |
|
|
scb->flags = 0;
|
| 3781 |
|
|
scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
|
| 3782 |
|
|
ret = IPS_SUCCESS;
|
| 3783 |
|
|
}
|
| 3784 |
|
|
|
| 3785 |
|
|
break;
|
| 3786 |
|
|
|
| 3787 |
|
|
case REQUEST_SENSE:
|
| 3788 |
|
|
ips_reqsen(ha, scb);
|
| 3789 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3790 |
|
|
break;
|
| 3791 |
|
|
|
| 3792 |
|
|
case READ_6:
|
| 3793 |
|
|
case WRITE_6:
|
| 3794 |
|
|
if (!scb->sg_len) {
|
| 3795 |
|
|
scb->cmd.basic_io.op_code =
|
| 3796 |
|
|
(scb->scsi_cmd->cmnd[0] ==
|
| 3797 |
|
|
READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
|
| 3798 |
|
|
scb->cmd.basic_io.enhanced_sg = 0;
|
| 3799 |
|
|
scb->cmd.basic_io.sg_addr =
|
| 3800 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 3801 |
|
|
} else {
|
| 3802 |
|
|
scb->cmd.basic_io.op_code =
|
| 3803 |
|
|
(scb->scsi_cmd->cmnd[0] ==
|
| 3804 |
|
|
READ_6) ? IPS_CMD_READ_SG :
|
| 3805 |
|
|
IPS_CMD_WRITE_SG;
|
| 3806 |
|
|
scb->cmd.basic_io.enhanced_sg =
|
| 3807 |
|
|
IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
|
| 3808 |
|
|
scb->cmd.basic_io.sg_addr =
|
| 3809 |
|
|
cpu_to_le32(scb->sg_busaddr);
|
| 3810 |
|
|
}
|
| 3811 |
|
|
|
| 3812 |
|
|
scb->cmd.basic_io.segment_4G = 0;
|
| 3813 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3814 |
|
|
scb->cmd.basic_io.log_drv = scb->target_id;
|
| 3815 |
|
|
scb->cmd.basic_io.sg_count = scb->sg_len;
|
| 3816 |
|
|
|
| 3817 |
|
|
if (scb->cmd.basic_io.lba)
|
| 3818 |
|
|
scb->cmd.basic_io.lba =
|
| 3819 |
|
|
cpu_to_le32(le32_to_cpu
|
| 3820 |
|
|
(scb->cmd.basic_io.lba) +
|
| 3821 |
|
|
le16_to_cpu(scb->cmd.basic_io.
|
| 3822 |
|
|
sector_count));
|
| 3823 |
|
|
else
|
| 3824 |
|
|
scb->cmd.basic_io.lba =
|
| 3825 |
|
|
(((scb->
|
| 3826 |
|
|
scsi_cmd->cmnd[1] & 0x1f) << 16) | (scb->
|
| 3827 |
|
|
scsi_cmd->
|
| 3828 |
|
|
cmnd
|
| 3829 |
|
|
[2]
|
| 3830 |
|
|
<< 8)
|
| 3831 |
|
|
| (scb->scsi_cmd->cmnd[3]));
|
| 3832 |
|
|
|
| 3833 |
|
|
scb->cmd.basic_io.sector_count =
|
| 3834 |
|
|
cpu_to_le16(scb->data_len / IPS_BLKSIZE);
|
| 3835 |
|
|
|
| 3836 |
|
|
if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
|
| 3837 |
|
|
scb->cmd.basic_io.sector_count =
|
| 3838 |
|
|
cpu_to_le16(256);
|
| 3839 |
|
|
|
| 3840 |
|
|
ret = IPS_SUCCESS;
|
| 3841 |
|
|
break;
|
| 3842 |
|
|
|
| 3843 |
|
|
case READ_10:
|
| 3844 |
|
|
case WRITE_10:
|
| 3845 |
|
|
if (!scb->sg_len) {
|
| 3846 |
|
|
scb->cmd.basic_io.op_code =
|
| 3847 |
|
|
(scb->scsi_cmd->cmnd[0] ==
|
| 3848 |
|
|
READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
|
| 3849 |
|
|
scb->cmd.basic_io.enhanced_sg = 0;
|
| 3850 |
|
|
scb->cmd.basic_io.sg_addr =
|
| 3851 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 3852 |
|
|
} else {
|
| 3853 |
|
|
scb->cmd.basic_io.op_code =
|
| 3854 |
|
|
(scb->scsi_cmd->cmnd[0] ==
|
| 3855 |
|
|
READ_10) ? IPS_CMD_READ_SG :
|
| 3856 |
|
|
IPS_CMD_WRITE_SG;
|
| 3857 |
|
|
scb->cmd.basic_io.enhanced_sg =
|
| 3858 |
|
|
IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
|
| 3859 |
|
|
scb->cmd.basic_io.sg_addr =
|
| 3860 |
|
|
cpu_to_le32(scb->sg_busaddr);
|
| 3861 |
|
|
}
|
| 3862 |
|
|
|
| 3863 |
|
|
scb->cmd.basic_io.segment_4G = 0;
|
| 3864 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3865 |
|
|
scb->cmd.basic_io.log_drv = scb->target_id;
|
| 3866 |
|
|
scb->cmd.basic_io.sg_count = scb->sg_len;
|
| 3867 |
|
|
|
| 3868 |
|
|
if (scb->cmd.basic_io.lba)
|
| 3869 |
|
|
scb->cmd.basic_io.lba =
|
| 3870 |
|
|
cpu_to_le32(le32_to_cpu
|
| 3871 |
|
|
(scb->cmd.basic_io.lba) +
|
| 3872 |
|
|
le16_to_cpu(scb->cmd.basic_io.
|
| 3873 |
|
|
sector_count));
|
| 3874 |
|
|
else
|
| 3875 |
|
|
scb->cmd.basic_io.lba =
|
| 3876 |
|
|
((scb->
|
| 3877 |
|
|
scsi_cmd->cmnd[2] << 24) | (scb->
|
| 3878 |
|
|
scsi_cmd->
|
| 3879 |
|
|
cmnd[3] << 16)
|
| 3880 |
|
|
| (scb->scsi_cmd->cmnd[4] << 8) | scb->
|
| 3881 |
|
|
scsi_cmd->cmnd[5]);
|
| 3882 |
|
|
|
| 3883 |
|
|
scb->cmd.basic_io.sector_count =
|
| 3884 |
|
|
cpu_to_le16(scb->data_len / IPS_BLKSIZE);
|
| 3885 |
|
|
|
| 3886 |
|
|
if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
|
| 3887 |
|
|
/*
|
| 3888 |
|
|
* This is a null condition
|
| 3889 |
|
|
* we don't have to do anything
|
| 3890 |
|
|
* so just return
|
| 3891 |
|
|
*/
|
| 3892 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3893 |
|
|
} else
|
| 3894 |
|
|
ret = IPS_SUCCESS;
|
| 3895 |
|
|
|
| 3896 |
|
|
break;
|
| 3897 |
|
|
|
| 3898 |
|
|
case RESERVE:
|
| 3899 |
|
|
case RELEASE:
|
| 3900 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3901 |
|
|
break;
|
| 3902 |
|
|
|
| 3903 |
|
|
case MODE_SENSE:
|
| 3904 |
|
|
scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
|
| 3905 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3906 |
|
|
scb->cmd.basic_io.segment_4G = 0;
|
| 3907 |
|
|
scb->cmd.basic_io.enhanced_sg = 0;
|
| 3908 |
|
|
scb->data_len = sizeof (*ha->enq);
|
| 3909 |
|
|
scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
|
| 3910 |
|
|
ret = IPS_SUCCESS;
|
| 3911 |
|
|
break;
|
| 3912 |
|
|
|
| 3913 |
|
|
case READ_CAPACITY:
|
| 3914 |
|
|
scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
|
| 3915 |
|
|
scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3916 |
|
|
scb->cmd.logical_info.reserved = 0;
|
| 3917 |
|
|
scb->cmd.logical_info.reserved2 = 0;
|
| 3918 |
|
|
scb->cmd.logical_info.reserved3 = 0;
|
| 3919 |
|
|
scb->data_len = sizeof (IPS_LD_INFO);
|
| 3920 |
|
|
scb->data_busaddr = ha->logical_drive_info_dma_addr;
|
| 3921 |
|
|
scb->flags = 0;
|
| 3922 |
|
|
scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
|
| 3923 |
|
|
ret = IPS_SUCCESS;
|
| 3924 |
|
|
break;
|
| 3925 |
|
|
|
| 3926 |
|
|
case SEND_DIAGNOSTIC:
|
| 3927 |
|
|
case REASSIGN_BLOCKS:
|
| 3928 |
|
|
case FORMAT_UNIT:
|
| 3929 |
|
|
case SEEK_10:
|
| 3930 |
|
|
case VERIFY:
|
| 3931 |
|
|
case READ_DEFECT_DATA:
|
| 3932 |
|
|
case READ_BUFFER:
|
| 3933 |
|
|
case WRITE_BUFFER:
|
| 3934 |
|
|
scb->scsi_cmd->result = DID_OK << 16;
|
| 3935 |
|
|
break;
|
| 3936 |
|
|
|
| 3937 |
|
|
default:
|
| 3938 |
|
|
/* Set the Return Info to appear like the Command was */
|
| 3939 |
|
|
/* attempted, a Check Condition occurred, and Sense */
|
| 3940 |
|
|
/* Data indicating an Invalid CDB OpCode is returned. */
|
| 3941 |
|
|
sp = (char *) scb->scsi_cmd->sense_buffer;
|
| 3942 |
|
|
memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
|
| 3943 |
|
|
|
| 3944 |
|
|
sp[0] = 0x70; /* Error Code */
|
| 3945 |
|
|
sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
|
| 3946 |
|
|
sp[7] = 0x0A; /* Additional Sense Length */
|
| 3947 |
|
|
sp[12] = 0x20; /* ASC = Invalid OpCode */
|
| 3948 |
|
|
sp[13] = 0x00; /* ASCQ */
|
| 3949 |
|
|
|
| 3950 |
|
|
device_error = 2; /* Indicate Check Condition */
|
| 3951 |
|
|
scb->scsi_cmd->result = device_error | (DID_OK << 16);
|
| 3952 |
|
|
break;
|
| 3953 |
|
|
} /* end switch */
|
| 3954 |
|
|
}
|
| 3955 |
|
|
/* end if */
|
| 3956 |
|
|
if (ret == IPS_SUCCESS_IMM)
|
| 3957 |
|
|
return (ret);
|
| 3958 |
|
|
|
| 3959 |
|
|
/* setup DCDB */
|
| 3960 |
|
|
if (scb->bus > 0) {
|
| 3961 |
|
|
|
| 3962 |
|
|
/* If we already know the Device is Not there, no need to attempt a Command */
|
| 3963 |
|
|
/* This also protects an NT FailOver Controller from getting CDB's sent to it */
|
| 3964 |
|
|
if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
|
| 3965 |
|
|
scb->scsi_cmd->result = DID_NO_CONNECT << 16;
|
| 3966 |
|
|
return (IPS_SUCCESS_IMM);
|
| 3967 |
|
|
}
|
| 3968 |
|
|
|
| 3969 |
|
|
ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
|
| 3970 |
|
|
scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
|
| 3971 |
|
|
scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
|
| 3972 |
|
|
(unsigned long) &scb->
|
| 3973 |
|
|
dcdb -
|
| 3974 |
|
|
(unsigned long) scb);
|
| 3975 |
|
|
scb->cmd.dcdb.reserved = 0;
|
| 3976 |
|
|
scb->cmd.dcdb.reserved2 = 0;
|
| 3977 |
|
|
scb->cmd.dcdb.reserved3 = 0;
|
| 3978 |
|
|
scb->cmd.dcdb.segment_4G = 0;
|
| 3979 |
|
|
scb->cmd.dcdb.enhanced_sg = 0;
|
| 3980 |
|
|
|
| 3981 |
|
|
TimeOut = scb->scsi_cmd->timeout_per_command;
|
| 3982 |
|
|
|
| 3983 |
|
|
if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
|
| 3984 |
|
|
if (!scb->sg_len) {
|
| 3985 |
|
|
scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
|
| 3986 |
|
|
} else {
|
| 3987 |
|
|
scb->cmd.dcdb.op_code =
|
| 3988 |
|
|
IPS_CMD_EXTENDED_DCDB_SG;
|
| 3989 |
|
|
scb->cmd.dcdb.enhanced_sg =
|
| 3990 |
|
|
IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
|
| 3991 |
|
|
}
|
| 3992 |
|
|
|
| 3993 |
|
|
tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
|
| 3994 |
|
|
tapeDCDB->device_address =
|
| 3995 |
|
|
((scb->bus - 1) << 4) | scb->target_id;
|
| 3996 |
|
|
tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
|
| 3997 |
|
|
tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
|
| 3998 |
|
|
|
| 3999 |
|
|
if (TimeOut) {
|
| 4000 |
|
|
if (TimeOut < (10 * HZ))
|
| 4001 |
|
|
tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
|
| 4002 |
|
|
else if (TimeOut < (60 * HZ))
|
| 4003 |
|
|
tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
|
| 4004 |
|
|
else if (TimeOut < (1200 * HZ))
|
| 4005 |
|
|
tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
|
| 4006 |
|
|
}
|
| 4007 |
|
|
|
| 4008 |
|
|
tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
|
| 4009 |
|
|
tapeDCDB->reserved_for_LUN = 0;
|
| 4010 |
|
|
tapeDCDB->transfer_length = scb->data_len;
|
| 4011 |
|
|
if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
|
| 4012 |
|
|
tapeDCDB->buffer_pointer =
|
| 4013 |
|
|
cpu_to_le32(scb->sg_busaddr);
|
| 4014 |
|
|
else
|
| 4015 |
|
|
tapeDCDB->buffer_pointer =
|
| 4016 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 4017 |
|
|
tapeDCDB->sg_count = scb->sg_len;
|
| 4018 |
|
|
tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
|
| 4019 |
|
|
tapeDCDB->scsi_status = 0;
|
| 4020 |
|
|
tapeDCDB->reserved = 0;
|
| 4021 |
|
|
memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
|
| 4022 |
|
|
scb->scsi_cmd->cmd_len);
|
| 4023 |
|
|
} else {
|
| 4024 |
|
|
if (!scb->sg_len) {
|
| 4025 |
|
|
scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
|
| 4026 |
|
|
} else {
|
| 4027 |
|
|
scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
|
| 4028 |
|
|
scb->cmd.dcdb.enhanced_sg =
|
| 4029 |
|
|
IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
|
| 4030 |
|
|
}
|
| 4031 |
|
|
|
| 4032 |
|
|
scb->dcdb.device_address =
|
| 4033 |
|
|
((scb->bus - 1) << 4) | scb->target_id;
|
| 4034 |
|
|
scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
|
| 4035 |
|
|
|
| 4036 |
|
|
if (TimeOut) {
|
| 4037 |
|
|
if (TimeOut < (10 * HZ))
|
| 4038 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
|
| 4039 |
|
|
else if (TimeOut < (60 * HZ))
|
| 4040 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
|
| 4041 |
|
|
else if (TimeOut < (1200 * HZ))
|
| 4042 |
|
|
scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
|
| 4043 |
|
|
}
|
| 4044 |
|
|
|
| 4045 |
|
|
scb->dcdb.transfer_length = scb->data_len;
|
| 4046 |
|
|
if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
|
| 4047 |
|
|
scb->dcdb.transfer_length = 0;
|
| 4048 |
|
|
if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
|
| 4049 |
|
|
scb->dcdb.buffer_pointer =
|
| 4050 |
|
|
cpu_to_le32(scb->sg_busaddr);
|
| 4051 |
|
|
else
|
| 4052 |
|
|
scb->dcdb.buffer_pointer =
|
| 4053 |
|
|
cpu_to_le32(scb->data_busaddr);
|
| 4054 |
|
|
scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
|
| 4055 |
|
|
scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
|
| 4056 |
|
|
scb->dcdb.sg_count = scb->sg_len;
|
| 4057 |
|
|
scb->dcdb.reserved = 0;
|
| 4058 |
|
|
memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
|
| 4059 |
|
|
scb->scsi_cmd->cmd_len);
|
| 4060 |
|
|
scb->dcdb.scsi_status = 0;
|
| 4061 |
|
|
scb->dcdb.reserved2[0] = 0;
|
| 4062 |
|
|
scb->dcdb.reserved2[1] = 0;
|
| 4063 |
|
|
scb->dcdb.reserved2[2] = 0;
|
| 4064 |
|
|
}
|
| 4065 |
|
|
}
|
| 4066 |
|
|
|
| 4067 |
|
|
return ((*ha->func.issue) (ha, scb));
|
| 4068 |
|
|
}
|
| 4069 |
|
|
|
| 4070 |
|
|
/****************************************************************************/
|
| 4071 |
|
|
/* */
|
| 4072 |
|
|
/* Routine Name: ips_chk_status */
|
| 4073 |
|
|
/* */
|
| 4074 |
|
|
/* Routine Description: */
|
| 4075 |
|
|
/* */
|
| 4076 |
|
|
/* Check the status of commands to logical drives */
|
| 4077 |
|
|
/* Assumed to be called with the HA lock */
|
| 4078 |
|
|
/****************************************************************************/
|
| 4079 |
|
|
static void
|
| 4080 |
|
|
ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
|
| 4081 |
|
|
{
|
| 4082 |
|
|
ips_scb_t *scb;
|
| 4083 |
|
|
ips_stat_t *sp;
|
| 4084 |
|
|
uint8_t basic_status;
|
| 4085 |
|
|
uint8_t ext_status;
|
| 4086 |
|
|
int errcode;
|
| 4087 |
|
|
|
| 4088 |
|
|
METHOD_TRACE("ips_chkstatus", 1);
|
| 4089 |
|
|
|
| 4090 |
|
|
scb = &ha->scbs[pstatus->fields.command_id];
|
| 4091 |
|
|
scb->basic_status = basic_status =
|
| 4092 |
|
|
pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
|
| 4093 |
|
|
scb->extended_status = ext_status = pstatus->fields.extended_status;
|
| 4094 |
|
|
|
| 4095 |
|
|
sp = &ha->sp;
|
| 4096 |
|
|
sp->residue_len = 0;
|
| 4097 |
|
|
sp->scb_addr = (void *) scb;
|
| 4098 |
|
|
|
| 4099 |
|
|
/* Remove the item from the active queue */
|
| 4100 |
|
|
ips_removeq_scb(&ha->scb_activelist, scb);
|
| 4101 |
|
|
|
| 4102 |
|
|
if (!scb->scsi_cmd)
|
| 4103 |
|
|
/* internal commands are handled in do_ipsintr */
|
| 4104 |
|
|
return;
|
| 4105 |
|
|
|
| 4106 |
|
|
DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
|
| 4107 |
|
|
ips_name,
|
| 4108 |
|
|
ha->host_num,
|
| 4109 |
|
|
scb->cdb[0],
|
| 4110 |
|
|
scb->cmd.basic_io.command_id,
|
| 4111 |
|
|
scb->bus, scb->target_id, scb->lun);
|
| 4112 |
|
|
|
| 4113 |
|
|
if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
|
| 4114 |
|
|
/* passthru - just returns the raw result */
|
| 4115 |
|
|
return;
|
| 4116 |
|
|
|
| 4117 |
|
|
errcode = DID_OK;
|
| 4118 |
|
|
|
| 4119 |
|
|
if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
|
| 4120 |
|
|
((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
|
| 4121 |
|
|
|
| 4122 |
|
|
if (scb->bus == 0) {
|
| 4123 |
|
|
if ((basic_status & IPS_GSC_STATUS_MASK) ==
|
| 4124 |
|
|
IPS_CMD_RECOVERED_ERROR) {
|
| 4125 |
|
|
DEBUG_VAR(1,
|
| 4126 |
|
|
"(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
|
| 4127 |
|
|
ips_name, ha->host_num,
|
| 4128 |
|
|
scb->cmd.basic_io.op_code,
|
| 4129 |
|
|
basic_status, ext_status);
|
| 4130 |
|
|
}
|
| 4131 |
|
|
|
| 4132 |
|
|
switch (scb->scsi_cmd->cmnd[0]) {
|
| 4133 |
|
|
case ALLOW_MEDIUM_REMOVAL:
|
| 4134 |
|
|
case REZERO_UNIT:
|
| 4135 |
|
|
case ERASE:
|
| 4136 |
|
|
case WRITE_FILEMARKS:
|
| 4137 |
|
|
case SPACE:
|
| 4138 |
|
|
errcode = DID_ERROR;
|
| 4139 |
|
|
break;
|
| 4140 |
|
|
|
| 4141 |
|
|
case START_STOP:
|
| 4142 |
|
|
break;
|
| 4143 |
|
|
|
| 4144 |
|
|
case TEST_UNIT_READY:
|
| 4145 |
|
|
if (!ips_online(ha, scb)) {
|
| 4146 |
|
|
errcode = DID_TIME_OUT;
|
| 4147 |
|
|
}
|
| 4148 |
|
|
break;
|
| 4149 |
|
|
|
| 4150 |
|
|
case INQUIRY:
|
| 4151 |
|
|
if (ips_online(ha, scb)) {
|
| 4152 |
|
|
ips_inquiry(ha, scb);
|
| 4153 |
|
|
} else {
|
| 4154 |
|
|
errcode = DID_TIME_OUT;
|
| 4155 |
|
|
}
|
| 4156 |
|
|
break;
|
| 4157 |
|
|
|
| 4158 |
|
|
case REQUEST_SENSE:
|
| 4159 |
|
|
ips_reqsen(ha, scb);
|
| 4160 |
|
|
break;
|
| 4161 |
|
|
|
| 4162 |
|
|
case READ_6:
|
| 4163 |
|
|
case WRITE_6:
|
| 4164 |
|
|
case READ_10:
|
| 4165 |
|
|
case WRITE_10:
|
| 4166 |
|
|
case RESERVE:
|
| 4167 |
|
|
case RELEASE:
|
| 4168 |
|
|
break;
|
| 4169 |
|
|
|
| 4170 |
|
|
case MODE_SENSE:
|
| 4171 |
|
|
if (!ips_online(ha, scb)
|
| 4172 |
|
|
|| !ips_msense(ha, scb)) {
|
| 4173 |
|
|
errcode = DID_ERROR;
|
| 4174 |
|
|
}
|
| 4175 |
|
|
break;
|
| 4176 |
|
|
|
| 4177 |
|
|
case READ_CAPACITY:
|
| 4178 |
|
|
if (ips_online(ha, scb))
|
| 4179 |
|
|
ips_rdcap(ha, scb);
|
| 4180 |
|
|
else {
|
| 4181 |
|
|
errcode = DID_TIME_OUT;
|
| 4182 |
|
|
}
|
| 4183 |
|
|
break;
|
| 4184 |
|
|
|
| 4185 |
|
|
case SEND_DIAGNOSTIC:
|
| 4186 |
|
|
case REASSIGN_BLOCKS:
|
| 4187 |
|
|
break;
|
| 4188 |
|
|
|
| 4189 |
|
|
case FORMAT_UNIT:
|
| 4190 |
|
|
errcode = DID_ERROR;
|
| 4191 |
|
|
break;
|
| 4192 |
|
|
|
| 4193 |
|
|
case SEEK_10:
|
| 4194 |
|
|
case VERIFY:
|
| 4195 |
|
|
case READ_DEFECT_DATA:
|
| 4196 |
|
|
case READ_BUFFER:
|
| 4197 |
|
|
case WRITE_BUFFER:
|
| 4198 |
|
|
break;
|
| 4199 |
|
|
|
| 4200 |
|
|
default:
|
| 4201 |
|
|
errcode = DID_ERROR;
|
| 4202 |
|
|
} /* end switch */
|
| 4203 |
|
|
|
| 4204 |
|
|
scb->scsi_cmd->result = errcode << 16;
|
| 4205 |
|
|
} else { /* bus == 0 */
|
| 4206 |
|
|
/* restrict access to physical drives */
|
| 4207 |
|
|
if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
|
| 4208 |
|
|
((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
|
| 4209 |
|
|
TYPE_DISK)) {
|
| 4210 |
|
|
|
| 4211 |
|
|
scb->scsi_cmd->result = DID_TIME_OUT << 16;
|
| 4212 |
|
|
}
|
| 4213 |
|
|
} /* else */
|
| 4214 |
|
|
} else { /* recovered error / success */
|
| 4215 |
|
|
if (scb->bus == 0) {
|
| 4216 |
|
|
DEBUG_VAR(1,
|
| 4217 |
|
|
"(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
|
| 4218 |
|
|
ips_name, ha->host_num,
|
| 4219 |
|
|
scb->cmd.basic_io.op_code, basic_status,
|
| 4220 |
|
|
ext_status);
|
| 4221 |
|
|
}
|
| 4222 |
|
|
|
| 4223 |
|
|
ips_map_status(ha, scb, sp);
|
| 4224 |
|
|
} /* else */
|
| 4225 |
|
|
}
|
| 4226 |
|
|
|
| 4227 |
|
|
/****************************************************************************/
|
| 4228 |
|
|
/* */
|
| 4229 |
|
|
/* Routine Name: ips_online */
|
| 4230 |
|
|
/* */
|
| 4231 |
|
|
/* Routine Description: */
|
| 4232 |
|
|
/* */
|
| 4233 |
|
|
/* Determine if a logical drive is online */
|
| 4234 |
|
|
/* */
|
| 4235 |
|
|
/****************************************************************************/
|
| 4236 |
|
|
static int
|
| 4237 |
|
|
ips_online(ips_ha_t * ha, ips_scb_t * scb)
|
| 4238 |
|
|
{
|
| 4239 |
|
|
METHOD_TRACE("ips_online", 1);
|
| 4240 |
|
|
|
| 4241 |
|
|
if (scb->target_id >= IPS_MAX_LD)
|
| 4242 |
|
|
return (0);
|
| 4243 |
|
|
|
| 4244 |
|
|
if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
|
| 4245 |
|
|
memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
|
| 4246 |
|
|
return (0);
|
| 4247 |
|
|
}
|
| 4248 |
|
|
|
| 4249 |
|
|
if (ha->logical_drive_info->drive_info[scb->target_id].state !=
|
| 4250 |
|
|
IPS_LD_OFFLINE
|
| 4251 |
|
|
&& ha->logical_drive_info->drive_info[scb->target_id].state !=
|
| 4252 |
|
|
IPS_LD_FREE
|
| 4253 |
|
|
&& ha->logical_drive_info->drive_info[scb->target_id].state !=
|
| 4254 |
|
|
IPS_LD_CRS
|
| 4255 |
|
|
&& ha->logical_drive_info->drive_info[scb->target_id].state !=
|
| 4256 |
|
|
IPS_LD_SYS) return (1);
|
| 4257 |
|
|
else
|
| 4258 |
|
|
return (0);
|
| 4259 |
|
|
}
|
| 4260 |
|
|
|
| 4261 |
|
|
/****************************************************************************/
|
| 4262 |
|
|
/* */
|
| 4263 |
|
|
/* Routine Name: ips_inquiry */
|
| 4264 |
|
|
/* */
|
| 4265 |
|
|
/* Routine Description: */
|
| 4266 |
|
|
/* */
|
| 4267 |
|
|
/* Simulate an inquiry command to a logical drive */
|
| 4268 |
|
|
/* */
|
| 4269 |
|
|
/****************************************************************************/
|
| 4270 |
|
|
static int
|
| 4271 |
|
|
ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
|
| 4272 |
|
|
{
|
| 4273 |
|
|
IPS_SCSI_INQ_DATA inquiry;
|
| 4274 |
|
|
|
| 4275 |
|
|
METHOD_TRACE("ips_inquiry", 1);
|
| 4276 |
|
|
|
| 4277 |
|
|
memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
|
| 4278 |
|
|
|
| 4279 |
|
|
inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
|
| 4280 |
|
|
inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
|
| 4281 |
|
|
inquiry.Version = IPS_SCSI_INQ_REV2;
|
| 4282 |
|
|
inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
|
| 4283 |
|
|
inquiry.AdditionalLength = 31;
|
| 4284 |
|
|
inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
|
| 4285 |
|
|
inquiry.Flags[1] =
|
| 4286 |
|
|
IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
|
| 4287 |
|
|
strncpy(inquiry.VendorId, "IBM ", 8);
|
| 4288 |
|
|
strncpy(inquiry.ProductId, "SERVERAID ", 16);
|
| 4289 |
|
|
strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
|
| 4290 |
|
|
|
| 4291 |
|
|
ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
|
| 4292 |
|
|
|
| 4293 |
|
|
return (1);
|
| 4294 |
|
|
}
|
| 4295 |
|
|
|
| 4296 |
|
|
/****************************************************************************/
|
| 4297 |
|
|
/* */
|
| 4298 |
|
|
/* Routine Name: ips_rdcap */
|
| 4299 |
|
|
/* */
|
| 4300 |
|
|
/* Routine Description: */
|
| 4301 |
|
|
/* */
|
| 4302 |
|
|
/* Simulate a read capacity command to a logical drive */
|
| 4303 |
|
|
/* */
|
| 4304 |
|
|
/****************************************************************************/
|
| 4305 |
|
|
static int
|
| 4306 |
|
|
ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
|
| 4307 |
|
|
{
|
| 4308 |
|
|
IPS_SCSI_CAPACITY cap;
|
| 4309 |
|
|
|
| 4310 |
|
|
METHOD_TRACE("ips_rdcap", 1);
|
| 4311 |
|
|
|
| 4312 |
|
|
if (scb->scsi_cmd->bufflen < 8)
|
| 4313 |
|
|
return (0);
|
| 4314 |
|
|
|
| 4315 |
|
|
cap.lba =
|
| 4316 |
|
|
cpu_to_be32(le32_to_cpu
|
| 4317 |
|
|
(ha->logical_drive_info->
|
| 4318 |
|
|
drive_info[scb->target_id].sector_count) - 1);
|
| 4319 |
|
|
cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
|
| 4320 |
|
|
|
| 4321 |
|
|
ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
|
| 4322 |
|
|
|
| 4323 |
|
|
return (1);
|
| 4324 |
|
|
}
|
| 4325 |
|
|
|
| 4326 |
|
|
/****************************************************************************/
|
| 4327 |
|
|
/* */
|
| 4328 |
|
|
/* Routine Name: ips_msense */
|
| 4329 |
|
|
/* */
|
| 4330 |
|
|
/* Routine Description: */
|
| 4331 |
|
|
/* */
|
| 4332 |
|
|
/* Simulate a mode sense command to a logical drive */
|
| 4333 |
|
|
/* */
|
| 4334 |
|
|
/****************************************************************************/
|
| 4335 |
|
|
static int
|
| 4336 |
|
|
ips_msense(ips_ha_t * ha, ips_scb_t * scb)
|
| 4337 |
|
|
{
|
| 4338 |
|
|
uint16_t heads;
|
| 4339 |
|
|
uint16_t sectors;
|
| 4340 |
|
|
uint32_t cylinders;
|
| 4341 |
|
|
IPS_SCSI_MODE_PAGE_DATA mdata;
|
| 4342 |
|
|
|
| 4343 |
|
|
METHOD_TRACE("ips_msense", 1);
|
| 4344 |
|
|
|
| 4345 |
|
|
if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
|
| 4346 |
|
|
(ha->enq->ucMiscFlag & 0x8) == 0) {
|
| 4347 |
|
|
heads = IPS_NORM_HEADS;
|
| 4348 |
|
|
sectors = IPS_NORM_SECTORS;
|
| 4349 |
|
|
} else {
|
| 4350 |
|
|
heads = IPS_COMP_HEADS;
|
| 4351 |
|
|
sectors = IPS_COMP_SECTORS;
|
| 4352 |
|
|
}
|
| 4353 |
|
|
|
| 4354 |
|
|
cylinders =
|
| 4355 |
|
|
(le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
|
| 4356 |
|
|
1) / (heads * sectors);
|
| 4357 |
|
|
|
| 4358 |
|
|
memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
|
| 4359 |
|
|
|
| 4360 |
|
|
mdata.hdr.BlockDescLength = 8;
|
| 4361 |
|
|
|
| 4362 |
|
|
switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
|
| 4363 |
|
|
case 0x03: /* page 3 */
|
| 4364 |
|
|
mdata.pdata.pg3.PageCode = 3;
|
| 4365 |
|
|
mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
|
| 4366 |
|
|
mdata.hdr.DataLength =
|
| 4367 |
|
|
3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
|
| 4368 |
|
|
mdata.pdata.pg3.TracksPerZone = 0;
|
| 4369 |
|
|
mdata.pdata.pg3.AltSectorsPerZone = 0;
|
| 4370 |
|
|
mdata.pdata.pg3.AltTracksPerZone = 0;
|
| 4371 |
|
|
mdata.pdata.pg3.AltTracksPerVolume = 0;
|
| 4372 |
|
|
mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
|
| 4373 |
|
|
mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
|
| 4374 |
|
|
mdata.pdata.pg3.Interleave = cpu_to_be16(1);
|
| 4375 |
|
|
mdata.pdata.pg3.TrackSkew = 0;
|
| 4376 |
|
|
mdata.pdata.pg3.CylinderSkew = 0;
|
| 4377 |
|
|
mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
|
| 4378 |
|
|
break;
|
| 4379 |
|
|
|
| 4380 |
|
|
case 0x4:
|
| 4381 |
|
|
mdata.pdata.pg4.PageCode = 4;
|
| 4382 |
|
|
mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
|
| 4383 |
|
|
mdata.hdr.DataLength =
|
| 4384 |
|
|
3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
|
| 4385 |
|
|
mdata.pdata.pg4.CylindersHigh =
|
| 4386 |
|
|
cpu_to_be16((cylinders >> 8) & 0xFFFF);
|
| 4387 |
|
|
mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
|
| 4388 |
|
|
mdata.pdata.pg4.Heads = heads;
|
| 4389 |
|
|
mdata.pdata.pg4.WritePrecompHigh = 0;
|
| 4390 |
|
|
mdata.pdata.pg4.WritePrecompLow = 0;
|
| 4391 |
|
|
mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
|
| 4392 |
|
|
mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
|
| 4393 |
|
|
mdata.pdata.pg4.StepRate = cpu_to_be16(1);
|
| 4394 |
|
|
mdata.pdata.pg4.LandingZoneHigh = 0;
|
| 4395 |
|
|
mdata.pdata.pg4.LandingZoneLow = 0;
|
| 4396 |
|
|
mdata.pdata.pg4.flags = 0;
|
| 4397 |
|
|
mdata.pdata.pg4.RotationalOffset = 0;
|
| 4398 |
|
|
mdata.pdata.pg4.MediumRotationRate = 0;
|
| 4399 |
|
|
break;
|
| 4400 |
|
|
|
| 4401 |
|
|
default:
|
| 4402 |
|
|
return (0);
|
| 4403 |
|
|
} /* end switch */
|
| 4404 |
|
|
|
| 4405 |
|
|
ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
|
| 4406 |
|
|
|
| 4407 |
|
|
return (1);
|
| 4408 |
|
|
}
|
| 4409 |
|
|
|
| 4410 |
|
|
/****************************************************************************/
|
| 4411 |
|
|
/* */
|
| 4412 |
|
|
/* Routine Name: ips_reqsen */
|
| 4413 |
|
|
/* */
|
| 4414 |
|
|
/* Routine Description: */
|
| 4415 |
|
|
/* */
|
| 4416 |
|
|
/* Simulate a request sense command to a logical drive */
|
| 4417 |
|
|
/* */
|
| 4418 |
|
|
/****************************************************************************/
|
| 4419 |
|
|
static int
|
| 4420 |
|
|
ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
|
| 4421 |
|
|
{
|
| 4422 |
|
|
IPS_SCSI_REQSEN reqsen;
|
| 4423 |
|
|
|
| 4424 |
|
|
METHOD_TRACE("ips_reqsen", 1);
|
| 4425 |
|
|
|
| 4426 |
|
|
memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
|
| 4427 |
|
|
|
| 4428 |
|
|
reqsen.ResponseCode =
|
| 4429 |
|
|
IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
|
| 4430 |
|
|
reqsen.AdditionalLength = 10;
|
| 4431 |
|
|
reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
|
| 4432 |
|
|
reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
|
| 4433 |
|
|
|
| 4434 |
|
|
ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
|
| 4435 |
|
|
|
| 4436 |
|
|
return (1);
|
| 4437 |
|
|
}
|
| 4438 |
|
|
|
| 4439 |
|
|
/****************************************************************************/
|
| 4440 |
|
|
/* */
|
| 4441 |
|
|
/* Routine Name: ips_free */
|
| 4442 |
|
|
/* */
|
| 4443 |
|
|
/* Routine Description: */
|
| 4444 |
|
|
/* */
|
| 4445 |
|
|
/* Free any allocated space for this controller */
|
| 4446 |
|
|
/* */
|
| 4447 |
|
|
/****************************************************************************/
|
| 4448 |
|
|
static void
|
| 4449 |
|
|
ips_free(ips_ha_t * ha)
|
| 4450 |
|
|
{
|
| 4451 |
|
|
|
| 4452 |
|
|
METHOD_TRACE("ips_free", 1);
|
| 4453 |
|
|
|
| 4454 |
|
|
if (ha) {
|
| 4455 |
|
|
if (ha->enq) {
|
| 4456 |
|
|
pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
|
| 4457 |
|
|
ha->enq, ha->enq_busaddr);
|
| 4458 |
|
|
ha->enq = NULL;
|
| 4459 |
|
|
}
|
| 4460 |
|
|
|
| 4461 |
|
|
if (ha->conf) {
|
| 4462 |
|
|
kfree(ha->conf);
|
| 4463 |
|
|
ha->conf = NULL;
|
| 4464 |
|
|
}
|
| 4465 |
|
|
|
| 4466 |
|
|
if (ha->adapt) {
|
| 4467 |
|
|
pci_free_consistent(ha->pcidev,
|
| 4468 |
|
|
sizeof (IPS_ADAPTER) +
|
| 4469 |
|
|
sizeof (IPS_IO_CMD), ha->adapt,
|
| 4470 |
|
|
ha->adapt->hw_status_start);
|
| 4471 |
|
|
ha->adapt = NULL;
|
| 4472 |
|
|
}
|
| 4473 |
|
|
|
| 4474 |
|
|
if (ha->logical_drive_info) {
|
| 4475 |
|
|
pci_free_consistent(ha->pcidev,
|
| 4476 |
|
|
sizeof (IPS_LD_INFO),
|
| 4477 |
|
|
ha->logical_drive_info,
|
| 4478 |
|
|
ha->logical_drive_info_dma_addr);
|
| 4479 |
|
|
ha->logical_drive_info = NULL;
|
| 4480 |
|
|
}
|
| 4481 |
|
|
|
| 4482 |
|
|
if (ha->nvram) {
|
| 4483 |
|
|
kfree(ha->nvram);
|
| 4484 |
|
|
ha->nvram = NULL;
|
| 4485 |
|
|
}
|
| 4486 |
|
|
|
| 4487 |
|
|
if (ha->subsys) {
|
| 4488 |
|
|
kfree(ha->subsys);
|
| 4489 |
|
|
ha->subsys = NULL;
|
| 4490 |
|
|
}
|
| 4491 |
|
|
|
| 4492 |
|
|
if (ha->ioctl_data) {
|
| 4493 |
|
|
pci_free_consistent(ha->pcidev, ha->ioctl_len,
|
| 4494 |
|
|
ha->ioctl_data, ha->ioctl_busaddr);
|
| 4495 |
|
|
ha->ioctl_data = NULL;
|
| 4496 |
|
|
ha->ioctl_datasize = 0;
|
| 4497 |
|
|
ha->ioctl_len = 0;
|
| 4498 |
|
|
}
|
| 4499 |
|
|
ips_deallocatescbs(ha, ha->max_cmds);
|
| 4500 |
|
|
|
| 4501 |
|
|
/* free memory mapped (if applicable) */
|
| 4502 |
|
|
if (ha->mem_ptr) {
|
| 4503 |
|
|
iounmap(ha->ioremap_ptr);
|
| 4504 |
|
|
ha->ioremap_ptr = NULL;
|
| 4505 |
|
|
ha->mem_ptr = NULL;
|
| 4506 |
|
|
}
|
| 4507 |
|
|
|
| 4508 |
|
|
if (ha->mem_addr)
|
| 4509 |
|
|
release_mem_region(ha->mem_addr, ha->mem_len);
|
| 4510 |
|
|
ha->mem_addr = 0;
|
| 4511 |
|
|
|
| 4512 |
|
|
}
|
| 4513 |
|
|
}
|
| 4514 |
|
|
|
| 4515 |
|
|
/****************************************************************************/
|
| 4516 |
|
|
/* */
|
| 4517 |
|
|
/* Routine Name: ips_deallocatescbs */
|
| 4518 |
|
|
/* */
|
| 4519 |
|
|
/* Routine Description: */
|
| 4520 |
|
|
/* */
|
| 4521 |
|
|
/* Free the command blocks */
|
| 4522 |
|
|
/* */
|
| 4523 |
|
|
/****************************************************************************/
|
| 4524 |
|
|
static int
|
| 4525 |
|
|
ips_deallocatescbs(ips_ha_t * ha, int cmds)
|
| 4526 |
|
|
{
|
| 4527 |
|
|
if (ha->scbs) {
|
| 4528 |
|
|
pci_free_consistent(ha->pcidev,
|
| 4529 |
|
|
IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
|
| 4530 |
|
|
ha->scbs->sg_list.list,
|
| 4531 |
|
|
ha->scbs->sg_busaddr);
|
| 4532 |
|
|
pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
|
| 4533 |
|
|
ha->scbs, ha->scbs->scb_busaddr);
|
| 4534 |
|
|
ha->scbs = NULL;
|
| 4535 |
|
|
} /* end if */
|
| 4536 |
|
|
return 1;
|
| 4537 |
|
|
}
|
| 4538 |
|
|
|
| 4539 |
|
|
/****************************************************************************/
|
| 4540 |
|
|
/* */
|
| 4541 |
|
|
/* Routine Name: ips_allocatescbs */
|
| 4542 |
|
|
/* */
|
| 4543 |
|
|
/* Routine Description: */
|
| 4544 |
|
|
/* */
|
| 4545 |
|
|
/* Allocate the command blocks */
|
| 4546 |
|
|
/* */
|
| 4547 |
|
|
/****************************************************************************/
|
| 4548 |
|
|
static int
|
| 4549 |
|
|
ips_allocatescbs(ips_ha_t * ha)
|
| 4550 |
|
|
{
|
| 4551 |
|
|
ips_scb_t *scb_p;
|
| 4552 |
|
|
IPS_SG_LIST ips_sg;
|
| 4553 |
|
|
int i;
|
| 4554 |
|
|
dma_addr_t command_dma, sg_dma;
|
| 4555 |
|
|
|
| 4556 |
|
|
METHOD_TRACE("ips_allocatescbs", 1);
|
| 4557 |
|
|
|
| 4558 |
|
|
/* Allocate memory for the SCBs */
|
| 4559 |
|
|
ha->scbs =
|
| 4560 |
|
|
pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
|
| 4561 |
|
|
&command_dma);
|
| 4562 |
|
|
if (ha->scbs == NULL)
|
| 4563 |
|
|
return 0;
|
| 4564 |
|
|
ips_sg.list =
|
| 4565 |
|
|
pci_alloc_consistent(ha->pcidev,
|
| 4566 |
|
|
IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
|
| 4567 |
|
|
ha->max_cmds, &sg_dma);
|
| 4568 |
|
|
if (ips_sg.list == NULL) {
|
| 4569 |
|
|
pci_free_consistent(ha->pcidev,
|
| 4570 |
|
|
ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
|
| 4571 |
|
|
command_dma);
|
| 4572 |
|
|
return 0;
|
| 4573 |
|
|
}
|
| 4574 |
|
|
|
| 4575 |
|
|
memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
|
| 4576 |
|
|
|
| 4577 |
|
|
for (i = 0; i < ha->max_cmds; i++) {
|
| 4578 |
|
|
scb_p = &ha->scbs[i];
|
| 4579 |
|
|
scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
|
| 4580 |
|
|
/* set up S/G list */
|
| 4581 |
|
|
if (IPS_USE_ENH_SGLIST(ha)) {
|
| 4582 |
|
|
scb_p->sg_list.enh_list =
|
| 4583 |
|
|
ips_sg.enh_list + i * IPS_MAX_SG;
|
| 4584 |
|
|
scb_p->sg_busaddr =
|
| 4585 |
|
|
sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
|
| 4586 |
|
|
} else {
|
| 4587 |
|
|
scb_p->sg_list.std_list =
|
| 4588 |
|
|
ips_sg.std_list + i * IPS_MAX_SG;
|
| 4589 |
|
|
scb_p->sg_busaddr =
|
| 4590 |
|
|
sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
|
| 4591 |
|
|
}
|
| 4592 |
|
|
|
| 4593 |
|
|
/* add to the free list */
|
| 4594 |
|
|
if (i < ha->max_cmds - 1) {
|
| 4595 |
|
|
scb_p->q_next = ha->scb_freelist;
|
| 4596 |
|
|
ha->scb_freelist = scb_p;
|
| 4597 |
|
|
}
|
| 4598 |
|
|
}
|
| 4599 |
|
|
|
| 4600 |
|
|
/* success */
|
| 4601 |
|
|
return (1);
|
| 4602 |
|
|
}
|
| 4603 |
|
|
|
| 4604 |
|
|
/****************************************************************************/
|
| 4605 |
|
|
/* */
|
| 4606 |
|
|
/* Routine Name: ips_init_scb */
|
| 4607 |
|
|
/* */
|
| 4608 |
|
|
/* Routine Description: */
|
| 4609 |
|
|
/* */
|
| 4610 |
|
|
/* Initialize a CCB to default values */
|
| 4611 |
|
|
/* */
|
| 4612 |
|
|
/****************************************************************************/
|
| 4613 |
|
|
static void
|
| 4614 |
|
|
ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
|
| 4615 |
|
|
{
|
| 4616 |
|
|
IPS_SG_LIST sg_list;
|
| 4617 |
|
|
uint32_t cmd_busaddr, sg_busaddr;
|
| 4618 |
|
|
METHOD_TRACE("ips_init_scb", 1);
|
| 4619 |
|
|
|
| 4620 |
|
|
if (scb == NULL)
|
| 4621 |
|
|
return;
|
| 4622 |
|
|
|
| 4623 |
|
|
sg_list.list = scb->sg_list.list;
|
| 4624 |
|
|
cmd_busaddr = scb->scb_busaddr;
|
| 4625 |
|
|
sg_busaddr = scb->sg_busaddr;
|
| 4626 |
|
|
/* zero fill */
|
| 4627 |
|
|
memset(scb, 0, sizeof (ips_scb_t));
|
| 4628 |
|
|
memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
|
| 4629 |
|
|
|
| 4630 |
|
|
/* Initialize dummy command bucket */
|
| 4631 |
|
|
ha->dummy->op_code = 0xFF;
|
| 4632 |
|
|
ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
|
| 4633 |
|
|
+ sizeof (IPS_ADAPTER));
|
| 4634 |
|
|
ha->dummy->command_id = IPS_MAX_CMDS;
|
| 4635 |
|
|
|
| 4636 |
|
|
/* set bus address of scb */
|
| 4637 |
|
|
scb->scb_busaddr = cmd_busaddr;
|
| 4638 |
|
|
scb->sg_busaddr = sg_busaddr;
|
| 4639 |
|
|
scb->sg_list.list = sg_list.list;
|
| 4640 |
|
|
|
| 4641 |
|
|
/* Neptune Fix */
|
| 4642 |
|
|
scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
|
| 4643 |
|
|
scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
|
| 4644 |
|
|
+ sizeof (IPS_ADAPTER));
|
| 4645 |
|
|
}
|
| 4646 |
|
|
|
| 4647 |
|
|
/****************************************************************************/
|
| 4648 |
|
|
/* */
|
| 4649 |
|
|
/* Routine Name: ips_get_scb */
|
| 4650 |
|
|
/* */
|
| 4651 |
|
|
/* Routine Description: */
|
| 4652 |
|
|
/* */
|
| 4653 |
|
|
/* Initialize a CCB to default values */
|
| 4654 |
|
|
/* */
|
| 4655 |
|
|
/* ASSUMED to be callled from within a lock */
|
| 4656 |
|
|
/* */
|
| 4657 |
|
|
/****************************************************************************/
|
| 4658 |
|
|
static ips_scb_t *
|
| 4659 |
|
|
ips_getscb(ips_ha_t * ha)
|
| 4660 |
|
|
{
|
| 4661 |
|
|
ips_scb_t *scb;
|
| 4662 |
|
|
|
| 4663 |
|
|
METHOD_TRACE("ips_getscb", 1);
|
| 4664 |
|
|
|
| 4665 |
|
|
if ((scb = ha->scb_freelist) == NULL) {
|
| 4666 |
|
|
|
| 4667 |
|
|
return (NULL);
|
| 4668 |
|
|
}
|
| 4669 |
|
|
|
| 4670 |
|
|
ha->scb_freelist = scb->q_next;
|
| 4671 |
|
|
scb->flags = 0;
|
| 4672 |
|
|
scb->q_next = NULL;
|
| 4673 |
|
|
|
| 4674 |
|
|
ips_init_scb(ha, scb);
|
| 4675 |
|
|
|
| 4676 |
|
|
return (scb);
|
| 4677 |
|
|
}
|
| 4678 |
|
|
|
| 4679 |
|
|
/****************************************************************************/
|
| 4680 |
|
|
/* */
|
| 4681 |
|
|
/* Routine Name: ips_free_scb */
|
| 4682 |
|
|
/* */
|
| 4683 |
|
|
/* Routine Description: */
|
| 4684 |
|
|
/* */
|
| 4685 |
|
|
/* Return an unused CCB back to the free list */
|
| 4686 |
|
|
/* */
|
| 4687 |
|
|
/* ASSUMED to be called from within a lock */
|
| 4688 |
|
|
/* */
|
| 4689 |
|
|
/****************************************************************************/
|
| 4690 |
|
|
static void
|
| 4691 |
|
|
ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
|
| 4692 |
|
|
{
|
| 4693 |
|
|
|
| 4694 |
|
|
METHOD_TRACE("ips_freescb", 1);
|
| 4695 |
|
|
if (scb->flags & IPS_SCB_MAP_SG)
|
| 4696 |
|
|
pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
|
| 4697 |
|
|
scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
|
| 4698 |
|
|
else if (scb->flags & IPS_SCB_MAP_SINGLE)
|
| 4699 |
|
|
pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
|
| 4700 |
|
|
IPS_DMA_DIR(scb));
|
| 4701 |
|
|
|
| 4702 |
|
|
/* check to make sure this is not our "special" scb */
|
| 4703 |
|
|
if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
|
| 4704 |
|
|
scb->q_next = ha->scb_freelist;
|
| 4705 |
|
|
ha->scb_freelist = scb;
|
| 4706 |
|
|
}
|
| 4707 |
|
|
}
|
| 4708 |
|
|
|
| 4709 |
|
|
/****************************************************************************/
|
| 4710 |
|
|
/* */
|
| 4711 |
|
|
/* Routine Name: ips_isinit_copperhead */
|
| 4712 |
|
|
/* */
|
| 4713 |
|
|
/* Routine Description: */
|
| 4714 |
|
|
/* */
|
| 4715 |
|
|
/* Is controller initialized ? */
|
| 4716 |
|
|
/* */
|
| 4717 |
|
|
/****************************************************************************/
|
| 4718 |
|
|
static int
|
| 4719 |
|
|
ips_isinit_copperhead(ips_ha_t * ha)
|
| 4720 |
|
|
{
|
| 4721 |
|
|
uint8_t scpr;
|
| 4722 |
|
|
uint8_t isr;
|
| 4723 |
|
|
|
| 4724 |
|
|
METHOD_TRACE("ips_isinit_copperhead", 1);
|
| 4725 |
|
|
|
| 4726 |
|
|
isr = inb(ha->io_addr + IPS_REG_HISR);
|
| 4727 |
|
|
scpr = inb(ha->io_addr + IPS_REG_SCPR);
|
| 4728 |
|
|
|
| 4729 |
|
|
if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
|
| 4730 |
|
|
return (0);
|
| 4731 |
|
|
else
|
| 4732 |
|
|
return (1);
|
| 4733 |
|
|
}
|
| 4734 |
|
|
|
| 4735 |
|
|
/****************************************************************************/
|
| 4736 |
|
|
/* */
|
| 4737 |
|
|
/* Routine Name: ips_isinit_copperhead_memio */
|
| 4738 |
|
|
/* */
|
| 4739 |
|
|
/* Routine Description: */
|
| 4740 |
|
|
/* */
|
| 4741 |
|
|
/* Is controller initialized ? */
|
| 4742 |
|
|
/* */
|
| 4743 |
|
|
/****************************************************************************/
|
| 4744 |
|
|
static int
|
| 4745 |
|
|
ips_isinit_copperhead_memio(ips_ha_t * ha)
|
| 4746 |
|
|
{
|
| 4747 |
|
|
uint8_t isr = 0;
|
| 4748 |
|
|
uint8_t scpr;
|
| 4749 |
|
|
|
| 4750 |
|
|
METHOD_TRACE("ips_is_init_copperhead_memio", 1);
|
| 4751 |
|
|
|
| 4752 |
|
|
isr = readb(ha->mem_ptr + IPS_REG_HISR);
|
| 4753 |
|
|
scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
|
| 4754 |
|
|
|
| 4755 |
|
|
if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
|
| 4756 |
|
|
return (0);
|
| 4757 |
|
|
else
|
| 4758 |
|
|
return (1);
|
| 4759 |
|
|
}
|
| 4760 |
|
|
|
| 4761 |
|
|
/****************************************************************************/
|
| 4762 |
|
|
/* */
|
| 4763 |
|
|
/* Routine Name: ips_isinit_morpheus */
|
| 4764 |
|
|
/* */
|
| 4765 |
|
|
/* Routine Description: */
|
| 4766 |
|
|
/* */
|
| 4767 |
|
|
/* Is controller initialized ? */
|
| 4768 |
|
|
/* */
|
| 4769 |
|
|
/****************************************************************************/
|
| 4770 |
|
|
static int
|
| 4771 |
|
|
ips_isinit_morpheus(ips_ha_t * ha)
|
| 4772 |
|
|
{
|
| 4773 |
|
|
uint32_t post;
|
| 4774 |
|
|
uint32_t bits;
|
| 4775 |
|
|
|
| 4776 |
|
|
METHOD_TRACE("ips_is_init_morpheus", 1);
|
| 4777 |
|
|
|
| 4778 |
|
|
post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
|
| 4779 |
|
|
bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 4780 |
|
|
|
| 4781 |
|
|
if (post == 0)
|
| 4782 |
|
|
return (0);
|
| 4783 |
|
|
else if (bits & 0x3)
|
| 4784 |
|
|
return (0);
|
| 4785 |
|
|
else
|
| 4786 |
|
|
return (1);
|
| 4787 |
|
|
}
|
| 4788 |
|
|
|
| 4789 |
|
|
/****************************************************************************/
|
| 4790 |
|
|
/* */
|
| 4791 |
|
|
/* Routine Name: ips_enable_int_copperhead */
|
| 4792 |
|
|
/* */
|
| 4793 |
|
|
/* Routine Description: */
|
| 4794 |
|
|
/* Turn on interrupts */
|
| 4795 |
|
|
/* */
|
| 4796 |
|
|
/****************************************************************************/
|
| 4797 |
|
|
static void
|
| 4798 |
|
|
ips_enable_int_copperhead(ips_ha_t * ha)
|
| 4799 |
|
|
{
|
| 4800 |
|
|
METHOD_TRACE("ips_enable_int_copperhead", 1);
|
| 4801 |
|
|
|
| 4802 |
|
|
outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
|
| 4803 |
|
|
inb(ha->io_addr + IPS_REG_HISR); // Ensure PCI Posting Completes
|
| 4804 |
|
|
}
|
| 4805 |
|
|
|
| 4806 |
|
|
/****************************************************************************/
|
| 4807 |
|
|
/* */
|
| 4808 |
|
|
/* Routine Name: ips_enable_int_copperhead_memio */
|
| 4809 |
|
|
/* */
|
| 4810 |
|
|
/* Routine Description: */
|
| 4811 |
|
|
/* Turn on interrupts */
|
| 4812 |
|
|
/* */
|
| 4813 |
|
|
/****************************************************************************/
|
| 4814 |
|
|
static void
|
| 4815 |
|
|
ips_enable_int_copperhead_memio(ips_ha_t * ha)
|
| 4816 |
|
|
{
|
| 4817 |
|
|
METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
|
| 4818 |
|
|
|
| 4819 |
|
|
writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
|
| 4820 |
|
|
readb(ha->mem_ptr + IPS_REG_HISR); // Ensure PCI Posting Completes
|
| 4821 |
|
|
}
|
| 4822 |
|
|
|
| 4823 |
|
|
/****************************************************************************/
|
| 4824 |
|
|
/* */
|
| 4825 |
|
|
/* Routine Name: ips_enable_int_morpheus */
|
| 4826 |
|
|
/* */
|
| 4827 |
|
|
/* Routine Description: */
|
| 4828 |
|
|
/* Turn on interrupts */
|
| 4829 |
|
|
/* */
|
| 4830 |
|
|
/****************************************************************************/
|
| 4831 |
|
|
static void
|
| 4832 |
|
|
ips_enable_int_morpheus(ips_ha_t * ha)
|
| 4833 |
|
|
{
|
| 4834 |
|
|
uint32_t Oimr;
|
| 4835 |
|
|
|
| 4836 |
|
|
METHOD_TRACE("ips_enable_int_morpheus", 1);
|
| 4837 |
|
|
|
| 4838 |
|
|
Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
|
| 4839 |
|
|
Oimr &= ~0x08;
|
| 4840 |
|
|
writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
|
| 4841 |
|
|
readl(ha->mem_ptr + IPS_REG_I960_OIMR); // Ensure PCI Posting Completes
|
| 4842 |
|
|
}
|
| 4843 |
|
|
|
| 4844 |
|
|
/****************************************************************************/
|
| 4845 |
|
|
/* */
|
| 4846 |
|
|
/* Routine Name: ips_init_copperhead */
|
| 4847 |
|
|
/* */
|
| 4848 |
|
|
/* Routine Description: */
|
| 4849 |
|
|
/* */
|
| 4850 |
|
|
/* Initialize a copperhead controller */
|
| 4851 |
|
|
/* */
|
| 4852 |
|
|
/****************************************************************************/
|
| 4853 |
|
|
static int
|
| 4854 |
|
|
ips_init_copperhead(ips_ha_t * ha)
|
| 4855 |
|
|
{
|
| 4856 |
|
|
uint8_t Isr;
|
| 4857 |
|
|
uint8_t Cbsp;
|
| 4858 |
|
|
uint8_t PostByte[IPS_MAX_POST_BYTES];
|
| 4859 |
|
|
uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
|
| 4860 |
|
|
int i, j;
|
| 4861 |
|
|
|
| 4862 |
|
|
METHOD_TRACE("ips_init_copperhead", 1);
|
| 4863 |
|
|
|
| 4864 |
|
|
for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
|
| 4865 |
|
|
for (j = 0; j < 45; j++) {
|
| 4866 |
|
|
Isr = inb(ha->io_addr + IPS_REG_HISR);
|
| 4867 |
|
|
if (Isr & IPS_BIT_GHI)
|
| 4868 |
|
|
break;
|
| 4869 |
|
|
|
| 4870 |
|
|
/* Delay for 1 Second */
|
| 4871 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 4872 |
|
|
}
|
| 4873 |
|
|
|
| 4874 |
|
|
if (j >= 45)
|
| 4875 |
|
|
/* error occurred */
|
| 4876 |
|
|
return (0);
|
| 4877 |
|
|
|
| 4878 |
|
|
PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
|
| 4879 |
|
|
outb(Isr, ha->io_addr + IPS_REG_HISR);
|
| 4880 |
|
|
}
|
| 4881 |
|
|
|
| 4882 |
|
|
if (PostByte[0] < IPS_GOOD_POST_STATUS) {
|
| 4883 |
|
|
printk(KERN_WARNING
|
| 4884 |
|
|
"(%s%d) reset controller fails (post status %x %x).\n",
|
| 4885 |
|
|
ips_name, ha->host_num, PostByte[0], PostByte[1]);
|
| 4886 |
|
|
|
| 4887 |
|
|
return (0);
|
| 4888 |
|
|
}
|
| 4889 |
|
|
|
| 4890 |
|
|
for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
|
| 4891 |
|
|
for (j = 0; j < 240; j++) {
|
| 4892 |
|
|
Isr = inb(ha->io_addr + IPS_REG_HISR);
|
| 4893 |
|
|
if (Isr & IPS_BIT_GHI)
|
| 4894 |
|
|
break;
|
| 4895 |
|
|
|
| 4896 |
|
|
/* Delay for 1 Second */
|
| 4897 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 4898 |
|
|
}
|
| 4899 |
|
|
|
| 4900 |
|
|
if (j >= 240)
|
| 4901 |
|
|
/* error occurred */
|
| 4902 |
|
|
return (0);
|
| 4903 |
|
|
|
| 4904 |
|
|
ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
|
| 4905 |
|
|
outb(Isr, ha->io_addr + IPS_REG_HISR);
|
| 4906 |
|
|
}
|
| 4907 |
|
|
|
| 4908 |
|
|
for (i = 0; i < 240; i++) {
|
| 4909 |
|
|
Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
|
| 4910 |
|
|
|
| 4911 |
|
|
if ((Cbsp & IPS_BIT_OP) == 0)
|
| 4912 |
|
|
break;
|
| 4913 |
|
|
|
| 4914 |
|
|
/* Delay for 1 Second */
|
| 4915 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 4916 |
|
|
}
|
| 4917 |
|
|
|
| 4918 |
|
|
if (i >= 240)
|
| 4919 |
|
|
/* reset failed */
|
| 4920 |
|
|
return (0);
|
| 4921 |
|
|
|
| 4922 |
|
|
/* setup CCCR */
|
| 4923 |
|
|
outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
|
| 4924 |
|
|
|
| 4925 |
|
|
/* Enable busmastering */
|
| 4926 |
|
|
outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
|
| 4927 |
|
|
|
| 4928 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 4929 |
|
|
/* fix for anaconda64 */
|
| 4930 |
|
|
outl(0, ha->io_addr + IPS_REG_NDAE);
|
| 4931 |
|
|
|
| 4932 |
|
|
/* Enable interrupts */
|
| 4933 |
|
|
outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
|
| 4934 |
|
|
|
| 4935 |
|
|
return (1);
|
| 4936 |
|
|
}
|
| 4937 |
|
|
|
| 4938 |
|
|
/****************************************************************************/
|
| 4939 |
|
|
/* */
|
| 4940 |
|
|
/* Routine Name: ips_init_copperhead_memio */
|
| 4941 |
|
|
/* */
|
| 4942 |
|
|
/* Routine Description: */
|
| 4943 |
|
|
/* */
|
| 4944 |
|
|
/* Initialize a copperhead controller with memory mapped I/O */
|
| 4945 |
|
|
/* */
|
| 4946 |
|
|
/****************************************************************************/
|
| 4947 |
|
|
static int
|
| 4948 |
|
|
ips_init_copperhead_memio(ips_ha_t * ha)
|
| 4949 |
|
|
{
|
| 4950 |
|
|
uint8_t Isr = 0;
|
| 4951 |
|
|
uint8_t Cbsp;
|
| 4952 |
|
|
uint8_t PostByte[IPS_MAX_POST_BYTES];
|
| 4953 |
|
|
uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
|
| 4954 |
|
|
int i, j;
|
| 4955 |
|
|
|
| 4956 |
|
|
METHOD_TRACE("ips_init_copperhead_memio", 1);
|
| 4957 |
|
|
|
| 4958 |
|
|
for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
|
| 4959 |
|
|
for (j = 0; j < 45; j++) {
|
| 4960 |
|
|
Isr = readb(ha->mem_ptr + IPS_REG_HISR);
|
| 4961 |
|
|
if (Isr & IPS_BIT_GHI)
|
| 4962 |
|
|
break;
|
| 4963 |
|
|
|
| 4964 |
|
|
/* Delay for 1 Second */
|
| 4965 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 4966 |
|
|
}
|
| 4967 |
|
|
|
| 4968 |
|
|
if (j >= 45)
|
| 4969 |
|
|
/* error occurred */
|
| 4970 |
|
|
return (0);
|
| 4971 |
|
|
|
| 4972 |
|
|
PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
|
| 4973 |
|
|
writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
|
| 4974 |
|
|
}
|
| 4975 |
|
|
|
| 4976 |
|
|
if (PostByte[0] < IPS_GOOD_POST_STATUS) {
|
| 4977 |
|
|
printk(KERN_WARNING
|
| 4978 |
|
|
"(%s%d) reset controller fails (post status %x %x).\n",
|
| 4979 |
|
|
ips_name, ha->host_num, PostByte[0], PostByte[1]);
|
| 4980 |
|
|
|
| 4981 |
|
|
return (0);
|
| 4982 |
|
|
}
|
| 4983 |
|
|
|
| 4984 |
|
|
for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
|
| 4985 |
|
|
for (j = 0; j < 240; j++) {
|
| 4986 |
|
|
Isr = readb(ha->mem_ptr + IPS_REG_HISR);
|
| 4987 |
|
|
if (Isr & IPS_BIT_GHI)
|
| 4988 |
|
|
break;
|
| 4989 |
|
|
|
| 4990 |
|
|
/* Delay for 1 Second */
|
| 4991 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 4992 |
|
|
}
|
| 4993 |
|
|
|
| 4994 |
|
|
if (j >= 240)
|
| 4995 |
|
|
/* error occurred */
|
| 4996 |
|
|
return (0);
|
| 4997 |
|
|
|
| 4998 |
|
|
ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
|
| 4999 |
|
|
writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
|
| 5000 |
|
|
}
|
| 5001 |
|
|
|
| 5002 |
|
|
for (i = 0; i < 240; i++) {
|
| 5003 |
|
|
Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
|
| 5004 |
|
|
|
| 5005 |
|
|
if ((Cbsp & IPS_BIT_OP) == 0)
|
| 5006 |
|
|
break;
|
| 5007 |
|
|
|
| 5008 |
|
|
/* Delay for 1 Second */
|
| 5009 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5010 |
|
|
}
|
| 5011 |
|
|
|
| 5012 |
|
|
if (i >= 240)
|
| 5013 |
|
|
/* error occurred */
|
| 5014 |
|
|
return (0);
|
| 5015 |
|
|
|
| 5016 |
|
|
/* setup CCCR */
|
| 5017 |
|
|
writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
|
| 5018 |
|
|
|
| 5019 |
|
|
/* Enable busmastering */
|
| 5020 |
|
|
writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
|
| 5021 |
|
|
|
| 5022 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 5023 |
|
|
/* fix for anaconda64 */
|
| 5024 |
|
|
writel(0, ha->mem_ptr + IPS_REG_NDAE);
|
| 5025 |
|
|
|
| 5026 |
|
|
/* Enable interrupts */
|
| 5027 |
|
|
writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
|
| 5028 |
|
|
|
| 5029 |
|
|
/* if we get here then everything went OK */
|
| 5030 |
|
|
return (1);
|
| 5031 |
|
|
}
|
| 5032 |
|
|
|
| 5033 |
|
|
/****************************************************************************/
|
| 5034 |
|
|
/* */
|
| 5035 |
|
|
/* Routine Name: ips_init_morpheus */
|
| 5036 |
|
|
/* */
|
| 5037 |
|
|
/* Routine Description: */
|
| 5038 |
|
|
/* */
|
| 5039 |
|
|
/* Initialize a morpheus controller */
|
| 5040 |
|
|
/* */
|
| 5041 |
|
|
/****************************************************************************/
|
| 5042 |
|
|
static int
|
| 5043 |
|
|
ips_init_morpheus(ips_ha_t * ha)
|
| 5044 |
|
|
{
|
| 5045 |
|
|
uint32_t Post;
|
| 5046 |
|
|
uint32_t Config;
|
| 5047 |
|
|
uint32_t Isr;
|
| 5048 |
|
|
uint32_t Oimr;
|
| 5049 |
|
|
int i;
|
| 5050 |
|
|
|
| 5051 |
|
|
METHOD_TRACE("ips_init_morpheus", 1);
|
| 5052 |
|
|
|
| 5053 |
|
|
/* Wait up to 45 secs for Post */
|
| 5054 |
|
|
for (i = 0; i < 45; i++) {
|
| 5055 |
|
|
Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5056 |
|
|
|
| 5057 |
|
|
if (Isr & IPS_BIT_I960_MSG0I)
|
| 5058 |
|
|
break;
|
| 5059 |
|
|
|
| 5060 |
|
|
/* Delay for 1 Second */
|
| 5061 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5062 |
|
|
}
|
| 5063 |
|
|
|
| 5064 |
|
|
if (i >= 45) {
|
| 5065 |
|
|
/* error occurred */
|
| 5066 |
|
|
printk(KERN_WARNING "(%s%d) timeout waiting for post.\n",
|
| 5067 |
|
|
ips_name, ha->host_num);
|
| 5068 |
|
|
|
| 5069 |
|
|
return (0);
|
| 5070 |
|
|
}
|
| 5071 |
|
|
|
| 5072 |
|
|
Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
|
| 5073 |
|
|
|
| 5074 |
|
|
if (Post == 0x4F00) { /* If Flashing the Battery PIC */
|
| 5075 |
|
|
printk(KERN_WARNING "Flashing Battery PIC, Please wait ...\n");
|
| 5076 |
|
|
|
| 5077 |
|
|
/* Clear the interrupt bit */
|
| 5078 |
|
|
Isr = (uint32_t) IPS_BIT_I960_MSG0I;
|
| 5079 |
|
|
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5080 |
|
|
|
| 5081 |
|
|
for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
|
| 5082 |
|
|
Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
|
| 5083 |
|
|
if (Post != 0x4F00)
|
| 5084 |
|
|
break;
|
| 5085 |
|
|
/* Delay for 1 Second */
|
| 5086 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5087 |
|
|
}
|
| 5088 |
|
|
|
| 5089 |
|
|
if (i >= 120) {
|
| 5090 |
|
|
printk(KERN_WARNING
|
| 5091 |
|
|
"(%s%d) timeout waiting for Battery PIC Flash\n",
|
| 5092 |
|
|
ips_name, ha->host_num);
|
| 5093 |
|
|
return (0);
|
| 5094 |
|
|
}
|
| 5095 |
|
|
|
| 5096 |
|
|
}
|
| 5097 |
|
|
|
| 5098 |
|
|
/* Clear the interrupt bit */
|
| 5099 |
|
|
Isr = (uint32_t) IPS_BIT_I960_MSG0I;
|
| 5100 |
|
|
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5101 |
|
|
|
| 5102 |
|
|
if (Post < (IPS_GOOD_POST_STATUS << 8)) {
|
| 5103 |
|
|
printk(KERN_WARNING
|
| 5104 |
|
|
"(%s%d) reset controller fails (post status %x).\n",
|
| 5105 |
|
|
ips_name, ha->host_num, Post);
|
| 5106 |
|
|
|
| 5107 |
|
|
return (0);
|
| 5108 |
|
|
}
|
| 5109 |
|
|
|
| 5110 |
|
|
/* Wait up to 240 secs for config bytes */
|
| 5111 |
|
|
for (i = 0; i < 240; i++) {
|
| 5112 |
|
|
Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5113 |
|
|
|
| 5114 |
|
|
if (Isr & IPS_BIT_I960_MSG1I)
|
| 5115 |
|
|
break;
|
| 5116 |
|
|
|
| 5117 |
|
|
/* Delay for 1 Second */
|
| 5118 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5119 |
|
|
}
|
| 5120 |
|
|
|
| 5121 |
|
|
if (i >= 240) {
|
| 5122 |
|
|
/* error occurred */
|
| 5123 |
|
|
printk(KERN_WARNING "(%s%d) timeout waiting for config.\n",
|
| 5124 |
|
|
ips_name, ha->host_num);
|
| 5125 |
|
|
|
| 5126 |
|
|
return (0);
|
| 5127 |
|
|
}
|
| 5128 |
|
|
|
| 5129 |
|
|
Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
|
| 5130 |
|
|
|
| 5131 |
|
|
/* Clear interrupt bit */
|
| 5132 |
|
|
Isr = (uint32_t) IPS_BIT_I960_MSG1I;
|
| 5133 |
|
|
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5134 |
|
|
|
| 5135 |
|
|
/* Turn on the interrupts */
|
| 5136 |
|
|
Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
|
| 5137 |
|
|
Oimr &= ~0x8;
|
| 5138 |
|
|
writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
|
| 5139 |
|
|
|
| 5140 |
|
|
/* if we get here then everything went OK */
|
| 5141 |
|
|
|
| 5142 |
|
|
/* Since we did a RESET, an EraseStripeLock may be needed */
|
| 5143 |
|
|
if (Post == 0xEF10) {
|
| 5144 |
|
|
if ((Config == 0x000F) || (Config == 0x0009))
|
| 5145 |
|
|
ha->requires_esl = 1;
|
| 5146 |
|
|
}
|
| 5147 |
|
|
|
| 5148 |
|
|
return (1);
|
| 5149 |
|
|
}
|
| 5150 |
|
|
|
| 5151 |
|
|
/****************************************************************************/
|
| 5152 |
|
|
/* */
|
| 5153 |
|
|
/* Routine Name: ips_reset_copperhead */
|
| 5154 |
|
|
/* */
|
| 5155 |
|
|
/* Routine Description: */
|
| 5156 |
|
|
/* */
|
| 5157 |
|
|
/* Reset the controller */
|
| 5158 |
|
|
/* */
|
| 5159 |
|
|
/****************************************************************************/
|
| 5160 |
|
|
static int
|
| 5161 |
|
|
ips_reset_copperhead(ips_ha_t * ha)
|
| 5162 |
|
|
{
|
| 5163 |
|
|
int reset_counter;
|
| 5164 |
|
|
|
| 5165 |
|
|
METHOD_TRACE("ips_reset_copperhead", 1);
|
| 5166 |
|
|
|
| 5167 |
|
|
DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
|
| 5168 |
|
|
ips_name, ha->host_num, ha->io_addr, ha->irq);
|
| 5169 |
|
|
|
| 5170 |
|
|
reset_counter = 0;
|
| 5171 |
|
|
|
| 5172 |
|
|
while (reset_counter < 2) {
|
| 5173 |
|
|
reset_counter++;
|
| 5174 |
|
|
|
| 5175 |
|
|
outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
|
| 5176 |
|
|
|
| 5177 |
|
|
/* Delay for 1 Second */
|
| 5178 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5179 |
|
|
|
| 5180 |
|
|
outb(0, ha->io_addr + IPS_REG_SCPR);
|
| 5181 |
|
|
|
| 5182 |
|
|
/* Delay for 1 Second */
|
| 5183 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5184 |
|
|
|
| 5185 |
|
|
if ((*ha->func.init) (ha))
|
| 5186 |
|
|
break;
|
| 5187 |
|
|
else if (reset_counter >= 2) {
|
| 5188 |
|
|
|
| 5189 |
|
|
return (0);
|
| 5190 |
|
|
}
|
| 5191 |
|
|
}
|
| 5192 |
|
|
|
| 5193 |
|
|
return (1);
|
| 5194 |
|
|
}
|
| 5195 |
|
|
|
| 5196 |
|
|
/****************************************************************************/
|
| 5197 |
|
|
/* */
|
| 5198 |
|
|
/* Routine Name: ips_reset_copperhead_memio */
|
| 5199 |
|
|
/* */
|
| 5200 |
|
|
/* Routine Description: */
|
| 5201 |
|
|
/* */
|
| 5202 |
|
|
/* Reset the controller */
|
| 5203 |
|
|
/* */
|
| 5204 |
|
|
/****************************************************************************/
|
| 5205 |
|
|
static int
|
| 5206 |
|
|
ips_reset_copperhead_memio(ips_ha_t * ha)
|
| 5207 |
|
|
{
|
| 5208 |
|
|
int reset_counter;
|
| 5209 |
|
|
|
| 5210 |
|
|
METHOD_TRACE("ips_reset_copperhead_memio", 1);
|
| 5211 |
|
|
|
| 5212 |
|
|
DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
|
| 5213 |
|
|
ips_name, ha->host_num, ha->mem_addr, ha->irq);
|
| 5214 |
|
|
|
| 5215 |
|
|
reset_counter = 0;
|
| 5216 |
|
|
|
| 5217 |
|
|
while (reset_counter < 2) {
|
| 5218 |
|
|
reset_counter++;
|
| 5219 |
|
|
|
| 5220 |
|
|
writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
|
| 5221 |
|
|
|
| 5222 |
|
|
/* Delay for 1 Second */
|
| 5223 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5224 |
|
|
|
| 5225 |
|
|
writeb(0, ha->mem_ptr + IPS_REG_SCPR);
|
| 5226 |
|
|
|
| 5227 |
|
|
/* Delay for 1 Second */
|
| 5228 |
|
|
MDELAY(IPS_ONE_SEC);
|
| 5229 |
|
|
|
| 5230 |
|
|
if ((*ha->func.init) (ha))
|
| 5231 |
|
|
break;
|
| 5232 |
|
|
else if (reset_counter >= 2) {
|
| 5233 |
|
|
|
| 5234 |
|
|
return (0);
|
| 5235 |
|
|
}
|
| 5236 |
|
|
}
|
| 5237 |
|
|
|
| 5238 |
|
|
return (1);
|
| 5239 |
|
|
}
|
| 5240 |
|
|
|
| 5241 |
|
|
/****************************************************************************/
|
| 5242 |
|
|
/* */
|
| 5243 |
|
|
/* Routine Name: ips_reset_morpheus */
|
| 5244 |
|
|
/* */
|
| 5245 |
|
|
/* Routine Description: */
|
| 5246 |
|
|
/* */
|
| 5247 |
|
|
/* Reset the controller */
|
| 5248 |
|
|
/* */
|
| 5249 |
|
|
/****************************************************************************/
|
| 5250 |
|
|
static int
|
| 5251 |
|
|
ips_reset_morpheus(ips_ha_t * ha)
|
| 5252 |
|
|
{
|
| 5253 |
|
|
int reset_counter;
|
| 5254 |
|
|
uint8_t junk;
|
| 5255 |
|
|
|
| 5256 |
|
|
METHOD_TRACE("ips_reset_morpheus", 1);
|
| 5257 |
|
|
|
| 5258 |
|
|
DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
|
| 5259 |
|
|
ips_name, ha->host_num, ha->mem_addr, ha->irq);
|
| 5260 |
|
|
|
| 5261 |
|
|
reset_counter = 0;
|
| 5262 |
|
|
|
| 5263 |
|
|
while (reset_counter < 2) {
|
| 5264 |
|
|
reset_counter++;
|
| 5265 |
|
|
|
| 5266 |
|
|
writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
|
| 5267 |
|
|
|
| 5268 |
|
|
/* Delay for 5 Seconds */
|
| 5269 |
|
|
MDELAY(5 * IPS_ONE_SEC);
|
| 5270 |
|
|
|
| 5271 |
|
|
/* Do a PCI config read to wait for adapter */
|
| 5272 |
|
|
pci_read_config_byte(ha->pcidev, 4, &junk);
|
| 5273 |
|
|
|
| 5274 |
|
|
if ((*ha->func.init) (ha))
|
| 5275 |
|
|
break;
|
| 5276 |
|
|
else if (reset_counter >= 2) {
|
| 5277 |
|
|
|
| 5278 |
|
|
return (0);
|
| 5279 |
|
|
}
|
| 5280 |
|
|
}
|
| 5281 |
|
|
|
| 5282 |
|
|
return (1);
|
| 5283 |
|
|
}
|
| 5284 |
|
|
|
| 5285 |
|
|
/****************************************************************************/
|
| 5286 |
|
|
/* */
|
| 5287 |
|
|
/* Routine Name: ips_statinit */
|
| 5288 |
|
|
/* */
|
| 5289 |
|
|
/* Routine Description: */
|
| 5290 |
|
|
/* */
|
| 5291 |
|
|
/* Initialize the status queues on the controller */
|
| 5292 |
|
|
/* */
|
| 5293 |
|
|
/****************************************************************************/
|
| 5294 |
|
|
static void
|
| 5295 |
|
|
ips_statinit(ips_ha_t * ha)
|
| 5296 |
|
|
{
|
| 5297 |
|
|
uint32_t phys_status_start;
|
| 5298 |
|
|
|
| 5299 |
|
|
METHOD_TRACE("ips_statinit", 1);
|
| 5300 |
|
|
|
| 5301 |
|
|
ha->adapt->p_status_start = ha->adapt->status;
|
| 5302 |
|
|
ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
|
| 5303 |
|
|
ha->adapt->p_status_tail = ha->adapt->status;
|
| 5304 |
|
|
|
| 5305 |
|
|
phys_status_start = ha->adapt->hw_status_start;
|
| 5306 |
|
|
outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
|
| 5307 |
|
|
outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
|
| 5308 |
|
|
ha->io_addr + IPS_REG_SQER);
|
| 5309 |
|
|
outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
|
| 5310 |
|
|
ha->io_addr + IPS_REG_SQHR);
|
| 5311 |
|
|
outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
|
| 5312 |
|
|
|
| 5313 |
|
|
ha->adapt->hw_status_tail = phys_status_start;
|
| 5314 |
|
|
}
|
| 5315 |
|
|
|
| 5316 |
|
|
/****************************************************************************/
|
| 5317 |
|
|
/* */
|
| 5318 |
|
|
/* Routine Name: ips_statinit_memio */
|
| 5319 |
|
|
/* */
|
| 5320 |
|
|
/* Routine Description: */
|
| 5321 |
|
|
/* */
|
| 5322 |
|
|
/* Initialize the status queues on the controller */
|
| 5323 |
|
|
/* */
|
| 5324 |
|
|
/****************************************************************************/
|
| 5325 |
|
|
static void
|
| 5326 |
|
|
ips_statinit_memio(ips_ha_t * ha)
|
| 5327 |
|
|
{
|
| 5328 |
|
|
uint32_t phys_status_start;
|
| 5329 |
|
|
|
| 5330 |
|
|
METHOD_TRACE("ips_statinit_memio", 1);
|
| 5331 |
|
|
|
| 5332 |
|
|
ha->adapt->p_status_start = ha->adapt->status;
|
| 5333 |
|
|
ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
|
| 5334 |
|
|
ha->adapt->p_status_tail = ha->adapt->status;
|
| 5335 |
|
|
|
| 5336 |
|
|
phys_status_start = ha->adapt->hw_status_start;
|
| 5337 |
|
|
writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
|
| 5338 |
|
|
writel(phys_status_start + IPS_STATUS_Q_SIZE,
|
| 5339 |
|
|
ha->mem_ptr + IPS_REG_SQER);
|
| 5340 |
|
|
writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
|
| 5341 |
|
|
writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
|
| 5342 |
|
|
|
| 5343 |
|
|
ha->adapt->hw_status_tail = phys_status_start;
|
| 5344 |
|
|
}
|
| 5345 |
|
|
|
| 5346 |
|
|
/****************************************************************************/
|
| 5347 |
|
|
/* */
|
| 5348 |
|
|
/* Routine Name: ips_statupd_copperhead */
|
| 5349 |
|
|
/* */
|
| 5350 |
|
|
/* Routine Description: */
|
| 5351 |
|
|
/* */
|
| 5352 |
|
|
/* Remove an element from the status queue */
|
| 5353 |
|
|
/* */
|
| 5354 |
|
|
/****************************************************************************/
|
| 5355 |
|
|
static uint32_t
|
| 5356 |
|
|
ips_statupd_copperhead(ips_ha_t * ha)
|
| 5357 |
|
|
{
|
| 5358 |
|
|
METHOD_TRACE("ips_statupd_copperhead", 1);
|
| 5359 |
|
|
|
| 5360 |
|
|
if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
|
| 5361 |
|
|
ha->adapt->p_status_tail++;
|
| 5362 |
|
|
ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
|
| 5363 |
|
|
} else {
|
| 5364 |
|
|
ha->adapt->p_status_tail = ha->adapt->p_status_start;
|
| 5365 |
|
|
ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
|
| 5366 |
|
|
}
|
| 5367 |
|
|
|
| 5368 |
|
|
outl(cpu_to_le32(ha->adapt->hw_status_tail),
|
| 5369 |
|
|
ha->io_addr + IPS_REG_SQTR);
|
| 5370 |
|
|
|
| 5371 |
|
|
return (ha->adapt->p_status_tail->value);
|
| 5372 |
|
|
}
|
| 5373 |
|
|
|
| 5374 |
|
|
/****************************************************************************/
|
| 5375 |
|
|
/* */
|
| 5376 |
|
|
/* Routine Name: ips_statupd_copperhead_memio */
|
| 5377 |
|
|
/* */
|
| 5378 |
|
|
/* Routine Description: */
|
| 5379 |
|
|
/* */
|
| 5380 |
|
|
/* Remove an element from the status queue */
|
| 5381 |
|
|
/* */
|
| 5382 |
|
|
/****************************************************************************/
|
| 5383 |
|
|
static uint32_t
|
| 5384 |
|
|
ips_statupd_copperhead_memio(ips_ha_t * ha)
|
| 5385 |
|
|
{
|
| 5386 |
|
|
METHOD_TRACE("ips_statupd_copperhead_memio", 1);
|
| 5387 |
|
|
|
| 5388 |
|
|
if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
|
| 5389 |
|
|
ha->adapt->p_status_tail++;
|
| 5390 |
|
|
ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
|
| 5391 |
|
|
} else {
|
| 5392 |
|
|
ha->adapt->p_status_tail = ha->adapt->p_status_start;
|
| 5393 |
|
|
ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
|
| 5394 |
|
|
}
|
| 5395 |
|
|
|
| 5396 |
|
|
writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
|
| 5397 |
|
|
|
| 5398 |
|
|
return (ha->adapt->p_status_tail->value);
|
| 5399 |
|
|
}
|
| 5400 |
|
|
|
| 5401 |
|
|
/****************************************************************************/
|
| 5402 |
|
|
/* */
|
| 5403 |
|
|
/* Routine Name: ips_statupd_morpheus */
|
| 5404 |
|
|
/* */
|
| 5405 |
|
|
/* Routine Description: */
|
| 5406 |
|
|
/* */
|
| 5407 |
|
|
/* Remove an element from the status queue */
|
| 5408 |
|
|
/* */
|
| 5409 |
|
|
/****************************************************************************/
|
| 5410 |
|
|
static uint32_t
|
| 5411 |
|
|
ips_statupd_morpheus(ips_ha_t * ha)
|
| 5412 |
|
|
{
|
| 5413 |
|
|
uint32_t val;
|
| 5414 |
|
|
|
| 5415 |
|
|
METHOD_TRACE("ips_statupd_morpheus", 1);
|
| 5416 |
|
|
|
| 5417 |
|
|
val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
|
| 5418 |
|
|
|
| 5419 |
|
|
return (val);
|
| 5420 |
|
|
}
|
| 5421 |
|
|
|
| 5422 |
|
|
/****************************************************************************/
|
| 5423 |
|
|
/* */
|
| 5424 |
|
|
/* Routine Name: ips_issue_copperhead */
|
| 5425 |
|
|
/* */
|
| 5426 |
|
|
/* Routine Description: */
|
| 5427 |
|
|
/* */
|
| 5428 |
|
|
/* Send a command down to the controller */
|
| 5429 |
|
|
/* */
|
| 5430 |
|
|
/****************************************************************************/
|
| 5431 |
|
|
static int
|
| 5432 |
|
|
ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
|
| 5433 |
|
|
{
|
| 5434 |
|
|
uint32_t TimeOut;
|
| 5435 |
|
|
uint32_t val;
|
| 5436 |
|
|
|
| 5437 |
|
|
METHOD_TRACE("ips_issue_copperhead", 1);
|
| 5438 |
|
|
|
| 5439 |
|
|
if (scb->scsi_cmd) {
|
| 5440 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
|
| 5441 |
|
|
ips_name,
|
| 5442 |
|
|
ha->host_num,
|
| 5443 |
|
|
scb->cdb[0],
|
| 5444 |
|
|
scb->cmd.basic_io.command_id,
|
| 5445 |
|
|
scb->bus, scb->target_id, scb->lun);
|
| 5446 |
|
|
} else {
|
| 5447 |
|
|
DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
|
| 5448 |
|
|
ips_name, ha->host_num, scb->cmd.basic_io.command_id);
|
| 5449 |
|
|
}
|
| 5450 |
|
|
|
| 5451 |
|
|
TimeOut = 0;
|
| 5452 |
|
|
|
| 5453 |
|
|
while ((val = le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) &
|
| 5454 |
|
|
IPS_BIT_SEM) {
|
| 5455 |
|
|
udelay(1000);
|
| 5456 |
|
|
|
| 5457 |
|
|
if (++TimeOut >= IPS_SEM_TIMEOUT) {
|
| 5458 |
|
|
if (!(val & IPS_BIT_START_STOP))
|
| 5459 |
|
|
break;
|
| 5460 |
|
|
|
| 5461 |
|
|
printk(KERN_WARNING "(%s%d) ips_issue val [0x%x].\n",
|
| 5462 |
|
|
ips_name, ha->host_num, val);
|
| 5463 |
|
|
printk(KERN_WARNING
|
| 5464 |
|
|
"(%s%d) ips_issue semaphore chk timeout.\n",
|
| 5465 |
|
|
ips_name, ha->host_num);
|
| 5466 |
|
|
|
| 5467 |
|
|
return (IPS_FAILURE);
|
| 5468 |
|
|
} /* end if */
|
| 5469 |
|
|
} /* end while */
|
| 5470 |
|
|
|
| 5471 |
|
|
outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
|
| 5472 |
|
|
outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
|
| 5473 |
|
|
|
| 5474 |
|
|
return (IPS_SUCCESS);
|
| 5475 |
|
|
}
|
| 5476 |
|
|
|
| 5477 |
|
|
/****************************************************************************/
|
| 5478 |
|
|
/* */
|
| 5479 |
|
|
/* Routine Name: ips_issue_copperhead_memio */
|
| 5480 |
|
|
/* */
|
| 5481 |
|
|
/* Routine Description: */
|
| 5482 |
|
|
/* */
|
| 5483 |
|
|
/* Send a command down to the controller */
|
| 5484 |
|
|
/* */
|
| 5485 |
|
|
/****************************************************************************/
|
| 5486 |
|
|
static int
|
| 5487 |
|
|
ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
|
| 5488 |
|
|
{
|
| 5489 |
|
|
uint32_t TimeOut;
|
| 5490 |
|
|
uint32_t val;
|
| 5491 |
|
|
|
| 5492 |
|
|
METHOD_TRACE("ips_issue_copperhead_memio", 1);
|
| 5493 |
|
|
|
| 5494 |
|
|
if (scb->scsi_cmd) {
|
| 5495 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
|
| 5496 |
|
|
ips_name,
|
| 5497 |
|
|
ha->host_num,
|
| 5498 |
|
|
scb->cdb[0],
|
| 5499 |
|
|
scb->cmd.basic_io.command_id,
|
| 5500 |
|
|
scb->bus, scb->target_id, scb->lun);
|
| 5501 |
|
|
} else {
|
| 5502 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
|
| 5503 |
|
|
ips_name, ha->host_num, scb->cmd.basic_io.command_id);
|
| 5504 |
|
|
}
|
| 5505 |
|
|
|
| 5506 |
|
|
TimeOut = 0;
|
| 5507 |
|
|
|
| 5508 |
|
|
while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
|
| 5509 |
|
|
udelay(1000);
|
| 5510 |
|
|
|
| 5511 |
|
|
if (++TimeOut >= IPS_SEM_TIMEOUT) {
|
| 5512 |
|
|
if (!(val & IPS_BIT_START_STOP))
|
| 5513 |
|
|
break;
|
| 5514 |
|
|
|
| 5515 |
|
|
printk(KERN_WARNING "(%s%d) ips_issue val [0x%x].\n",
|
| 5516 |
|
|
ips_name, ha->host_num, val);
|
| 5517 |
|
|
printk(KERN_WARNING
|
| 5518 |
|
|
"(%s%d) ips_issue semaphore chk timeout.\n",
|
| 5519 |
|
|
ips_name, ha->host_num);
|
| 5520 |
|
|
|
| 5521 |
|
|
return (IPS_FAILURE);
|
| 5522 |
|
|
} /* end if */
|
| 5523 |
|
|
} /* end while */
|
| 5524 |
|
|
|
| 5525 |
|
|
writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
|
| 5526 |
|
|
writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
|
| 5527 |
|
|
|
| 5528 |
|
|
return (IPS_SUCCESS);
|
| 5529 |
|
|
}
|
| 5530 |
|
|
|
| 5531 |
|
|
/****************************************************************************/
|
| 5532 |
|
|
/* */
|
| 5533 |
|
|
/* Routine Name: ips_issue_i2o */
|
| 5534 |
|
|
/* */
|
| 5535 |
|
|
/* Routine Description: */
|
| 5536 |
|
|
/* */
|
| 5537 |
|
|
/* Send a command down to the controller */
|
| 5538 |
|
|
/* */
|
| 5539 |
|
|
/****************************************************************************/
|
| 5540 |
|
|
static int
|
| 5541 |
|
|
ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
|
| 5542 |
|
|
{
|
| 5543 |
|
|
|
| 5544 |
|
|
METHOD_TRACE("ips_issue_i2o", 1);
|
| 5545 |
|
|
|
| 5546 |
|
|
if (scb->scsi_cmd) {
|
| 5547 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
|
| 5548 |
|
|
ips_name,
|
| 5549 |
|
|
ha->host_num,
|
| 5550 |
|
|
scb->cdb[0],
|
| 5551 |
|
|
scb->cmd.basic_io.command_id,
|
| 5552 |
|
|
scb->bus, scb->target_id, scb->lun);
|
| 5553 |
|
|
} else {
|
| 5554 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
|
| 5555 |
|
|
ips_name, ha->host_num, scb->cmd.basic_io.command_id);
|
| 5556 |
|
|
}
|
| 5557 |
|
|
|
| 5558 |
|
|
outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
|
| 5559 |
|
|
|
| 5560 |
|
|
return (IPS_SUCCESS);
|
| 5561 |
|
|
}
|
| 5562 |
|
|
|
| 5563 |
|
|
/****************************************************************************/
|
| 5564 |
|
|
/* */
|
| 5565 |
|
|
/* Routine Name: ips_issue_i2o_memio */
|
| 5566 |
|
|
/* */
|
| 5567 |
|
|
/* Routine Description: */
|
| 5568 |
|
|
/* */
|
| 5569 |
|
|
/* Send a command down to the controller */
|
| 5570 |
|
|
/* */
|
| 5571 |
|
|
/****************************************************************************/
|
| 5572 |
|
|
static int
|
| 5573 |
|
|
ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
|
| 5574 |
|
|
{
|
| 5575 |
|
|
|
| 5576 |
|
|
METHOD_TRACE("ips_issue_i2o_memio", 1);
|
| 5577 |
|
|
|
| 5578 |
|
|
if (scb->scsi_cmd) {
|
| 5579 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
|
| 5580 |
|
|
ips_name,
|
| 5581 |
|
|
ha->host_num,
|
| 5582 |
|
|
scb->cdb[0],
|
| 5583 |
|
|
scb->cmd.basic_io.command_id,
|
| 5584 |
|
|
scb->bus, scb->target_id, scb->lun);
|
| 5585 |
|
|
} else {
|
| 5586 |
|
|
DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
|
| 5587 |
|
|
ips_name, ha->host_num, scb->cmd.basic_io.command_id);
|
| 5588 |
|
|
}
|
| 5589 |
|
|
|
| 5590 |
|
|
writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
|
| 5591 |
|
|
|
| 5592 |
|
|
return (IPS_SUCCESS);
|
| 5593 |
|
|
}
|
| 5594 |
|
|
|
| 5595 |
|
|
/****************************************************************************/
|
| 5596 |
|
|
/* */
|
| 5597 |
|
|
/* Routine Name: ips_isintr_copperhead */
|
| 5598 |
|
|
/* */
|
| 5599 |
|
|
/* Routine Description: */
|
| 5600 |
|
|
/* */
|
| 5601 |
|
|
/* Test to see if an interrupt is for us */
|
| 5602 |
|
|
/* */
|
| 5603 |
|
|
/****************************************************************************/
|
| 5604 |
|
|
static int
|
| 5605 |
|
|
ips_isintr_copperhead(ips_ha_t * ha)
|
| 5606 |
|
|
{
|
| 5607 |
|
|
uint8_t Isr;
|
| 5608 |
|
|
|
| 5609 |
|
|
METHOD_TRACE("ips_isintr_copperhead", 2);
|
| 5610 |
|
|
|
| 5611 |
|
|
Isr = inb(ha->io_addr + IPS_REG_HISR);
|
| 5612 |
|
|
|
| 5613 |
|
|
if (Isr == 0xFF)
|
| 5614 |
|
|
/* ?!?! Nothing really there */
|
| 5615 |
|
|
return (0);
|
| 5616 |
|
|
|
| 5617 |
|
|
if (Isr & IPS_BIT_SCE)
|
| 5618 |
|
|
return (1);
|
| 5619 |
|
|
else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
|
| 5620 |
|
|
/* status queue overflow or GHI */
|
| 5621 |
|
|
/* just clear the interrupt */
|
| 5622 |
|
|
outb(Isr, ha->io_addr + IPS_REG_HISR);
|
| 5623 |
|
|
}
|
| 5624 |
|
|
|
| 5625 |
|
|
return (0);
|
| 5626 |
|
|
}
|
| 5627 |
|
|
|
| 5628 |
|
|
/****************************************************************************/
|
| 5629 |
|
|
/* */
|
| 5630 |
|
|
/* Routine Name: ips_isintr_copperhead_memio */
|
| 5631 |
|
|
/* */
|
| 5632 |
|
|
/* Routine Description: */
|
| 5633 |
|
|
/* */
|
| 5634 |
|
|
/* Test to see if an interrupt is for us */
|
| 5635 |
|
|
/* */
|
| 5636 |
|
|
/****************************************************************************/
|
| 5637 |
|
|
static int
|
| 5638 |
|
|
ips_isintr_copperhead_memio(ips_ha_t * ha)
|
| 5639 |
|
|
{
|
| 5640 |
|
|
uint8_t Isr;
|
| 5641 |
|
|
|
| 5642 |
|
|
METHOD_TRACE("ips_isintr_memio", 2);
|
| 5643 |
|
|
|
| 5644 |
|
|
Isr = readb(ha->mem_ptr + IPS_REG_HISR);
|
| 5645 |
|
|
|
| 5646 |
|
|
if (Isr == 0xFF)
|
| 5647 |
|
|
/* ?!?! Nothing really there */
|
| 5648 |
|
|
return (0);
|
| 5649 |
|
|
|
| 5650 |
|
|
if (Isr & IPS_BIT_SCE)
|
| 5651 |
|
|
return (1);
|
| 5652 |
|
|
else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
|
| 5653 |
|
|
/* status queue overflow or GHI */
|
| 5654 |
|
|
/* just clear the interrupt */
|
| 5655 |
|
|
writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
|
| 5656 |
|
|
}
|
| 5657 |
|
|
|
| 5658 |
|
|
return (0);
|
| 5659 |
|
|
}
|
| 5660 |
|
|
|
| 5661 |
|
|
/****************************************************************************/
|
| 5662 |
|
|
/* */
|
| 5663 |
|
|
/* Routine Name: ips_isintr_morpheus */
|
| 5664 |
|
|
/* */
|
| 5665 |
|
|
/* Routine Description: */
|
| 5666 |
|
|
/* */
|
| 5667 |
|
|
/* Test to see if an interrupt is for us */
|
| 5668 |
|
|
/* */
|
| 5669 |
|
|
/****************************************************************************/
|
| 5670 |
|
|
static int
|
| 5671 |
|
|
ips_isintr_morpheus(ips_ha_t * ha)
|
| 5672 |
|
|
{
|
| 5673 |
|
|
uint32_t Isr;
|
| 5674 |
|
|
|
| 5675 |
|
|
METHOD_TRACE("ips_isintr_morpheus", 2);
|
| 5676 |
|
|
|
| 5677 |
|
|
Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
|
| 5678 |
|
|
|
| 5679 |
|
|
if (Isr & IPS_BIT_I2O_OPQI)
|
| 5680 |
|
|
return (1);
|
| 5681 |
|
|
else
|
| 5682 |
|
|
return (0);
|
| 5683 |
|
|
}
|
| 5684 |
|
|
|
| 5685 |
|
|
/****************************************************************************/
|
| 5686 |
|
|
/* */
|
| 5687 |
|
|
/* Routine Name: ips_wait */
|
| 5688 |
|
|
/* */
|
| 5689 |
|
|
/* Routine Description: */
|
| 5690 |
|
|
/* */
|
| 5691 |
|
|
/* Wait for a command to complete */
|
| 5692 |
|
|
/* */
|
| 5693 |
|
|
/****************************************************************************/
|
| 5694 |
|
|
static int
|
| 5695 |
|
|
ips_wait(ips_ha_t * ha, int time, int intr)
|
| 5696 |
|
|
{
|
| 5697 |
|
|
int ret;
|
| 5698 |
|
|
int done;
|
| 5699 |
|
|
|
| 5700 |
|
|
METHOD_TRACE("ips_wait", 1);
|
| 5701 |
|
|
|
| 5702 |
|
|
ret = IPS_FAILURE;
|
| 5703 |
|
|
done = FALSE;
|
| 5704 |
|
|
|
| 5705 |
|
|
time *= IPS_ONE_SEC; /* convert seconds */
|
| 5706 |
|
|
|
| 5707 |
|
|
while ((time > 0) && (!done)) {
|
| 5708 |
|
|
if (intr == IPS_INTR_ON) {
|
| 5709 |
|
|
if (ha->waitflag == FALSE) {
|
| 5710 |
|
|
ret = IPS_SUCCESS;
|
| 5711 |
|
|
done = TRUE;
|
| 5712 |
|
|
break;
|
| 5713 |
|
|
}
|
| 5714 |
|
|
} else if (intr == IPS_INTR_IORL) {
|
| 5715 |
|
|
if (ha->waitflag == FALSE) {
|
| 5716 |
|
|
/*
|
| 5717 |
|
|
* controller generated an interrupt to
|
| 5718 |
|
|
* acknowledge completion of the command
|
| 5719 |
|
|
* and ips_intr() has serviced the interrupt.
|
| 5720 |
|
|
*/
|
| 5721 |
|
|
ret = IPS_SUCCESS;
|
| 5722 |
|
|
done = TRUE;
|
| 5723 |
|
|
break;
|
| 5724 |
|
|
}
|
| 5725 |
|
|
|
| 5726 |
|
|
/*
|
| 5727 |
|
|
* NOTE: we already have the io_request_lock so
|
| 5728 |
|
|
* even if we get an interrupt it won't get serviced
|
| 5729 |
|
|
* until after we finish.
|
| 5730 |
|
|
*/
|
| 5731 |
|
|
|
| 5732 |
|
|
(*ha->func.intr) (ha);
|
| 5733 |
|
|
}
|
| 5734 |
|
|
|
| 5735 |
|
|
/* This looks like a very evil loop, but it only does this during start-up */
|
| 5736 |
|
|
udelay(1000);
|
| 5737 |
|
|
time--;
|
| 5738 |
|
|
}
|
| 5739 |
|
|
|
| 5740 |
|
|
return (ret);
|
| 5741 |
|
|
}
|
| 5742 |
|
|
|
| 5743 |
|
|
/****************************************************************************/
|
| 5744 |
|
|
/* */
|
| 5745 |
|
|
/* Routine Name: ips_write_driver_status */
|
| 5746 |
|
|
/* */
|
| 5747 |
|
|
/* Routine Description: */
|
| 5748 |
|
|
/* */
|
| 5749 |
|
|
/* Write OS/Driver version to Page 5 of the nvram on the controller */
|
| 5750 |
|
|
/* */
|
| 5751 |
|
|
/****************************************************************************/
|
| 5752 |
|
|
static int
|
| 5753 |
|
|
ips_write_driver_status(ips_ha_t * ha, int intr)
|
| 5754 |
|
|
{
|
| 5755 |
|
|
METHOD_TRACE("ips_write_driver_status", 1);
|
| 5756 |
|
|
|
| 5757 |
|
|
if (!ips_readwrite_page5(ha, FALSE, intr)) {
|
| 5758 |
|
|
printk(KERN_WARNING "(%s%d) unable to read NVRAM page 5.\n",
|
| 5759 |
|
|
ips_name, ha->host_num);
|
| 5760 |
|
|
|
| 5761 |
|
|
return (0);
|
| 5762 |
|
|
}
|
| 5763 |
|
|
|
| 5764 |
|
|
/* check to make sure the page has a valid */
|
| 5765 |
|
|
/* signature */
|
| 5766 |
|
|
if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
|
| 5767 |
|
|
DEBUG_VAR(1,
|
| 5768 |
|
|
"(%s%d) NVRAM page 5 has an invalid signature: %X.",
|
| 5769 |
|
|
ips_name, ha->host_num, ha->nvram->signature);
|
| 5770 |
|
|
ha->nvram->signature = IPS_NVRAM_P5_SIG;
|
| 5771 |
|
|
}
|
| 5772 |
|
|
|
| 5773 |
|
|
DEBUG_VAR(2,
|
| 5774 |
|
|
"(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
|
| 5775 |
|
|
ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
|
| 5776 |
|
|
ha->nvram->adapter_slot, ha->nvram->bios_high[0],
|
| 5777 |
|
|
ha->nvram->bios_high[1], ha->nvram->bios_high[2],
|
| 5778 |
|
|
ha->nvram->bios_high[3], ha->nvram->bios_low[0],
|
| 5779 |
|
|
ha->nvram->bios_low[1], ha->nvram->bios_low[2],
|
| 5780 |
|
|
ha->nvram->bios_low[3]);
|
| 5781 |
|
|
|
| 5782 |
|
|
ips_get_bios_version(ha, intr);
|
| 5783 |
|
|
|
| 5784 |
|
|
/* change values (as needed) */
|
| 5785 |
|
|
ha->nvram->operating_system = IPS_OS_LINUX;
|
| 5786 |
|
|
ha->nvram->adapter_type = ha->ad_type;
|
| 5787 |
|
|
strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
|
| 5788 |
|
|
strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
|
| 5789 |
|
|
strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
|
| 5790 |
|
|
strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
|
| 5791 |
|
|
|
| 5792 |
|
|
ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
|
| 5793 |
|
|
|
| 5794 |
|
|
/* now update the page */
|
| 5795 |
|
|
if (!ips_readwrite_page5(ha, TRUE, intr)) {
|
| 5796 |
|
|
printk(KERN_WARNING "(%s%d) unable to write NVRAM page 5.\n",
|
| 5797 |
|
|
ips_name, ha->host_num);
|
| 5798 |
|
|
|
| 5799 |
|
|
return (0);
|
| 5800 |
|
|
}
|
| 5801 |
|
|
|
| 5802 |
|
|
/* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
|
| 5803 |
|
|
ha->slot_num = ha->nvram->adapter_slot;
|
| 5804 |
|
|
|
| 5805 |
|
|
return (1);
|
| 5806 |
|
|
}
|
| 5807 |
|
|
|
| 5808 |
|
|
/****************************************************************************/
|
| 5809 |
|
|
/* */
|
| 5810 |
|
|
/* Routine Name: ips_read_adapter_status */
|
| 5811 |
|
|
/* */
|
| 5812 |
|
|
/* Routine Description: */
|
| 5813 |
|
|
/* */
|
| 5814 |
|
|
/* Do an Inquiry command to the adapter */
|
| 5815 |
|
|
/* */
|
| 5816 |
|
|
/****************************************************************************/
|
| 5817 |
|
|
static int
|
| 5818 |
|
|
ips_read_adapter_status(ips_ha_t * ha, int intr)
|
| 5819 |
|
|
{
|
| 5820 |
|
|
ips_scb_t *scb;
|
| 5821 |
|
|
int ret;
|
| 5822 |
|
|
|
| 5823 |
|
|
METHOD_TRACE("ips_read_adapter_status", 1);
|
| 5824 |
|
|
|
| 5825 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 5826 |
|
|
|
| 5827 |
|
|
ips_init_scb(ha, scb);
|
| 5828 |
|
|
|
| 5829 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 5830 |
|
|
scb->cdb[0] = IPS_CMD_ENQUIRY;
|
| 5831 |
|
|
|
| 5832 |
|
|
scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
|
| 5833 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 5834 |
|
|
scb->cmd.basic_io.sg_count = 0;
|
| 5835 |
|
|
scb->cmd.basic_io.lba = 0;
|
| 5836 |
|
|
scb->cmd.basic_io.sector_count = 0;
|
| 5837 |
|
|
scb->cmd.basic_io.log_drv = 0;
|
| 5838 |
|
|
scb->data_len = sizeof (*ha->enq);
|
| 5839 |
|
|
scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
|
| 5840 |
|
|
|
| 5841 |
|
|
/* send command */
|
| 5842 |
|
|
if (
|
| 5843 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 5844 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 5845 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
|
| 5846 |
|
|
return (0);
|
| 5847 |
|
|
|
| 5848 |
|
|
return (1);
|
| 5849 |
|
|
}
|
| 5850 |
|
|
|
| 5851 |
|
|
/****************************************************************************/
|
| 5852 |
|
|
/* */
|
| 5853 |
|
|
/* Routine Name: ips_read_subsystem_parameters */
|
| 5854 |
|
|
/* */
|
| 5855 |
|
|
/* Routine Description: */
|
| 5856 |
|
|
/* */
|
| 5857 |
|
|
/* Read subsystem parameters from the adapter */
|
| 5858 |
|
|
/* */
|
| 5859 |
|
|
/****************************************************************************/
|
| 5860 |
|
|
static int
|
| 5861 |
|
|
ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
|
| 5862 |
|
|
{
|
| 5863 |
|
|
ips_scb_t *scb;
|
| 5864 |
|
|
int ret;
|
| 5865 |
|
|
|
| 5866 |
|
|
METHOD_TRACE("ips_read_subsystem_parameters", 1);
|
| 5867 |
|
|
|
| 5868 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 5869 |
|
|
|
| 5870 |
|
|
ips_init_scb(ha, scb);
|
| 5871 |
|
|
|
| 5872 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 5873 |
|
|
scb->cdb[0] = IPS_CMD_GET_SUBSYS;
|
| 5874 |
|
|
|
| 5875 |
|
|
scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
|
| 5876 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 5877 |
|
|
scb->cmd.basic_io.sg_count = 0;
|
| 5878 |
|
|
scb->cmd.basic_io.lba = 0;
|
| 5879 |
|
|
scb->cmd.basic_io.sector_count = 0;
|
| 5880 |
|
|
scb->cmd.basic_io.log_drv = 0;
|
| 5881 |
|
|
scb->data_len = sizeof (*ha->subsys);
|
| 5882 |
|
|
scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
|
| 5883 |
|
|
|
| 5884 |
|
|
/* send command */
|
| 5885 |
|
|
if (
|
| 5886 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 5887 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 5888 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
|
| 5889 |
|
|
return (0);
|
| 5890 |
|
|
|
| 5891 |
|
|
memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
|
| 5892 |
|
|
return (1);
|
| 5893 |
|
|
}
|
| 5894 |
|
|
|
| 5895 |
|
|
/****************************************************************************/
|
| 5896 |
|
|
/* */
|
| 5897 |
|
|
/* Routine Name: ips_read_config */
|
| 5898 |
|
|
/* */
|
| 5899 |
|
|
/* Routine Description: */
|
| 5900 |
|
|
/* */
|
| 5901 |
|
|
/* Read the configuration on the adapter */
|
| 5902 |
|
|
/* */
|
| 5903 |
|
|
/****************************************************************************/
|
| 5904 |
|
|
static int
|
| 5905 |
|
|
ips_read_config(ips_ha_t * ha, int intr)
|
| 5906 |
|
|
{
|
| 5907 |
|
|
ips_scb_t *scb;
|
| 5908 |
|
|
int i;
|
| 5909 |
|
|
int ret;
|
| 5910 |
|
|
|
| 5911 |
|
|
METHOD_TRACE("ips_read_config", 1);
|
| 5912 |
|
|
|
| 5913 |
|
|
/* set defaults for initiator IDs */
|
| 5914 |
|
|
for (i = 0; i < 4; i++)
|
| 5915 |
|
|
ha->conf->init_id[i] = 7;
|
| 5916 |
|
|
|
| 5917 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 5918 |
|
|
|
| 5919 |
|
|
ips_init_scb(ha, scb);
|
| 5920 |
|
|
|
| 5921 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 5922 |
|
|
scb->cdb[0] = IPS_CMD_READ_CONF;
|
| 5923 |
|
|
|
| 5924 |
|
|
scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
|
| 5925 |
|
|
scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
|
| 5926 |
|
|
scb->data_len = sizeof (*ha->conf);
|
| 5927 |
|
|
scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
|
| 5928 |
|
|
|
| 5929 |
|
|
/* send command */
|
| 5930 |
|
|
if (
|
| 5931 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 5932 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 5933 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
|
| 5934 |
|
|
|
| 5935 |
|
|
memset(ha->conf, 0, sizeof (IPS_CONF));
|
| 5936 |
|
|
|
| 5937 |
|
|
/* reset initiator IDs */
|
| 5938 |
|
|
for (i = 0; i < 4; i++)
|
| 5939 |
|
|
ha->conf->init_id[i] = 7;
|
| 5940 |
|
|
|
| 5941 |
|
|
/* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
|
| 5942 |
|
|
if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
|
| 5943 |
|
|
IPS_CMD_CMPLT_WERROR) return (1);
|
| 5944 |
|
|
|
| 5945 |
|
|
return (0);
|
| 5946 |
|
|
}
|
| 5947 |
|
|
|
| 5948 |
|
|
memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
|
| 5949 |
|
|
return (1);
|
| 5950 |
|
|
}
|
| 5951 |
|
|
|
| 5952 |
|
|
/****************************************************************************/
|
| 5953 |
|
|
/* */
|
| 5954 |
|
|
/* Routine Name: ips_readwrite_page5 */
|
| 5955 |
|
|
/* */
|
| 5956 |
|
|
/* Routine Description: */
|
| 5957 |
|
|
/* */
|
| 5958 |
|
|
/* Read nvram page 5 from the adapter */
|
| 5959 |
|
|
/* */
|
| 5960 |
|
|
/****************************************************************************/
|
| 5961 |
|
|
static int
|
| 5962 |
|
|
ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
|
| 5963 |
|
|
{
|
| 5964 |
|
|
ips_scb_t *scb;
|
| 5965 |
|
|
int ret;
|
| 5966 |
|
|
|
| 5967 |
|
|
METHOD_TRACE("ips_readwrite_page5", 1);
|
| 5968 |
|
|
|
| 5969 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 5970 |
|
|
|
| 5971 |
|
|
ips_init_scb(ha, scb);
|
| 5972 |
|
|
|
| 5973 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 5974 |
|
|
scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
|
| 5975 |
|
|
|
| 5976 |
|
|
scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
|
| 5977 |
|
|
scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
|
| 5978 |
|
|
scb->cmd.nvram.page = 5;
|
| 5979 |
|
|
scb->cmd.nvram.write = write;
|
| 5980 |
|
|
scb->cmd.nvram.reserved = 0;
|
| 5981 |
|
|
scb->cmd.nvram.reserved2 = 0;
|
| 5982 |
|
|
scb->data_len = sizeof (*ha->nvram);
|
| 5983 |
|
|
scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
|
| 5984 |
|
|
if (write)
|
| 5985 |
|
|
memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
|
| 5986 |
|
|
|
| 5987 |
|
|
/* issue the command */
|
| 5988 |
|
|
if (
|
| 5989 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 5990 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 5991 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
|
| 5992 |
|
|
|
| 5993 |
|
|
memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
|
| 5994 |
|
|
|
| 5995 |
|
|
return (0);
|
| 5996 |
|
|
}
|
| 5997 |
|
|
if (!write)
|
| 5998 |
|
|
memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
|
| 5999 |
|
|
return (1);
|
| 6000 |
|
|
}
|
| 6001 |
|
|
|
| 6002 |
|
|
/****************************************************************************/
|
| 6003 |
|
|
/* */
|
| 6004 |
|
|
/* Routine Name: ips_clear_adapter */
|
| 6005 |
|
|
/* */
|
| 6006 |
|
|
/* Routine Description: */
|
| 6007 |
|
|
/* */
|
| 6008 |
|
|
/* Clear the stripe lock tables */
|
| 6009 |
|
|
/* */
|
| 6010 |
|
|
/****************************************************************************/
|
| 6011 |
|
|
static int
|
| 6012 |
|
|
ips_clear_adapter(ips_ha_t * ha, int intr)
|
| 6013 |
|
|
{
|
| 6014 |
|
|
ips_scb_t *scb;
|
| 6015 |
|
|
int ret;
|
| 6016 |
|
|
|
| 6017 |
|
|
METHOD_TRACE("ips_clear_adapter", 1);
|
| 6018 |
|
|
|
| 6019 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 6020 |
|
|
|
| 6021 |
|
|
ips_init_scb(ha, scb);
|
| 6022 |
|
|
|
| 6023 |
|
|
scb->timeout = ips_reset_timeout;
|
| 6024 |
|
|
scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
|
| 6025 |
|
|
|
| 6026 |
|
|
scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
|
| 6027 |
|
|
scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
|
| 6028 |
|
|
scb->cmd.config_sync.channel = 0;
|
| 6029 |
|
|
scb->cmd.config_sync.source_target = IPS_POCL;
|
| 6030 |
|
|
scb->cmd.config_sync.reserved = 0;
|
| 6031 |
|
|
scb->cmd.config_sync.reserved2 = 0;
|
| 6032 |
|
|
scb->cmd.config_sync.reserved3 = 0;
|
| 6033 |
|
|
|
| 6034 |
|
|
/* issue command */
|
| 6035 |
|
|
if (
|
| 6036 |
|
|
((ret = ips_send_wait(ha, scb, ips_reset_timeout, intr)) ==
|
| 6037 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 6038 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
|
| 6039 |
|
|
return (0);
|
| 6040 |
|
|
|
| 6041 |
|
|
/* send unlock stripe command */
|
| 6042 |
|
|
ips_init_scb(ha, scb);
|
| 6043 |
|
|
|
| 6044 |
|
|
scb->cdb[0] = IPS_CMD_ERROR_TABLE;
|
| 6045 |
|
|
scb->timeout = ips_reset_timeout;
|
| 6046 |
|
|
|
| 6047 |
|
|
scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
|
| 6048 |
|
|
scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
|
| 6049 |
|
|
scb->cmd.unlock_stripe.log_drv = 0;
|
| 6050 |
|
|
scb->cmd.unlock_stripe.control = IPS_CSL;
|
| 6051 |
|
|
scb->cmd.unlock_stripe.reserved = 0;
|
| 6052 |
|
|
scb->cmd.unlock_stripe.reserved2 = 0;
|
| 6053 |
|
|
scb->cmd.unlock_stripe.reserved3 = 0;
|
| 6054 |
|
|
|
| 6055 |
|
|
/* issue command */
|
| 6056 |
|
|
if (
|
| 6057 |
|
|
((ret = ips_send_wait(ha, scb, ips_cmd_timeout, intr)) ==
|
| 6058 |
|
|
IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)
|
| 6059 |
|
|
|| ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
|
| 6060 |
|
|
return (0);
|
| 6061 |
|
|
|
| 6062 |
|
|
return (1);
|
| 6063 |
|
|
}
|
| 6064 |
|
|
|
| 6065 |
|
|
/****************************************************************************/
|
| 6066 |
|
|
/* */
|
| 6067 |
|
|
/* Routine Name: ips_ffdc_reset */
|
| 6068 |
|
|
/* */
|
| 6069 |
|
|
/* Routine Description: */
|
| 6070 |
|
|
/* */
|
| 6071 |
|
|
/* FFDC: write reset info */
|
| 6072 |
|
|
/* */
|
| 6073 |
|
|
/****************************************************************************/
|
| 6074 |
|
|
static void
|
| 6075 |
|
|
ips_ffdc_reset(ips_ha_t * ha, int intr)
|
| 6076 |
|
|
{
|
| 6077 |
|
|
ips_scb_t *scb;
|
| 6078 |
|
|
|
| 6079 |
|
|
METHOD_TRACE("ips_ffdc_reset", 1);
|
| 6080 |
|
|
|
| 6081 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 6082 |
|
|
|
| 6083 |
|
|
ips_init_scb(ha, scb);
|
| 6084 |
|
|
|
| 6085 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 6086 |
|
|
scb->cdb[0] = IPS_CMD_FFDC;
|
| 6087 |
|
|
scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
|
| 6088 |
|
|
scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
|
| 6089 |
|
|
scb->cmd.ffdc.reset_count = ha->reset_count;
|
| 6090 |
|
|
scb->cmd.ffdc.reset_type = 0x80;
|
| 6091 |
|
|
|
| 6092 |
|
|
/* convert time to what the card wants */
|
| 6093 |
|
|
ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
|
| 6094 |
|
|
|
| 6095 |
|
|
/* issue command */
|
| 6096 |
|
|
ips_send_wait(ha, scb, ips_cmd_timeout, intr);
|
| 6097 |
|
|
}
|
| 6098 |
|
|
|
| 6099 |
|
|
/****************************************************************************/
|
| 6100 |
|
|
/* */
|
| 6101 |
|
|
/* Routine Name: ips_ffdc_time */
|
| 6102 |
|
|
/* */
|
| 6103 |
|
|
/* Routine Description: */
|
| 6104 |
|
|
/* */
|
| 6105 |
|
|
/* FFDC: write time info */
|
| 6106 |
|
|
/* */
|
| 6107 |
|
|
/****************************************************************************/
|
| 6108 |
|
|
static void
|
| 6109 |
|
|
ips_ffdc_time(ips_ha_t * ha)
|
| 6110 |
|
|
{
|
| 6111 |
|
|
ips_scb_t *scb;
|
| 6112 |
|
|
|
| 6113 |
|
|
METHOD_TRACE("ips_ffdc_time", 1);
|
| 6114 |
|
|
|
| 6115 |
|
|
DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
|
| 6116 |
|
|
|
| 6117 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 6118 |
|
|
|
| 6119 |
|
|
ips_init_scb(ha, scb);
|
| 6120 |
|
|
|
| 6121 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 6122 |
|
|
scb->cdb[0] = IPS_CMD_FFDC;
|
| 6123 |
|
|
scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
|
| 6124 |
|
|
scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
|
| 6125 |
|
|
scb->cmd.ffdc.reset_count = 0;
|
| 6126 |
|
|
scb->cmd.ffdc.reset_type = 0;
|
| 6127 |
|
|
|
| 6128 |
|
|
/* convert time to what the card wants */
|
| 6129 |
|
|
ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
|
| 6130 |
|
|
|
| 6131 |
|
|
/* issue command */
|
| 6132 |
|
|
ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
|
| 6133 |
|
|
}
|
| 6134 |
|
|
|
| 6135 |
|
|
/****************************************************************************/
|
| 6136 |
|
|
/* */
|
| 6137 |
|
|
/* Routine Name: ips_fix_ffdc_time */
|
| 6138 |
|
|
/* */
|
| 6139 |
|
|
/* Routine Description: */
|
| 6140 |
|
|
/* Adjust time_t to what the card wants */
|
| 6141 |
|
|
/* */
|
| 6142 |
|
|
/****************************************************************************/
|
| 6143 |
|
|
static void
|
| 6144 |
|
|
ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
|
| 6145 |
|
|
{
|
| 6146 |
|
|
long days;
|
| 6147 |
|
|
long rem;
|
| 6148 |
|
|
int i;
|
| 6149 |
|
|
int year;
|
| 6150 |
|
|
int yleap;
|
| 6151 |
|
|
int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
|
| 6152 |
|
|
int month_lengths[12][2] = { {31, 31},
|
| 6153 |
|
|
{28, 29},
|
| 6154 |
|
|
{31, 31},
|
| 6155 |
|
|
{30, 30},
|
| 6156 |
|
|
{31, 31},
|
| 6157 |
|
|
{30, 30},
|
| 6158 |
|
|
{31, 31},
|
| 6159 |
|
|
{31, 31},
|
| 6160 |
|
|
{30, 30},
|
| 6161 |
|
|
{31, 31},
|
| 6162 |
|
|
{30, 30},
|
| 6163 |
|
|
{31, 31}
|
| 6164 |
|
|
};
|
| 6165 |
|
|
|
| 6166 |
|
|
METHOD_TRACE("ips_fix_ffdc_time", 1);
|
| 6167 |
|
|
|
| 6168 |
|
|
days = current_time / IPS_SECS_DAY;
|
| 6169 |
|
|
rem = current_time % IPS_SECS_DAY;
|
| 6170 |
|
|
|
| 6171 |
|
|
scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
|
| 6172 |
|
|
rem = rem % IPS_SECS_HOUR;
|
| 6173 |
|
|
scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
|
| 6174 |
|
|
scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
|
| 6175 |
|
|
|
| 6176 |
|
|
year = IPS_EPOCH_YEAR;
|
| 6177 |
|
|
while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
|
| 6178 |
|
|
int newy;
|
| 6179 |
|
|
|
| 6180 |
|
|
newy = year + (days / IPS_DAYS_NORMAL_YEAR);
|
| 6181 |
|
|
if (days < 0)
|
| 6182 |
|
|
--newy;
|
| 6183 |
|
|
days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
|
| 6184 |
|
|
IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
|
| 6185 |
|
|
IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
|
| 6186 |
|
|
year = newy;
|
| 6187 |
|
|
}
|
| 6188 |
|
|
|
| 6189 |
|
|
scb->cmd.ffdc.yearH = year / 100;
|
| 6190 |
|
|
scb->cmd.ffdc.yearL = year % 100;
|
| 6191 |
|
|
|
| 6192 |
|
|
for (i = 0; days >= month_lengths[i][yleap]; ++i)
|
| 6193 |
|
|
days -= month_lengths[i][yleap];
|
| 6194 |
|
|
|
| 6195 |
|
|
scb->cmd.ffdc.month = i + 1;
|
| 6196 |
|
|
scb->cmd.ffdc.day = days + 1;
|
| 6197 |
|
|
}
|
| 6198 |
|
|
|
| 6199 |
|
|
/****************************************************************************
|
| 6200 |
|
|
* BIOS Flash Routines *
|
| 6201 |
|
|
****************************************************************************/
|
| 6202 |
|
|
|
| 6203 |
|
|
/****************************************************************************/
|
| 6204 |
|
|
/* */
|
| 6205 |
|
|
/* Routine Name: ips_erase_bios */
|
| 6206 |
|
|
/* */
|
| 6207 |
|
|
/* Routine Description: */
|
| 6208 |
|
|
/* Erase the BIOS on the adapter */
|
| 6209 |
|
|
/* */
|
| 6210 |
|
|
/****************************************************************************/
|
| 6211 |
|
|
static int
|
| 6212 |
|
|
ips_erase_bios(ips_ha_t * ha)
|
| 6213 |
|
|
{
|
| 6214 |
|
|
int timeout;
|
| 6215 |
|
|
uint8_t status = 0;
|
| 6216 |
|
|
|
| 6217 |
|
|
METHOD_TRACE("ips_erase_bios", 1);
|
| 6218 |
|
|
|
| 6219 |
|
|
status = 0;
|
| 6220 |
|
|
|
| 6221 |
|
|
/* Clear the status register */
|
| 6222 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6223 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6224 |
|
|
udelay(25); /* 25 us */
|
| 6225 |
|
|
|
| 6226 |
|
|
outb(0x50, ha->io_addr + IPS_REG_FLDP);
|
| 6227 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6228 |
|
|
udelay(25); /* 25 us */
|
| 6229 |
|
|
|
| 6230 |
|
|
/* Erase Setup */
|
| 6231 |
|
|
outb(0x20, ha->io_addr + IPS_REG_FLDP);
|
| 6232 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6233 |
|
|
udelay(25); /* 25 us */
|
| 6234 |
|
|
|
| 6235 |
|
|
/* Erase Confirm */
|
| 6236 |
|
|
outb(0xD0, ha->io_addr + IPS_REG_FLDP);
|
| 6237 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6238 |
|
|
udelay(25); /* 25 us */
|
| 6239 |
|
|
|
| 6240 |
|
|
/* Erase Status */
|
| 6241 |
|
|
outb(0x70, ha->io_addr + IPS_REG_FLDP);
|
| 6242 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6243 |
|
|
udelay(25); /* 25 us */
|
| 6244 |
|
|
|
| 6245 |
|
|
timeout = 80000; /* 80 seconds */
|
| 6246 |
|
|
|
| 6247 |
|
|
while (timeout > 0) {
|
| 6248 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6249 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6250 |
|
|
udelay(25); /* 25 us */
|
| 6251 |
|
|
}
|
| 6252 |
|
|
|
| 6253 |
|
|
status = inb(ha->io_addr + IPS_REG_FLDP);
|
| 6254 |
|
|
|
| 6255 |
|
|
if (status & 0x80)
|
| 6256 |
|
|
break;
|
| 6257 |
|
|
|
| 6258 |
|
|
MDELAY(1);
|
| 6259 |
|
|
timeout--;
|
| 6260 |
|
|
}
|
| 6261 |
|
|
|
| 6262 |
|
|
/* check for timeout */
|
| 6263 |
|
|
if (timeout <= 0) {
|
| 6264 |
|
|
/* timeout */
|
| 6265 |
|
|
|
| 6266 |
|
|
/* try to suspend the erase */
|
| 6267 |
|
|
outb(0xB0, ha->io_addr + IPS_REG_FLDP);
|
| 6268 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6269 |
|
|
udelay(25); /* 25 us */
|
| 6270 |
|
|
|
| 6271 |
|
|
/* wait for 10 seconds */
|
| 6272 |
|
|
timeout = 10000;
|
| 6273 |
|
|
while (timeout > 0) {
|
| 6274 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6275 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6276 |
|
|
udelay(25); /* 25 us */
|
| 6277 |
|
|
}
|
| 6278 |
|
|
|
| 6279 |
|
|
status = inb(ha->io_addr + IPS_REG_FLDP);
|
| 6280 |
|
|
|
| 6281 |
|
|
if (status & 0xC0)
|
| 6282 |
|
|
break;
|
| 6283 |
|
|
|
| 6284 |
|
|
MDELAY(1);
|
| 6285 |
|
|
timeout--;
|
| 6286 |
|
|
}
|
| 6287 |
|
|
|
| 6288 |
|
|
return (1);
|
| 6289 |
|
|
}
|
| 6290 |
|
|
|
| 6291 |
|
|
/* check for valid VPP */
|
| 6292 |
|
|
if (status & 0x08)
|
| 6293 |
|
|
/* VPP failure */
|
| 6294 |
|
|
return (1);
|
| 6295 |
|
|
|
| 6296 |
|
|
/* check for succesful flash */
|
| 6297 |
|
|
if (status & 0x30)
|
| 6298 |
|
|
/* sequence error */
|
| 6299 |
|
|
return (1);
|
| 6300 |
|
|
|
| 6301 |
|
|
/* Otherwise, we were successful */
|
| 6302 |
|
|
/* clear status */
|
| 6303 |
|
|
outb(0x50, ha->io_addr + IPS_REG_FLDP);
|
| 6304 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6305 |
|
|
udelay(25); /* 25 us */
|
| 6306 |
|
|
|
| 6307 |
|
|
/* enable reads */
|
| 6308 |
|
|
outb(0xFF, ha->io_addr + IPS_REG_FLDP);
|
| 6309 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6310 |
|
|
udelay(25); /* 25 us */
|
| 6311 |
|
|
|
| 6312 |
|
|
return (0);
|
| 6313 |
|
|
}
|
| 6314 |
|
|
|
| 6315 |
|
|
/****************************************************************************/
|
| 6316 |
|
|
/* */
|
| 6317 |
|
|
/* Routine Name: ips_erase_bios_memio */
|
| 6318 |
|
|
/* */
|
| 6319 |
|
|
/* Routine Description: */
|
| 6320 |
|
|
/* Erase the BIOS on the adapter */
|
| 6321 |
|
|
/* */
|
| 6322 |
|
|
/****************************************************************************/
|
| 6323 |
|
|
static int
|
| 6324 |
|
|
ips_erase_bios_memio(ips_ha_t * ha)
|
| 6325 |
|
|
{
|
| 6326 |
|
|
int timeout;
|
| 6327 |
|
|
uint8_t status;
|
| 6328 |
|
|
|
| 6329 |
|
|
METHOD_TRACE("ips_erase_bios_memio", 1);
|
| 6330 |
|
|
|
| 6331 |
|
|
status = 0;
|
| 6332 |
|
|
|
| 6333 |
|
|
/* Clear the status register */
|
| 6334 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6335 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6336 |
|
|
udelay(25); /* 25 us */
|
| 6337 |
|
|
|
| 6338 |
|
|
writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
|
| 6339 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6340 |
|
|
udelay(25); /* 25 us */
|
| 6341 |
|
|
|
| 6342 |
|
|
/* Erase Setup */
|
| 6343 |
|
|
writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
|
| 6344 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6345 |
|
|
udelay(25); /* 25 us */
|
| 6346 |
|
|
|
| 6347 |
|
|
/* Erase Confirm */
|
| 6348 |
|
|
writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
|
| 6349 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6350 |
|
|
udelay(25); /* 25 us */
|
| 6351 |
|
|
|
| 6352 |
|
|
/* Erase Status */
|
| 6353 |
|
|
writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
|
| 6354 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6355 |
|
|
udelay(25); /* 25 us */
|
| 6356 |
|
|
|
| 6357 |
|
|
timeout = 80000; /* 80 seconds */
|
| 6358 |
|
|
|
| 6359 |
|
|
while (timeout > 0) {
|
| 6360 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6361 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6362 |
|
|
udelay(25); /* 25 us */
|
| 6363 |
|
|
}
|
| 6364 |
|
|
|
| 6365 |
|
|
status = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 6366 |
|
|
|
| 6367 |
|
|
if (status & 0x80)
|
| 6368 |
|
|
break;
|
| 6369 |
|
|
|
| 6370 |
|
|
MDELAY(1);
|
| 6371 |
|
|
timeout--;
|
| 6372 |
|
|
}
|
| 6373 |
|
|
|
| 6374 |
|
|
/* check for timeout */
|
| 6375 |
|
|
if (timeout <= 0) {
|
| 6376 |
|
|
/* timeout */
|
| 6377 |
|
|
|
| 6378 |
|
|
/* try to suspend the erase */
|
| 6379 |
|
|
writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
|
| 6380 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6381 |
|
|
udelay(25); /* 25 us */
|
| 6382 |
|
|
|
| 6383 |
|
|
/* wait for 10 seconds */
|
| 6384 |
|
|
timeout = 10000;
|
| 6385 |
|
|
while (timeout > 0) {
|
| 6386 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6387 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6388 |
|
|
udelay(25); /* 25 us */
|
| 6389 |
|
|
}
|
| 6390 |
|
|
|
| 6391 |
|
|
status = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 6392 |
|
|
|
| 6393 |
|
|
if (status & 0xC0)
|
| 6394 |
|
|
break;
|
| 6395 |
|
|
|
| 6396 |
|
|
MDELAY(1);
|
| 6397 |
|
|
timeout--;
|
| 6398 |
|
|
}
|
| 6399 |
|
|
|
| 6400 |
|
|
return (1);
|
| 6401 |
|
|
}
|
| 6402 |
|
|
|
| 6403 |
|
|
/* check for valid VPP */
|
| 6404 |
|
|
if (status & 0x08)
|
| 6405 |
|
|
/* VPP failure */
|
| 6406 |
|
|
return (1);
|
| 6407 |
|
|
|
| 6408 |
|
|
/* check for succesful flash */
|
| 6409 |
|
|
if (status & 0x30)
|
| 6410 |
|
|
/* sequence error */
|
| 6411 |
|
|
return (1);
|
| 6412 |
|
|
|
| 6413 |
|
|
/* Otherwise, we were successful */
|
| 6414 |
|
|
/* clear status */
|
| 6415 |
|
|
writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
|
| 6416 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6417 |
|
|
udelay(25); /* 25 us */
|
| 6418 |
|
|
|
| 6419 |
|
|
/* enable reads */
|
| 6420 |
|
|
writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
|
| 6421 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6422 |
|
|
udelay(25); /* 25 us */
|
| 6423 |
|
|
|
| 6424 |
|
|
return (0);
|
| 6425 |
|
|
}
|
| 6426 |
|
|
|
| 6427 |
|
|
/****************************************************************************/
|
| 6428 |
|
|
/* */
|
| 6429 |
|
|
/* Routine Name: ips_program_bios */
|
| 6430 |
|
|
/* */
|
| 6431 |
|
|
/* Routine Description: */
|
| 6432 |
|
|
/* Program the BIOS on the adapter */
|
| 6433 |
|
|
/* */
|
| 6434 |
|
|
/****************************************************************************/
|
| 6435 |
|
|
static int
|
| 6436 |
|
|
ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
|
| 6437 |
|
|
uint32_t offset)
|
| 6438 |
|
|
{
|
| 6439 |
|
|
int i;
|
| 6440 |
|
|
int timeout;
|
| 6441 |
|
|
uint8_t status = 0;
|
| 6442 |
|
|
|
| 6443 |
|
|
METHOD_TRACE("ips_program_bios", 1);
|
| 6444 |
|
|
|
| 6445 |
|
|
status = 0;
|
| 6446 |
|
|
|
| 6447 |
|
|
for (i = 0; i < buffersize; i++) {
|
| 6448 |
|
|
/* write a byte */
|
| 6449 |
|
|
outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
|
| 6450 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6451 |
|
|
udelay(25); /* 25 us */
|
| 6452 |
|
|
|
| 6453 |
|
|
outb(0x40, ha->io_addr + IPS_REG_FLDP);
|
| 6454 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6455 |
|
|
udelay(25); /* 25 us */
|
| 6456 |
|
|
|
| 6457 |
|
|
outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
|
| 6458 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6459 |
|
|
udelay(25); /* 25 us */
|
| 6460 |
|
|
|
| 6461 |
|
|
/* wait up to one second */
|
| 6462 |
|
|
timeout = 1000;
|
| 6463 |
|
|
while (timeout > 0) {
|
| 6464 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6465 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6466 |
|
|
udelay(25); /* 25 us */
|
| 6467 |
|
|
}
|
| 6468 |
|
|
|
| 6469 |
|
|
status = inb(ha->io_addr + IPS_REG_FLDP);
|
| 6470 |
|
|
|
| 6471 |
|
|
if (status & 0x80)
|
| 6472 |
|
|
break;
|
| 6473 |
|
|
|
| 6474 |
|
|
MDELAY(1);
|
| 6475 |
|
|
timeout--;
|
| 6476 |
|
|
}
|
| 6477 |
|
|
|
| 6478 |
|
|
if (timeout == 0) {
|
| 6479 |
|
|
/* timeout error */
|
| 6480 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6481 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6482 |
|
|
udelay(25); /* 25 us */
|
| 6483 |
|
|
|
| 6484 |
|
|
outb(0xFF, ha->io_addr + IPS_REG_FLDP);
|
| 6485 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6486 |
|
|
udelay(25); /* 25 us */
|
| 6487 |
|
|
|
| 6488 |
|
|
return (1);
|
| 6489 |
|
|
}
|
| 6490 |
|
|
|
| 6491 |
|
|
/* check the status */
|
| 6492 |
|
|
if (status & 0x18) {
|
| 6493 |
|
|
/* programming error */
|
| 6494 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6495 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6496 |
|
|
udelay(25); /* 25 us */
|
| 6497 |
|
|
|
| 6498 |
|
|
outb(0xFF, ha->io_addr + IPS_REG_FLDP);
|
| 6499 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6500 |
|
|
udelay(25); /* 25 us */
|
| 6501 |
|
|
|
| 6502 |
|
|
return (1);
|
| 6503 |
|
|
}
|
| 6504 |
|
|
} /* end for */
|
| 6505 |
|
|
|
| 6506 |
|
|
/* Enable reading */
|
| 6507 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6508 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6509 |
|
|
udelay(25); /* 25 us */
|
| 6510 |
|
|
|
| 6511 |
|
|
outb(0xFF, ha->io_addr + IPS_REG_FLDP);
|
| 6512 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6513 |
|
|
udelay(25); /* 25 us */
|
| 6514 |
|
|
|
| 6515 |
|
|
return (0);
|
| 6516 |
|
|
}
|
| 6517 |
|
|
|
| 6518 |
|
|
/****************************************************************************/
|
| 6519 |
|
|
/* */
|
| 6520 |
|
|
/* Routine Name: ips_program_bios_memio */
|
| 6521 |
|
|
/* */
|
| 6522 |
|
|
/* Routine Description: */
|
| 6523 |
|
|
/* Program the BIOS on the adapter */
|
| 6524 |
|
|
/* */
|
| 6525 |
|
|
/****************************************************************************/
|
| 6526 |
|
|
static int
|
| 6527 |
|
|
ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
|
| 6528 |
|
|
uint32_t offset)
|
| 6529 |
|
|
{
|
| 6530 |
|
|
int i;
|
| 6531 |
|
|
int timeout;
|
| 6532 |
|
|
uint8_t status = 0;
|
| 6533 |
|
|
|
| 6534 |
|
|
METHOD_TRACE("ips_program_bios_memio", 1);
|
| 6535 |
|
|
|
| 6536 |
|
|
status = 0;
|
| 6537 |
|
|
|
| 6538 |
|
|
for (i = 0; i < buffersize; i++) {
|
| 6539 |
|
|
/* write a byte */
|
| 6540 |
|
|
writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
|
| 6541 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6542 |
|
|
udelay(25); /* 25 us */
|
| 6543 |
|
|
|
| 6544 |
|
|
writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
|
| 6545 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6546 |
|
|
udelay(25); /* 25 us */
|
| 6547 |
|
|
|
| 6548 |
|
|
writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
|
| 6549 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6550 |
|
|
udelay(25); /* 25 us */
|
| 6551 |
|
|
|
| 6552 |
|
|
/* wait up to one second */
|
| 6553 |
|
|
timeout = 1000;
|
| 6554 |
|
|
while (timeout > 0) {
|
| 6555 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64) {
|
| 6556 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6557 |
|
|
udelay(25); /* 25 us */
|
| 6558 |
|
|
}
|
| 6559 |
|
|
|
| 6560 |
|
|
status = readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 6561 |
|
|
|
| 6562 |
|
|
if (status & 0x80)
|
| 6563 |
|
|
break;
|
| 6564 |
|
|
|
| 6565 |
|
|
MDELAY(1);
|
| 6566 |
|
|
timeout--;
|
| 6567 |
|
|
}
|
| 6568 |
|
|
|
| 6569 |
|
|
if (timeout == 0) {
|
| 6570 |
|
|
/* timeout error */
|
| 6571 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6572 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6573 |
|
|
udelay(25); /* 25 us */
|
| 6574 |
|
|
|
| 6575 |
|
|
writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
|
| 6576 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6577 |
|
|
udelay(25); /* 25 us */
|
| 6578 |
|
|
|
| 6579 |
|
|
return (1);
|
| 6580 |
|
|
}
|
| 6581 |
|
|
|
| 6582 |
|
|
/* check the status */
|
| 6583 |
|
|
if (status & 0x18) {
|
| 6584 |
|
|
/* programming error */
|
| 6585 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6586 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6587 |
|
|
udelay(25); /* 25 us */
|
| 6588 |
|
|
|
| 6589 |
|
|
writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
|
| 6590 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6591 |
|
|
udelay(25); /* 25 us */
|
| 6592 |
|
|
|
| 6593 |
|
|
return (1);
|
| 6594 |
|
|
}
|
| 6595 |
|
|
} /* end for */
|
| 6596 |
|
|
|
| 6597 |
|
|
/* Enable reading */
|
| 6598 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6599 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6600 |
|
|
udelay(25); /* 25 us */
|
| 6601 |
|
|
|
| 6602 |
|
|
writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
|
| 6603 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6604 |
|
|
udelay(25); /* 25 us */
|
| 6605 |
|
|
|
| 6606 |
|
|
return (0);
|
| 6607 |
|
|
}
|
| 6608 |
|
|
|
| 6609 |
|
|
/****************************************************************************/
|
| 6610 |
|
|
/* */
|
| 6611 |
|
|
/* Routine Name: ips_verify_bios */
|
| 6612 |
|
|
/* */
|
| 6613 |
|
|
/* Routine Description: */
|
| 6614 |
|
|
/* Verify the BIOS on the adapter */
|
| 6615 |
|
|
/* */
|
| 6616 |
|
|
/****************************************************************************/
|
| 6617 |
|
|
static int
|
| 6618 |
|
|
ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
|
| 6619 |
|
|
uint32_t offset)
|
| 6620 |
|
|
{
|
| 6621 |
|
|
uint8_t checksum;
|
| 6622 |
|
|
int i;
|
| 6623 |
|
|
|
| 6624 |
|
|
METHOD_TRACE("ips_verify_bios", 1);
|
| 6625 |
|
|
|
| 6626 |
|
|
/* test 1st byte */
|
| 6627 |
|
|
outl(0, ha->io_addr + IPS_REG_FLAP);
|
| 6628 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6629 |
|
|
udelay(25); /* 25 us */
|
| 6630 |
|
|
|
| 6631 |
|
|
if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
|
| 6632 |
|
|
return (1);
|
| 6633 |
|
|
|
| 6634 |
|
|
outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
|
| 6635 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6636 |
|
|
udelay(25); /* 25 us */
|
| 6637 |
|
|
if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
|
| 6638 |
|
|
return (1);
|
| 6639 |
|
|
|
| 6640 |
|
|
checksum = 0xff;
|
| 6641 |
|
|
for (i = 2; i < buffersize; i++) {
|
| 6642 |
|
|
|
| 6643 |
|
|
outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
|
| 6644 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6645 |
|
|
udelay(25); /* 25 us */
|
| 6646 |
|
|
|
| 6647 |
|
|
checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
|
| 6648 |
|
|
}
|
| 6649 |
|
|
|
| 6650 |
|
|
if (checksum != 0)
|
| 6651 |
|
|
/* failure */
|
| 6652 |
|
|
return (1);
|
| 6653 |
|
|
else
|
| 6654 |
|
|
/* success */
|
| 6655 |
|
|
return (0);
|
| 6656 |
|
|
}
|
| 6657 |
|
|
|
| 6658 |
|
|
/****************************************************************************/
|
| 6659 |
|
|
/* */
|
| 6660 |
|
|
/* Routine Name: ips_verify_bios_memio */
|
| 6661 |
|
|
/* */
|
| 6662 |
|
|
/* Routine Description: */
|
| 6663 |
|
|
/* Verify the BIOS on the adapter */
|
| 6664 |
|
|
/* */
|
| 6665 |
|
|
/****************************************************************************/
|
| 6666 |
|
|
static int
|
| 6667 |
|
|
ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
|
| 6668 |
|
|
uint32_t offset)
|
| 6669 |
|
|
{
|
| 6670 |
|
|
uint8_t checksum;
|
| 6671 |
|
|
int i;
|
| 6672 |
|
|
|
| 6673 |
|
|
METHOD_TRACE("ips_verify_bios_memio", 1);
|
| 6674 |
|
|
|
| 6675 |
|
|
/* test 1st byte */
|
| 6676 |
|
|
writel(0, ha->mem_ptr + IPS_REG_FLAP);
|
| 6677 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6678 |
|
|
udelay(25); /* 25 us */
|
| 6679 |
|
|
|
| 6680 |
|
|
if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
|
| 6681 |
|
|
return (1);
|
| 6682 |
|
|
|
| 6683 |
|
|
writel(1, ha->mem_ptr + IPS_REG_FLAP);
|
| 6684 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6685 |
|
|
udelay(25); /* 25 us */
|
| 6686 |
|
|
if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
|
| 6687 |
|
|
return (1);
|
| 6688 |
|
|
|
| 6689 |
|
|
checksum = 0xff;
|
| 6690 |
|
|
for (i = 2; i < buffersize; i++) {
|
| 6691 |
|
|
|
| 6692 |
|
|
writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
|
| 6693 |
|
|
if (ha->revision_id == IPS_REVID_TROMBONE64)
|
| 6694 |
|
|
udelay(25); /* 25 us */
|
| 6695 |
|
|
|
| 6696 |
|
|
checksum =
|
| 6697 |
|
|
(uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
|
| 6698 |
|
|
}
|
| 6699 |
|
|
|
| 6700 |
|
|
if (checksum != 0)
|
| 6701 |
|
|
/* failure */
|
| 6702 |
|
|
return (1);
|
| 6703 |
|
|
else
|
| 6704 |
|
|
/* success */
|
| 6705 |
|
|
return (0);
|
| 6706 |
|
|
}
|
| 6707 |
|
|
|
| 6708 |
|
|
/*---------------------------------------------------------------------------*/
|
| 6709 |
|
|
/* Routine Name: ips_version_check */
|
| 6710 |
|
|
/* */
|
| 6711 |
|
|
/* Dependencies: */
|
| 6712 |
|
|
/* Assumes that ips_read_adapter_status() is called first filling in */
|
| 6713 |
|
|
/* the data for SubSystem Parameters. */
|
| 6714 |
|
|
/* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
|
| 6715 |
|
|
/* Data is available. */
|
| 6716 |
|
|
/* */
|
| 6717 |
|
|
/*---------------------------------------------------------------------------*/
|
| 6718 |
|
|
static void
|
| 6719 |
|
|
ips_version_check(ips_ha_t * ha, int intr)
|
| 6720 |
|
|
{
|
| 6721 |
|
|
IPS_VERSION_DATA *VersionInfo;
|
| 6722 |
|
|
uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
|
| 6723 |
|
|
uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
|
| 6724 |
|
|
int MatchError;
|
| 6725 |
|
|
int rc;
|
| 6726 |
|
|
char BiosString[10];
|
| 6727 |
|
|
char FirmwareString[10];
|
| 6728 |
|
|
|
| 6729 |
|
|
METHOD_TRACE("ips_version_check", 1);
|
| 6730 |
|
|
|
| 6731 |
|
|
VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
|
| 6732 |
|
|
|
| 6733 |
|
|
memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
|
| 6734 |
|
|
memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
|
| 6735 |
|
|
|
| 6736 |
|
|
/* Get the Compatible BIOS Version from NVRAM Page 5 */
|
| 6737 |
|
|
memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
|
| 6738 |
|
|
IPS_COMPAT_ID_LENGTH);
|
| 6739 |
|
|
|
| 6740 |
|
|
rc = IPS_FAILURE;
|
| 6741 |
|
|
if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
|
| 6742 |
|
|
memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
|
| 6743 |
|
|
/* Get the Version Info with a Get Version Command */
|
| 6744 |
|
|
rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
|
| 6745 |
|
|
if (rc == IPS_SUCCESS)
|
| 6746 |
|
|
memcpy(FirmwareVersion, VersionInfo->compatibilityId,
|
| 6747 |
|
|
IPS_COMPAT_ID_LENGTH);
|
| 6748 |
|
|
}
|
| 6749 |
|
|
|
| 6750 |
|
|
if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
|
| 6751 |
|
|
/* Get the Firmware Version from Enquiry Data */
|
| 6752 |
|
|
memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
|
| 6753 |
|
|
IPS_COMPAT_ID_LENGTH);
|
| 6754 |
|
|
}
|
| 6755 |
|
|
|
| 6756 |
|
|
/* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
|
| 6757 |
|
|
/* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
|
| 6758 |
|
|
/* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
|
| 6759 |
|
|
/* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
|
| 6760 |
|
|
|
| 6761 |
|
|
MatchError = 0;
|
| 6762 |
|
|
|
| 6763 |
|
|
if (strncmp
|
| 6764 |
|
|
(FirmwareVersion, Compatable[ha->nvram->adapter_type],
|
| 6765 |
|
|
IPS_COMPAT_ID_LENGTH) != 0)
|
| 6766 |
|
|
MatchError = 1;
|
| 6767 |
|
|
|
| 6768 |
|
|
if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
|
| 6769 |
|
|
MatchError = 1;
|
| 6770 |
|
|
|
| 6771 |
|
|
ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
|
| 6772 |
|
|
|
| 6773 |
|
|
if (MatchError) {
|
| 6774 |
|
|
ha->nvram->version_mismatch = 1;
|
| 6775 |
|
|
if (ips_cd_boot == 0) {
|
| 6776 |
|
|
strncpy(&BiosString[0], ha->nvram->bios_high, 4);
|
| 6777 |
|
|
strncpy(&BiosString[4], ha->nvram->bios_low, 4);
|
| 6778 |
|
|
BiosString[8] = 0;
|
| 6779 |
|
|
|
| 6780 |
|
|
strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
|
| 6781 |
|
|
FirmwareString[8] = 0;
|
| 6782 |
|
|
|
| 6783 |
|
|
printk(KERN_WARNING
|
| 6784 |
|
|
"Warning ! ! ! ServeRAID Version Mismatch\n");
|
| 6785 |
|
|
printk(KERN_WARNING
|
| 6786 |
|
|
"Bios = %s, Firmware = %s, Device Driver = %s%s\n",
|
| 6787 |
|
|
BiosString, FirmwareString, IPS_VERSION_HIGH,
|
| 6788 |
|
|
IPS_VERSION_LOW);
|
| 6789 |
|
|
printk(KERN_WARNING
|
| 6790 |
|
|
"These levels should match to avoid possible compatibility problems.\n");
|
| 6791 |
|
|
}
|
| 6792 |
|
|
} else {
|
| 6793 |
|
|
ha->nvram->version_mismatch = 0;
|
| 6794 |
|
|
}
|
| 6795 |
|
|
|
| 6796 |
|
|
return;
|
| 6797 |
|
|
}
|
| 6798 |
|
|
|
| 6799 |
|
|
/*---------------------------------------------------------------------------*/
|
| 6800 |
|
|
/* Routine Name: ips_get_version_info */
|
| 6801 |
|
|
/* */
|
| 6802 |
|
|
/* Routine Description: */
|
| 6803 |
|
|
/* Issue an internal GETVERSION Command */
|
| 6804 |
|
|
/* */
|
| 6805 |
|
|
/* Return Value: */
|
| 6806 |
|
|
/* 0 if Successful, else non-zero */
|
| 6807 |
|
|
/*---------------------------------------------------------------------------*/
|
| 6808 |
|
|
static int
|
| 6809 |
|
|
ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
|
| 6810 |
|
|
{
|
| 6811 |
|
|
ips_scb_t *scb;
|
| 6812 |
|
|
int rc;
|
| 6813 |
|
|
|
| 6814 |
|
|
METHOD_TRACE("ips_get_version_info", 1);
|
| 6815 |
|
|
|
| 6816 |
|
|
scb = &ha->scbs[ha->max_cmds - 1];
|
| 6817 |
|
|
|
| 6818 |
|
|
ips_init_scb(ha, scb);
|
| 6819 |
|
|
|
| 6820 |
|
|
scb->timeout = ips_cmd_timeout;
|
| 6821 |
|
|
scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
|
| 6822 |
|
|
scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
|
| 6823 |
|
|
scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
|
| 6824 |
|
|
scb->cmd.version_info.reserved = 0;
|
| 6825 |
|
|
scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
|
| 6826 |
|
|
scb->cmd.version_info.reserved2 = 0;
|
| 6827 |
|
|
scb->data_len = sizeof (IPS_VERSION_DATA);
|
| 6828 |
|
|
scb->data_busaddr = Buffer;
|
| 6829 |
|
|
scb->cmd.version_info.buffer_addr = Buffer;
|
| 6830 |
|
|
scb->flags = 0;
|
| 6831 |
|
|
|
| 6832 |
|
|
/* issue command */
|
| 6833 |
|
|
rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
|
| 6834 |
|
|
return (rc);
|
| 6835 |
|
|
}
|
| 6836 |
|
|
|
| 6837 |
|
|
/****************************************************************************/
|
| 6838 |
|
|
/* */
|
| 6839 |
|
|
/* Routine Name: ips_abort_init */
|
| 6840 |
|
|
/* */
|
| 6841 |
|
|
/* Routine Description: */
|
| 6842 |
|
|
/* cleanup routine for a failed adapter initialization */
|
| 6843 |
|
|
/****************************************************************************/
|
| 6844 |
|
|
static int
|
| 6845 |
|
|
ips_abort_init(ips_ha_t * ha, int index)
|
| 6846 |
|
|
{
|
| 6847 |
|
|
ha->active = 0;
|
| 6848 |
|
|
ips_free(ha);
|
| 6849 |
|
|
ips_ha[index] = 0;
|
| 6850 |
|
|
ips_sh[index] = 0;
|
| 6851 |
|
|
return -1;
|
| 6852 |
|
|
}
|
| 6853 |
|
|
|
| 6854 |
|
|
/****************************************************************************/
|
| 6855 |
|
|
/* */
|
| 6856 |
|
|
/* Routine Name: ips_shift_controllers */
|
| 6857 |
|
|
/* */
|
| 6858 |
|
|
/* Routine Description: */
|
| 6859 |
|
|
/* helper function for ordering adapters */
|
| 6860 |
|
|
/****************************************************************************/
|
| 6861 |
|
|
static void
|
| 6862 |
|
|
ips_shift_controllers(int lowindex, int highindex)
|
| 6863 |
|
|
{
|
| 6864 |
|
|
ips_ha_t *ha_sav = ips_ha[highindex];
|
| 6865 |
|
|
struct Scsi_Host *sh_sav = ips_sh[highindex];
|
| 6866 |
|
|
int i;
|
| 6867 |
|
|
|
| 6868 |
|
|
for (i = highindex; i > lowindex; i--) {
|
| 6869 |
|
|
ips_ha[i] = ips_ha[i - 1];
|
| 6870 |
|
|
ips_sh[i] = ips_sh[i - 1];
|
| 6871 |
|
|
ips_ha[i]->host_num = i;
|
| 6872 |
|
|
}
|
| 6873 |
|
|
ha_sav->host_num = lowindex;
|
| 6874 |
|
|
ips_ha[lowindex] = ha_sav;
|
| 6875 |
|
|
ips_sh[lowindex] = sh_sav;
|
| 6876 |
|
|
}
|
| 6877 |
|
|
|
| 6878 |
|
|
/****************************************************************************/
|
| 6879 |
|
|
/* */
|
| 6880 |
|
|
/* Routine Name: ips_order_controllers */
|
| 6881 |
|
|
/* */
|
| 6882 |
|
|
/* Routine Description: */
|
| 6883 |
|
|
/* place controllers is the "proper" boot order */
|
| 6884 |
|
|
/****************************************************************************/
|
| 6885 |
|
|
static void
|
| 6886 |
|
|
ips_order_controllers(void)
|
| 6887 |
|
|
{
|
| 6888 |
|
|
int i, j, tmp, position = 0;
|
| 6889 |
|
|
IPS_NVRAM_P5 *nvram;
|
| 6890 |
|
|
if (!ips_ha[0])
|
| 6891 |
|
|
return;
|
| 6892 |
|
|
nvram = ips_ha[0]->nvram;
|
| 6893 |
|
|
|
| 6894 |
|
|
if (nvram->adapter_order[0]) {
|
| 6895 |
|
|
for (i = 1; i <= nvram->adapter_order[0]; i++) {
|
| 6896 |
|
|
for (j = position; j < ips_num_controllers; j++) {
|
| 6897 |
|
|
switch (ips_ha[j]->ad_type) {
|
| 6898 |
|
|
case IPS_ADTYPE_SERVERAID6M:
|
| 6899 |
|
|
if (nvram->adapter_order[i] == 'M') {
|
| 6900 |
|
|
ips_shift_controllers(position,
|
| 6901 |
|
|
j);
|
| 6902 |
|
|
position++;
|
| 6903 |
|
|
}
|
| 6904 |
|
|
break;
|
| 6905 |
|
|
case IPS_ADTYPE_SERVERAID4L:
|
| 6906 |
|
|
case IPS_ADTYPE_SERVERAID4M:
|
| 6907 |
|
|
case IPS_ADTYPE_SERVERAID4MX:
|
| 6908 |
|
|
case IPS_ADTYPE_SERVERAID4LX:
|
| 6909 |
|
|
if (nvram->adapter_order[i] == 'N') {
|
| 6910 |
|
|
ips_shift_controllers(position,
|
| 6911 |
|
|
j);
|
| 6912 |
|
|
position++;
|
| 6913 |
|
|
}
|
| 6914 |
|
|
break;
|
| 6915 |
|
|
case IPS_ADTYPE_SERVERAID6I:
|
| 6916 |
|
|
case IPS_ADTYPE_SERVERAID5I2:
|
| 6917 |
|
|
case IPS_ADTYPE_SERVERAID5I1:
|
| 6918 |
|
|
if (nvram->adapter_order[i] == 'S') {
|
| 6919 |
|
|
ips_shift_controllers(position,
|
| 6920 |
|
|
j);
|
| 6921 |
|
|
position++;
|
| 6922 |
|
|
}
|
| 6923 |
|
|
break;
|
| 6924 |
|
|
case IPS_ADTYPE_SERVERAID:
|
| 6925 |
|
|
case IPS_ADTYPE_SERVERAID2:
|
| 6926 |
|
|
case IPS_ADTYPE_NAVAJO:
|
| 6927 |
|
|
case IPS_ADTYPE_KIOWA:
|
| 6928 |
|
|
case IPS_ADTYPE_SERVERAID3L:
|
| 6929 |
|
|
case IPS_ADTYPE_SERVERAID3:
|
| 6930 |
|
|
case IPS_ADTYPE_SERVERAID4H:
|
| 6931 |
|
|
if (nvram->adapter_order[i] == 'A') {
|
| 6932 |
|
|
ips_shift_controllers(position,
|
| 6933 |
|
|
j);
|
| 6934 |
|
|
position++;
|
| 6935 |
|
|
}
|
| 6936 |
|
|
break;
|
| 6937 |
|
|
default:
|
| 6938 |
|
|
break;
|
| 6939 |
|
|
}
|
| 6940 |
|
|
}
|
| 6941 |
|
|
}
|
| 6942 |
|
|
/* if adapter_order[0], then ordering is complete */
|
| 6943 |
|
|
return;
|
| 6944 |
|
|
}
|
| 6945 |
|
|
/* old bios, use older ordering */
|
| 6946 |
|
|
tmp = 0;
|
| 6947 |
|
|
for (i = position; i < ips_num_controllers; i++) {
|
| 6948 |
|
|
if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
|
| 6949 |
|
|
ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
|
| 6950 |
|
|
ips_shift_controllers(position, i);
|
| 6951 |
|
|
position++;
|
| 6952 |
|
|
tmp = 1;
|
| 6953 |
|
|
}
|
| 6954 |
|
|
}
|
| 6955 |
|
|
/* if there were no 5I cards, then don't do any extra ordering */
|
| 6956 |
|
|
if (!tmp)
|
| 6957 |
|
|
return;
|
| 6958 |
|
|
for (i = position; i < ips_num_controllers; i++) {
|
| 6959 |
|
|
if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
|
| 6960 |
|
|
ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
|
| 6961 |
|
|
ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
|
| 6962 |
|
|
ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
|
| 6963 |
|
|
ips_shift_controllers(position, i);
|
| 6964 |
|
|
position++;
|
| 6965 |
|
|
}
|
| 6966 |
|
|
}
|
| 6967 |
|
|
|
| 6968 |
|
|
return;
|
| 6969 |
|
|
}
|
| 6970 |
|
|
|
| 6971 |
|
|
/****************************************************************************/
|
| 6972 |
|
|
/* */
|
| 6973 |
|
|
/* Routine Name: ips_register_scsi */
|
| 6974 |
|
|
/* */
|
| 6975 |
|
|
/* Routine Description: */
|
| 6976 |
|
|
/* perform any registration and setup with the scsi layer */
|
| 6977 |
|
|
/****************************************************************************/
|
| 6978 |
|
|
static int
|
| 6979 |
|
|
ips_register_scsi(int index)
|
| 6980 |
|
|
{
|
| 6981 |
|
|
struct Scsi_Host *sh;
|
| 6982 |
|
|
ips_ha_t *ha, *oldha;
|
| 6983 |
|
|
sh = scsi_register(&ips_driver_template, sizeof (ips_ha_t));
|
| 6984 |
|
|
if (!sh) {
|
| 6985 |
|
|
printk(KERN_WARNING
|
| 6986 |
|
|
"Unable to register controller with SCSI subsystem\n");
|
| 6987 |
|
|
return -1;
|
| 6988 |
|
|
}
|
| 6989 |
|
|
oldha = ips_ha[index];
|
| 6990 |
|
|
ha = IPS_HA(sh);
|
| 6991 |
|
|
memcpy(ha, oldha, sizeof (ips_ha_t));
|
| 6992 |
|
|
free_irq(oldha->irq, oldha);
|
| 6993 |
|
|
/* Install the interrupt handler with the new ha */
|
| 6994 |
|
|
if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
|
| 6995 |
|
|
printk(KERN_WARNING "Unable to install interrupt handler\n");
|
| 6996 |
|
|
scsi_unregister(sh);
|
| 6997 |
|
|
return -1;
|
| 6998 |
|
|
}
|
| 6999 |
|
|
|
| 7000 |
|
|
kfree(oldha);
|
| 7001 |
|
|
ips_sh[index] = sh;
|
| 7002 |
|
|
ips_ha[index] = ha;
|
| 7003 |
|
|
scsi_set_pci_device(sh, ha->pcidev);
|
| 7004 |
|
|
|
| 7005 |
|
|
/* Store away needed values for later use */
|
| 7006 |
|
|
sh->io_port = ha->io_addr;
|
| 7007 |
|
|
sh->n_io_port = ha->io_addr ? 255 : 0;
|
| 7008 |
|
|
sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
|
| 7009 |
|
|
sh->irq = ha->irq;
|
| 7010 |
|
|
sh->sg_tablesize = sh->hostt->sg_tablesize;
|
| 7011 |
|
|
sh->can_queue = sh->hostt->can_queue;
|
| 7012 |
|
|
sh->cmd_per_lun = sh->hostt->cmd_per_lun;
|
| 7013 |
|
|
sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
|
| 7014 |
|
|
sh->use_clustering = sh->hostt->use_clustering;
|
| 7015 |
|
|
|
| 7016 |
|
|
#if LINUX_VERSION_CODE >= LinuxVersionCode(2,4,7)
|
| 7017 |
|
|
sh->max_sectors = 128;
|
| 7018 |
|
|
#endif
|
| 7019 |
|
|
|
| 7020 |
|
|
sh->max_id = ha->ntargets;
|
| 7021 |
|
|
sh->max_lun = ha->nlun;
|
| 7022 |
|
|
sh->max_channel = ha->nbus - 1;
|
| 7023 |
|
|
sh->can_queue = ha->max_cmds - 1;
|
| 7024 |
|
|
|
| 7025 |
|
|
return 0;
|
| 7026 |
|
|
}
|
| 7027 |
|
|
|
| 7028 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7029 |
|
|
/* Routine Name: ips_remove_device */
|
| 7030 |
|
|
/* */
|
| 7031 |
|
|
/* Routine Description: */
|
| 7032 |
|
|
/* Remove one Adapter ( Hot Plugging ) */
|
| 7033 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7034 |
|
|
static void
|
| 7035 |
|
|
ips_remove_device(struct pci_dev *pci_dev)
|
| 7036 |
|
|
{
|
| 7037 |
|
|
int i;
|
| 7038 |
|
|
struct Scsi_Host *sh;
|
| 7039 |
|
|
ips_ha_t *ha;
|
| 7040 |
|
|
|
| 7041 |
|
|
for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
|
| 7042 |
|
|
ha = ips_ha[i];
|
| 7043 |
|
|
if (ha) {
|
| 7044 |
|
|
if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
|
| 7045 |
|
|
(pci_dev->devfn == ha->pcidev->devfn)) {
|
| 7046 |
|
|
sh = ips_sh[i];
|
| 7047 |
|
|
ips_release(sh);
|
| 7048 |
|
|
}
|
| 7049 |
|
|
}
|
| 7050 |
|
|
}
|
| 7051 |
|
|
}
|
| 7052 |
|
|
|
| 7053 |
|
|
/****************************************************************************/
|
| 7054 |
|
|
/* */
|
| 7055 |
|
|
/* Routine Name: ips_module_init */
|
| 7056 |
|
|
/* */
|
| 7057 |
|
|
/* Routine Description: */
|
| 7058 |
|
|
/* function called on module load */
|
| 7059 |
|
|
/****************************************************************************/
|
| 7060 |
|
|
static int __init
|
| 7061 |
|
|
ips_module_init(void)
|
| 7062 |
|
|
{
|
| 7063 |
|
|
if (pci_module_init(&ips_pci_driver) < 0)
|
| 7064 |
|
|
return -ENODEV;
|
| 7065 |
|
|
ips_driver_template.module = THIS_MODULE;
|
| 7066 |
|
|
ips_order_controllers();
|
| 7067 |
|
|
if (scsi_register_module(MODULE_SCSI_HA, &ips_driver_template)) {
|
| 7068 |
|
|
pci_unregister_driver(&ips_pci_driver);
|
| 7069 |
|
|
return -ENODEV;
|
| 7070 |
|
|
}
|
| 7071 |
|
|
register_reboot_notifier(&ips_notifier);
|
| 7072 |
|
|
return 0;
|
| 7073 |
|
|
}
|
| 7074 |
|
|
|
| 7075 |
|
|
/****************************************************************************/
|
| 7076 |
|
|
/* */
|
| 7077 |
|
|
/* Routine Name: ips_module_exit */
|
| 7078 |
|
|
/* */
|
| 7079 |
|
|
/* Routine Description: */
|
| 7080 |
|
|
/* function called on module unload */
|
| 7081 |
|
|
/****************************************************************************/
|
| 7082 |
|
|
static void __exit
|
| 7083 |
|
|
ips_module_exit(void)
|
| 7084 |
|
|
{
|
| 7085 |
|
|
scsi_unregister_module(MODULE_SCSI_HA, &ips_driver_template);
|
| 7086 |
|
|
pci_unregister_driver(&ips_pci_driver);
|
| 7087 |
|
|
unregister_reboot_notifier(&ips_notifier);
|
| 7088 |
|
|
}
|
| 7089 |
|
|
|
| 7090 |
|
|
module_init(ips_module_init);
|
| 7091 |
|
|
module_exit(ips_module_exit);
|
| 7092 |
|
|
|
| 7093 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7094 |
|
|
/* Routine Name: ips_insert_device */
|
| 7095 |
|
|
/* */
|
| 7096 |
|
|
/* Routine Description: */
|
| 7097 |
|
|
/* Add One Adapter ( Hot Plug ) */
|
| 7098 |
|
|
/* */
|
| 7099 |
|
|
/* Return Value: */
|
| 7100 |
|
|
/* 0 if Successful, else non-zero */
|
| 7101 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7102 |
|
|
static int __devinit
|
| 7103 |
|
|
ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
|
| 7104 |
|
|
{
|
| 7105 |
|
|
int index;
|
| 7106 |
|
|
int rc;
|
| 7107 |
|
|
|
| 7108 |
|
|
METHOD_TRACE("ips_insert_device", 1);
|
| 7109 |
|
|
|
| 7110 |
|
|
if (pci_enable_device(pci_dev))
|
| 7111 |
|
|
return -1;
|
| 7112 |
|
|
|
| 7113 |
|
|
rc = ips_init_phase1(pci_dev, &index);
|
| 7114 |
|
|
if (rc == SUCCESS)
|
| 7115 |
|
|
rc = ips_init_phase2(index);
|
| 7116 |
|
|
|
| 7117 |
|
|
if (rc == SUCCESS)
|
| 7118 |
|
|
ips_num_controllers++;
|
| 7119 |
|
|
|
| 7120 |
|
|
ips_next_controller = ips_num_controllers;
|
| 7121 |
|
|
return rc;
|
| 7122 |
|
|
}
|
| 7123 |
|
|
|
| 7124 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7125 |
|
|
/* Routine Name: ips_init_phase1 */
|
| 7126 |
|
|
/* */
|
| 7127 |
|
|
/* Routine Description: */
|
| 7128 |
|
|
/* Adapter Initialization */
|
| 7129 |
|
|
/* */
|
| 7130 |
|
|
/* Return Value: */
|
| 7131 |
|
|
/* 0 if Successful, else non-zero */
|
| 7132 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7133 |
|
|
static int
|
| 7134 |
|
|
ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
|
| 7135 |
|
|
{
|
| 7136 |
|
|
ips_ha_t *ha;
|
| 7137 |
|
|
uint32_t io_addr;
|
| 7138 |
|
|
uint32_t mem_addr;
|
| 7139 |
|
|
uint32_t io_len;
|
| 7140 |
|
|
uint32_t mem_len;
|
| 7141 |
|
|
uint8_t revision_id;
|
| 7142 |
|
|
uint8_t bus;
|
| 7143 |
|
|
uint8_t func;
|
| 7144 |
|
|
uint8_t irq;
|
| 7145 |
|
|
uint16_t subdevice_id;
|
| 7146 |
|
|
int j;
|
| 7147 |
|
|
int index;
|
| 7148 |
|
|
dma_addr_t dma_address;
|
| 7149 |
|
|
char *ioremap_ptr;
|
| 7150 |
|
|
char *mem_ptr;
|
| 7151 |
|
|
uint32_t IsDead;
|
| 7152 |
|
|
|
| 7153 |
|
|
METHOD_TRACE("ips_init_phase1", 1);
|
| 7154 |
|
|
index = IPS_MAX_ADAPTERS;
|
| 7155 |
|
|
for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
|
| 7156 |
|
|
if (ips_ha[j] == 0) {
|
| 7157 |
|
|
index = j;
|
| 7158 |
|
|
break;
|
| 7159 |
|
|
}
|
| 7160 |
|
|
}
|
| 7161 |
|
|
|
| 7162 |
|
|
if (index >= IPS_MAX_ADAPTERS)
|
| 7163 |
|
|
return -1;
|
| 7164 |
|
|
|
| 7165 |
|
|
/* stuff that we get in dev */
|
| 7166 |
|
|
irq = pci_dev->irq;
|
| 7167 |
|
|
bus = pci_dev->bus->number;
|
| 7168 |
|
|
func = pci_dev->devfn;
|
| 7169 |
|
|
|
| 7170 |
|
|
/* Init MEM/IO addresses to 0 */
|
| 7171 |
|
|
mem_addr = 0;
|
| 7172 |
|
|
io_addr = 0;
|
| 7173 |
|
|
mem_len = 0;
|
| 7174 |
|
|
io_len = 0;
|
| 7175 |
|
|
|
| 7176 |
|
|
for (j = 0; j < 2; j++) {
|
| 7177 |
|
|
if (!pci_resource_start(pci_dev, j))
|
| 7178 |
|
|
break;
|
| 7179 |
|
|
|
| 7180 |
|
|
if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
|
| 7181 |
|
|
io_addr = pci_resource_start(pci_dev, j);
|
| 7182 |
|
|
io_len = pci_resource_len(pci_dev, j);
|
| 7183 |
|
|
} else {
|
| 7184 |
|
|
mem_addr = pci_resource_start(pci_dev, j);
|
| 7185 |
|
|
mem_len = pci_resource_len(pci_dev, j);
|
| 7186 |
|
|
}
|
| 7187 |
|
|
}
|
| 7188 |
|
|
|
| 7189 |
|
|
/* setup memory mapped area (if applicable) */
|
| 7190 |
|
|
if (mem_addr) {
|
| 7191 |
|
|
uint32_t base;
|
| 7192 |
|
|
uint32_t offs;
|
| 7193 |
|
|
|
| 7194 |
|
|
if (!request_mem_region(mem_addr, mem_len, "ips")) {
|
| 7195 |
|
|
printk(KERN_WARNING
|
| 7196 |
|
|
"Couldn't allocate IO Memory space %x len %d.\n",
|
| 7197 |
|
|
mem_addr, mem_len);
|
| 7198 |
|
|
return -1;
|
| 7199 |
|
|
}
|
| 7200 |
|
|
|
| 7201 |
|
|
base = mem_addr & PAGE_MASK;
|
| 7202 |
|
|
offs = mem_addr - base;
|
| 7203 |
|
|
ioremap_ptr = ioremap(base, PAGE_SIZE);
|
| 7204 |
|
|
mem_ptr = ioremap_ptr + offs;
|
| 7205 |
|
|
} else {
|
| 7206 |
|
|
ioremap_ptr = NULL;
|
| 7207 |
|
|
mem_ptr = NULL;
|
| 7208 |
|
|
}
|
| 7209 |
|
|
|
| 7210 |
|
|
/* setup I/O mapped area (if applicable) */
|
| 7211 |
|
|
if (io_addr) {
|
| 7212 |
|
|
if (!request_region(io_addr, io_len, "ips")) {
|
| 7213 |
|
|
printk(KERN_WARNING
|
| 7214 |
|
|
"Couldn't allocate IO space %x len %d.\n",
|
| 7215 |
|
|
io_addr, io_len);
|
| 7216 |
|
|
return -1;
|
| 7217 |
|
|
}
|
| 7218 |
|
|
}
|
| 7219 |
|
|
|
| 7220 |
|
|
/* get the revision ID */
|
| 7221 |
|
|
if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
|
| 7222 |
|
|
printk(KERN_WARNING "Can't get revision id.\n");
|
| 7223 |
|
|
return -1;
|
| 7224 |
|
|
}
|
| 7225 |
|
|
|
| 7226 |
|
|
subdevice_id = pci_dev->subsystem_device;
|
| 7227 |
|
|
|
| 7228 |
|
|
/* found a controller */
|
| 7229 |
|
|
ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
|
| 7230 |
|
|
if (ha == NULL) {
|
| 7231 |
|
|
printk(KERN_WARNING "Unable to allocate temporary ha struct\n");
|
| 7232 |
|
|
return -1;
|
| 7233 |
|
|
}
|
| 7234 |
|
|
|
| 7235 |
|
|
memset(ha, 0, sizeof (ips_ha_t));
|
| 7236 |
|
|
|
| 7237 |
|
|
ips_sh[index] = NULL;
|
| 7238 |
|
|
ips_ha[index] = ha;
|
| 7239 |
|
|
ha->active = 1;
|
| 7240 |
|
|
|
| 7241 |
|
|
/* Store info in HA structure */
|
| 7242 |
|
|
ha->irq = irq;
|
| 7243 |
|
|
ha->io_addr = io_addr;
|
| 7244 |
|
|
ha->io_len = io_len;
|
| 7245 |
|
|
ha->mem_addr = mem_addr;
|
| 7246 |
|
|
ha->mem_len = mem_len;
|
| 7247 |
|
|
ha->mem_ptr = mem_ptr;
|
| 7248 |
|
|
ha->ioremap_ptr = ioremap_ptr;
|
| 7249 |
|
|
ha->host_num = (uint32_t) index;
|
| 7250 |
|
|
ha->revision_id = revision_id;
|
| 7251 |
|
|
ha->slot_num = PCI_SLOT(pci_dev->devfn);
|
| 7252 |
|
|
ha->device_id = pci_dev->device;
|
| 7253 |
|
|
ha->subdevice_id = subdevice_id;
|
| 7254 |
|
|
ha->pcidev = pci_dev;
|
| 7255 |
|
|
|
| 7256 |
|
|
/*
|
| 7257 |
|
|
* Set the pci_dev's dma_mask. Not all adapters support 64bit
|
| 7258 |
|
|
* addressing so don't enable it if the adapter can't support
|
| 7259 |
|
|
* it! Also, don't use 64bit addressing if dma addresses
|
| 7260 |
|
|
* are guaranteed to be < 4G.
|
| 7261 |
|
|
*/
|
| 7262 |
|
|
if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
|
| 7263 |
|
|
!pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
|
| 7264 |
|
|
(ha)->flags |= IPS_HA_ENH_SG;
|
| 7265 |
|
|
} else {
|
| 7266 |
|
|
if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
|
| 7267 |
|
|
printk(KERN_WARNING "Unable to set DMA Mask\n");
|
| 7268 |
|
|
return ips_abort_init(ha, index);
|
| 7269 |
|
|
}
|
| 7270 |
|
|
}
|
| 7271 |
|
|
if(ips_cd_boot && !ips_FlashData){
|
| 7272 |
|
|
ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
|
| 7273 |
|
|
&ips_flashbusaddr);
|
| 7274 |
|
|
}
|
| 7275 |
|
|
|
| 7276 |
|
|
ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
|
| 7277 |
|
|
&ha->enq_busaddr);
|
| 7278 |
|
|
if (!ha->enq) {
|
| 7279 |
|
|
printk(KERN_WARNING
|
| 7280 |
|
|
"Unable to allocate host inquiry structure\n");
|
| 7281 |
|
|
return ips_abort_init(ha, index);
|
| 7282 |
|
|
}
|
| 7283 |
|
|
|
| 7284 |
|
|
ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
|
| 7285 |
|
|
sizeof (IPS_IO_CMD), &dma_address);
|
| 7286 |
|
|
if (!ha->adapt) {
|
| 7287 |
|
|
printk(KERN_WARNING
|
| 7288 |
|
|
"Unable to allocate host adapt & dummy structures\n");
|
| 7289 |
|
|
return ips_abort_init(ha, index);
|
| 7290 |
|
|
}
|
| 7291 |
|
|
ha->adapt->hw_status_start = dma_address;
|
| 7292 |
|
|
ha->dummy = (void *) (ha->adapt + 1);
|
| 7293 |
|
|
|
| 7294 |
|
|
ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO),
|
| 7295 |
|
|
&dma_address);
|
| 7296 |
|
|
if (!ha->logical_drive_info) {
|
| 7297 |
|
|
printk(KERN_WARNING
|
| 7298 |
|
|
"Unable to allocate host logical drive info structure\n");
|
| 7299 |
|
|
return ips_abort_init(ha, index);
|
| 7300 |
|
|
}
|
| 7301 |
|
|
ha->logical_drive_info_dma_addr = dma_address;
|
| 7302 |
|
|
|
| 7303 |
|
|
ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
|
| 7304 |
|
|
|
| 7305 |
|
|
if (!ha->conf) {
|
| 7306 |
|
|
printk(KERN_WARNING "Unable to allocate host conf structure\n");
|
| 7307 |
|
|
return ips_abort_init(ha, index);
|
| 7308 |
|
|
}
|
| 7309 |
|
|
|
| 7310 |
|
|
ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
|
| 7311 |
|
|
|
| 7312 |
|
|
if (!ha->nvram) {
|
| 7313 |
|
|
printk(KERN_WARNING
|
| 7314 |
|
|
"Unable to allocate host NVRAM structure\n");
|
| 7315 |
|
|
return ips_abort_init(ha, index);
|
| 7316 |
|
|
}
|
| 7317 |
|
|
|
| 7318 |
|
|
ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
|
| 7319 |
|
|
|
| 7320 |
|
|
if (!ha->subsys) {
|
| 7321 |
|
|
printk(KERN_WARNING
|
| 7322 |
|
|
"Unable to allocate host subsystem structure\n");
|
| 7323 |
|
|
return ips_abort_init(ha, index);
|
| 7324 |
|
|
}
|
| 7325 |
|
|
|
| 7326 |
|
|
/* the ioctl buffer is now used during adapter initialization, so its
|
| 7327 |
|
|
* successful allocation is now required */
|
| 7328 |
|
|
if (ips_ioctlsize < PAGE_SIZE)
|
| 7329 |
|
|
ips_ioctlsize = PAGE_SIZE;
|
| 7330 |
|
|
|
| 7331 |
|
|
ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
|
| 7332 |
|
|
&ha->ioctl_busaddr);
|
| 7333 |
|
|
ha->ioctl_len = ips_ioctlsize;
|
| 7334 |
|
|
|
| 7335 |
|
|
if (!ha->ioctl_data) {
|
| 7336 |
|
|
printk(KERN_WARNING "Unable to allocate IOCTL data\n");
|
| 7337 |
|
|
return ips_abort_init(ha, index);
|
| 7338 |
|
|
}
|
| 7339 |
|
|
|
| 7340 |
|
|
/*
|
| 7341 |
|
|
* Setup Functions
|
| 7342 |
|
|
*/
|
| 7343 |
|
|
ips_setup_funclist(ha);
|
| 7344 |
|
|
|
| 7345 |
|
|
if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
|
| 7346 |
|
|
/* If Morpheus appears dead, reset it */
|
| 7347 |
|
|
IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
|
| 7348 |
|
|
if (IsDead == 0xDEADBEEF) {
|
| 7349 |
|
|
ips_reset_morpheus(ha);
|
| 7350 |
|
|
}
|
| 7351 |
|
|
}
|
| 7352 |
|
|
|
| 7353 |
|
|
/*
|
| 7354 |
|
|
* Initialize the card if it isn't already
|
| 7355 |
|
|
*/
|
| 7356 |
|
|
|
| 7357 |
|
|
if (!(*ha->func.isinit) (ha)) {
|
| 7358 |
|
|
if (!(*ha->func.init) (ha)) {
|
| 7359 |
|
|
/*
|
| 7360 |
|
|
* Initialization failed
|
| 7361 |
|
|
*/
|
| 7362 |
|
|
printk(KERN_WARNING
|
| 7363 |
|
|
"Unable to initialize controller\n");
|
| 7364 |
|
|
return ips_abort_init(ha, index);
|
| 7365 |
|
|
}
|
| 7366 |
|
|
}
|
| 7367 |
|
|
|
| 7368 |
|
|
*indexPtr = index;
|
| 7369 |
|
|
return SUCCESS;
|
| 7370 |
|
|
}
|
| 7371 |
|
|
|
| 7372 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7373 |
|
|
/* Routine Name: ips_init_phase2 */
|
| 7374 |
|
|
/* */
|
| 7375 |
|
|
/* Routine Description: */
|
| 7376 |
|
|
/* Adapter Initialization Phase 2 */
|
| 7377 |
|
|
/* */
|
| 7378 |
|
|
/* Return Value: */
|
| 7379 |
|
|
/* 0 if Successful, else non-zero */
|
| 7380 |
|
|
/*---------------------------------------------------------------------------*/
|
| 7381 |
|
|
static int
|
| 7382 |
|
|
ips_init_phase2(int index)
|
| 7383 |
|
|
{
|
| 7384 |
|
|
ips_ha_t *ha;
|
| 7385 |
|
|
|
| 7386 |
|
|
ha = ips_ha[index];
|
| 7387 |
|
|
|
| 7388 |
|
|
METHOD_TRACE("ips_init_phase2", 1);
|
| 7389 |
|
|
if (!ha->active) {
|
| 7390 |
|
|
ips_ha[index] = NULL;
|
| 7391 |
|
|
return -1;
|
| 7392 |
|
|
}
|
| 7393 |
|
|
|
| 7394 |
|
|
/* Install the interrupt handler */
|
| 7395 |
|
|
if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
|
| 7396 |
|
|
printk(KERN_WARNING "Unable to install interrupt handler\n");
|
| 7397 |
|
|
return ips_abort_init(ha, index);
|
| 7398 |
|
|
}
|
| 7399 |
|
|
|
| 7400 |
|
|
/*
|
| 7401 |
|
|
* Allocate a temporary SCB for initialization
|
| 7402 |
|
|
*/
|
| 7403 |
|
|
ha->max_cmds = 1;
|
| 7404 |
|
|
if (!ips_allocatescbs(ha)) {
|
| 7405 |
|
|
printk(KERN_WARNING "Unable to allocate a CCB\n");
|
| 7406 |
|
|
free_irq(ha->irq, ha);
|
| 7407 |
|
|
return ips_abort_init(ha, index);
|
| 7408 |
|
|
}
|
| 7409 |
|
|
|
| 7410 |
|
|
if (!ips_hainit(ha)) {
|
| 7411 |
|
|
printk(KERN_WARNING "Unable to initialize controller\n");
|
| 7412 |
|
|
free_irq(ha->irq, ha);
|
| 7413 |
|
|
return ips_abort_init(ha, index);
|
| 7414 |
|
|
}
|
| 7415 |
|
|
/* Free the temporary SCB */
|
| 7416 |
|
|
ips_deallocatescbs(ha, 1);
|
| 7417 |
|
|
|
| 7418 |
|
|
/* allocate CCBs */
|
| 7419 |
|
|
if (!ips_allocatescbs(ha)) {
|
| 7420 |
|
|
printk(KERN_WARNING "Unable to allocate CCBs\n");
|
| 7421 |
|
|
free_irq(ha->irq, ha);
|
| 7422 |
|
|
return ips_abort_init(ha, index);
|
| 7423 |
|
|
}
|
| 7424 |
|
|
|
| 7425 |
|
|
return SUCCESS;
|
| 7426 |
|
|
}
|
| 7427 |
|
|
|
| 7428 |
|
|
#if LINUX_VERSION_CODE >= LinuxVersionCode(2,4,9)
|
| 7429 |
|
|
MODULE_LICENSE("GPL");
|
| 7430 |
|
|
#endif
|
| 7431 |
|
|
|
| 7432 |
|
|
/*
|
| 7433 |
|
|
* Overrides for Emacs so that we almost follow Linus's tabbing style.
|
| 7434 |
|
|
* Emacs will notice this stuff at the end of the file and automatically
|
| 7435 |
|
|
* adjust the settings for this buffer only. This must remain at the end
|
| 7436 |
|
|
* of the file.
|
| 7437 |
|
|
* ---------------------------------------------------------------------------
|
| 7438 |
|
|
* Local variables:
|
| 7439 |
|
|
* c-indent-level: 2
|
| 7440 |
|
|
* c-brace-imaginary-offset: 0
|
| 7441 |
|
|
* c-brace-offset: -2
|
| 7442 |
|
|
* c-argdecl-indent: 2
|
| 7443 |
|
|
* c-label-offset: -2
|
| 7444 |
|
|
* c-continued-statement-offset: 2
|
| 7445 |
|
|
* c-continued-brace-offset: 0
|
| 7446 |
|
|
* indent-tabs-mode: nil
|
| 7447 |
|
|
* tab-width: 8
|
| 7448 |
|
|
* End:
|
| 7449 |
|
|
*/
|
