1 |
1275 |
phoenix |
/*
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* Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
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* Basic data header
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _NSP32_H
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#define _NSP32_H
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//#define NSP32_DEBUG 9
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/*
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* VENDOR/DEVICE ID
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*/
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#define PCI_VENDOR_ID_IODATA 0x10fc
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#define PCI_VENDOR_ID_WORKBIT 0x1145
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#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
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#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
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#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
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#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
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#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
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#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
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#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
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#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
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#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
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/*
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* MODEL NAME
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*
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* note: Model number and model string must be same order.
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*/
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enum {
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MODEL_IODATA = 0,
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MODEL_KME = 1,
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MODEL_WORKBIT = 2,
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MODEL_LOGITEC = 3,
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MODEL_PCI_WORKBIT = 4,
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MODEL_PCI_LOGITEC = 5,
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MODEL_PCI_MELCO = 6,
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};
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static char * nsp32_model[] = {
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"I-O DATA CBSC-II CardBus card",
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"KME SCSI CardBus card",
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"Workbit duo SCSI CardBus card",
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"Logitec CardBus card with external ROM",
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"Workbit / I-O DATA PCI card",
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"Logitec PCI card with external ROM",
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"Melco CardBus/PCI card with external ROM",
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};
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/*
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* SCSI generic message definitions
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*/
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#define EXTENDED_SDTR_LEN 0x03
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/* Little Endian */
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typedef u32 u32_le;
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typedef u16 u16_le;
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/*
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* MACRO
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*/
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/* from X11/Intrinsic.h */
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#define NUMBER(arr) ((int) (sizeof(arr) / sizeof(arr[0])))
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#define ARRAY_OFFSET(type,num) ((int) (((type *) 0) + (num)))
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#define BIT(x) (1UL << (x))
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#ifndef MIN
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# define MIN(a,b) ((a) > (b) ? (b) : (a))
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#endif
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/*
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* BASIC Definitions
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*/
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#ifndef TRUE
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# define TRUE 1
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#endif
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#ifndef FALSE
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# define FALSE 0
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#endif
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#define ASSERT 1
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#define NEGATE 0
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/*******************/
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/* normal register */
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/*******************/
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/*
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* Don't access below register with Double Word:
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* +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
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*/
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#define IRQ_CONTROL 0x00 /* BASE+00, W, W */
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#define IRQ_STATUS 0x00 /* BASE+00, W, R */
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# define IRQSTATUS_LATCHED_MSG BIT(0)
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# define IRQSTATUS_LATCHED_IO BIT(1)
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# define IRQSTATUS_LATCHED_CD BIT(2)
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# define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
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# define IRQSTATUS_RESELECT_OCCUER BIT(4)
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# define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
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# define IRQSTATUS_SCSIRESET_IRQ BIT(6)
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# define IRQSTATUS_TIMER_IRQ BIT(7)
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# define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
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# define IRQSTATUS_PCI_IRQ BIT(9)
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# define IRQSTATUS_BMCNTERR_IRQ BIT(10)
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# define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
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# define PCI_IRQ_MASK BIT(12)
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# define TIMER_IRQ_MASK BIT(13)
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# define FIFO_IRQ_MASK BIT(14)
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# define SCSI_IRQ_MASK BIT(15)
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# define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
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TIMER_IRQ_MASK | \
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FIFO_IRQ_MASK | \
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SCSI_IRQ_MASK )
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# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
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IRQSTATUS_PHASE_CHANGE_IRQ | \
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IRQSTATUS_SCSIRESET_IRQ | \
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IRQSTATUS_TIMER_IRQ | \
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IRQSTATUS_FIFO_SHLD_IRQ | \
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IRQSTATUS_PCI_IRQ | \
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IRQSTATUS_BMCNTERR_IRQ | \
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IRQSTATUS_AUTOSCSI_IRQ )
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#define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
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#define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
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# define CB_MMIO_MODE BIT(0)
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# define CB_IO_MODE BIT(1)
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# define BM_TEST BIT(2)
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# define BM_TEST_DIR BIT(3)
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# define DUAL_EDGE_ENABLE BIT(4)
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# define NO_TRANSFER_TO_HOST BIT(5)
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# define TRANSFER_GO BIT(7)
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# define BLIEND_MODE BIT(8)
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# define BM_START BIT(9)
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# define ADVANCED_BM_WRITE BIT(10)
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# define BM_SINGLE_MODE BIT(11)
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# define FIFO_TRUE_FULL BIT(12)
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# define FIFO_TRUE_EMPTY BIT(13)
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# define ALL_COUNTER_CLR BIT(14)
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# define FIFOTEST BIT(15)
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#define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
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#define TIMER_SET 0x06 /* BASE+06, W, R/W */
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# define TIMER_CNT_MASK (0xff)
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# define TIMER_STOP BIT(8)
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158 |
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#define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
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#define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
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#define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
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# define FIFO_REST_MASK 0x1ff
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# define FIFO_EMPTY_SHLD_FLAG BIT(14)
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# define FIFO_FULL_SHLD_FLAG BIT(15)
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#define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
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# define SREQSMPLRATE_RATE0 BIT(0)
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# define SREQSMPLRATE_RATE1 BIT(1)
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# define SAMPLING_ENABLE BIT(2)
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# define SMPL_40M (0) /* 40MHz: 0-100ns/period */
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# define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
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# define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
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#define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
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# define BUSCTL_SEL BIT(0)
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# define BUSCTL_RST BIT(1)
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# define BUSCTL_DATAOUT_ENB BIT(2)
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# define BUSCTL_ATN BIT(3)
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# define BUSCTL_ACK BIT(4)
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# define BUSCTL_BSY BIT(5)
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# define AUTODIRECTION BIT(6)
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# define ACKENB BIT(7)
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#define CLR_COUNTER 0x12 /* BASE+12, B, W */
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# define ACK_COUNTER_CLR BIT(0)
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# define SREQ_COUNTER_CLR BIT(1)
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# define FIFO_HOST_POINTER_CLR BIT(2)
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# define FIFO_REST_COUNT_CLR BIT(3)
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# define BM_COUNTER_CLR BIT(4)
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# define SAVED_ACK_CLR BIT(5)
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# define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
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SREQ_COUNTER_CLR | \
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FIFO_HOST_POINTER_CLR | \
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FIFO_REST_COUNT_CLR | \
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BM_COUNTER_CLR | \
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SAVED_ACK_CLR )
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198 |
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#define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
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# define BUSMON_MSG BIT(0)
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# define BUSMON_IO BIT(1)
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# define BUSMON_CD BIT(2)
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# define BUSMON_BSY BIT(3)
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# define BUSMON_ACK BIT(4)
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# define BUSMON_REQ BIT(5)
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# define BUSMON_SEL BIT(6)
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# define BUSMON_ATN BIT(7)
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208 |
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#define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
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210 |
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#define PARITY_CONTROL 0x16 /* BASE+16, B, W */
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# define PARITY_CHECK_ENABLE BIT(0)
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# define PARITY_ERROR_CLEAR BIT(1)
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#define PARITY_STATUS 0x16 /* BASE+16, B, R */
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//# define PARITY_CHECK_ENABLE BIT(0)
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# define PARITY_ERROR_NORMAL BIT(1)
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# define PARITY_ERROR_LSB BIT(1)
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# define PARITY_ERROR_MSB BIT(2)
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218 |
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219 |
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#define RESELECT_ID 0x18 /* BASE+18, B, R */
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221 |
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#define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
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# define CLEAR_CDB_FIFO_POINTER BIT(0)
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# define AUTO_COMMAND_PHASE BIT(1)
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# define AUTOSCSI_START BIT(2)
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# define AUTOSCSI_RESTART BIT(3)
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226 |
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# define AUTO_PARAMETER BIT(4)
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227 |
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# define AUTO_ATN BIT(5)
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228 |
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# define AUTO_MSGIN_00_OR_04 BIT(6)
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# define AUTO_MSGIN_02 BIT(7)
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230 |
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# define AUTO_MSGIN_03 BIT(8)
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231 |
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232 |
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#define SET_ARBIT 0x1a /* BASE+1a, B, W */
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# define ARBIT_GO BIT(0)
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# define ARBIT_CLEAR BIT(1)
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236 |
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#define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
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237 |
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//# define ARBIT_GO BIT(0)
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238 |
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# define ARBIT_WIN BIT(1)
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239 |
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# define ARBIT_FAIL BIT(2)
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240 |
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# define AUTO_PARAMETER_VALID BIT(3)
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241 |
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# define SGT_VALID BIT(4)
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242 |
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243 |
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#define SYNC_REG 0x1c /* BASE+1c, B, R/W */
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244 |
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245 |
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#define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
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246 |
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247 |
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#define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
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248 |
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#define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
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249 |
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#define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
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250 |
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251 |
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#define SCAM_CONTROL 0x24 /* BASE+24, B, W */
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252 |
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#define SCAM_STATUS 0x24 /* BASE+24, B, R */
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253 |
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# define SCAM_MSG BIT(0)
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254 |
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# define SCAM_IO BIT(1)
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255 |
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# define SCAM_CD BIT(2)
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256 |
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# define SCAM_BSY BIT(3)
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257 |
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# define SCAM_SEL BIT(4)
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258 |
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# define SCAM_XFEROK BIT(5)
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259 |
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260 |
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#define SCAM_DATA 0x26 /* BASE+26, B, R/W */
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261 |
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# define SD0 BIT(0)
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262 |
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# define SD1 BIT(1)
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263 |
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# define SD2 BIT(2)
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264 |
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# define SD3 BIT(3)
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265 |
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# define SD4 BIT(4)
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266 |
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# define SD5 BIT(5)
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267 |
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# define SD6 BIT(6)
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268 |
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# define SD7 BIT(7)
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269 |
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270 |
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#define SACK_CNT 0x28 /* BASE+28, DW, R/W */
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271 |
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#define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
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272 |
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273 |
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#define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
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274 |
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#define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
|
275 |
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#define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
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276 |
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|
277 |
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#define BM_CNT 0x38 /* BASE+38, DW, R/W */
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278 |
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# define BM_COUNT_MASK 0x0001ffffUL
|
279 |
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# define SGTEND BIT(31) /* Last SGT marker */
|
280 |
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|
281 |
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#define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
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282 |
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#define WAIT_REG 0x40 /* Bi only */
|
283 |
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|
284 |
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#define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
|
285 |
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# define COMMAND_PHASE BIT(0)
|
286 |
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# define DATA_IN_PHASE BIT(1)
|
287 |
|
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# define DATA_OUT_PHASE BIT(2)
|
288 |
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# define MSGOUT_PHASE BIT(3)
|
289 |
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# define STATUS_PHASE BIT(4)
|
290 |
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# define ILLEGAL_PHASE BIT(5)
|
291 |
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# define BUS_FREE_OCCUER BIT(6)
|
292 |
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# define MSG_IN_OCCUER BIT(7)
|
293 |
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# define MSG_OUT_OCCUER BIT(8)
|
294 |
|
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# define SELECTION_TIMEOUT BIT(9)
|
295 |
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# define MSGIN_00_VALID BIT(10)
|
296 |
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# define MSGIN_02_VALID BIT(11)
|
297 |
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# define MSGIN_03_VALID BIT(12)
|
298 |
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# define MSGIN_04_VALID BIT(13)
|
299 |
|
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# define AUTOSCSI_BUSY BIT(15)
|
300 |
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|
301 |
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#define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
|
302 |
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|
303 |
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#define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
|
304 |
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# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
|
305 |
|
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# define MSGOUT_VALID BIT(7)
|
306 |
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|
307 |
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#define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
|
308 |
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#define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
|
309 |
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|
310 |
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#define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
|
311 |
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#define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
|
312 |
|
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#define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
|
313 |
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#define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
|
314 |
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|
315 |
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|
316 |
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/********************/
|
317 |
|
|
/* indexed register */
|
318 |
|
|
/********************/
|
319 |
|
|
|
320 |
|
|
#define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
|
321 |
|
|
# define CLOCK_2 BIT(0) /* MCLK/2 */
|
322 |
|
|
# define CLOCK_4 BIT(1) /* MCLK/4 */
|
323 |
|
|
# define PCICLK BIT(7) /* PCICLK (33MHz) */
|
324 |
|
|
|
325 |
|
|
#define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
|
326 |
|
|
# define BPWR BIT(0)
|
327 |
|
|
# define SENSE BIT(1) /* Read Only */
|
328 |
|
|
|
329 |
|
|
#define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
|
330 |
|
|
#define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
|
331 |
|
|
# define LED_ON (0)
|
332 |
|
|
# define LED_OFF BIT(0)
|
333 |
|
|
|
334 |
|
|
#define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
|
335 |
|
|
# define IRQSELECT_RESELECT_IRQ BIT(0)
|
336 |
|
|
# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
|
337 |
|
|
# define IRQSELECT_SCSIRESET_IRQ BIT(2)
|
338 |
|
|
# define IRQSELECT_TIMER_IRQ BIT(3)
|
339 |
|
|
# define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
|
340 |
|
|
# define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
|
341 |
|
|
# define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
|
342 |
|
|
# define IRQSELECT_SERR_IRQ BIT(7)
|
343 |
|
|
# define IRQSELECT_PERR_IRQ BIT(8)
|
344 |
|
|
# define IRQSELECT_BMCNTERR_IRQ BIT(9)
|
345 |
|
|
# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
|
346 |
|
|
|
347 |
|
|
#define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
|
348 |
|
|
# define OLD_MSG BIT(0)
|
349 |
|
|
# define OLD_IO BIT(1)
|
350 |
|
|
# define OLD_CD BIT(2)
|
351 |
|
|
# define OLD_BUSY BIT(3)
|
352 |
|
|
|
353 |
|
|
#define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
|
354 |
|
|
#define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
|
355 |
|
|
|
356 |
|
|
#define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
|
357 |
|
|
# define ROM_WRITE_ENB BIT(0)
|
358 |
|
|
# define IO_ACCESS_ENB BIT(1)
|
359 |
|
|
# define ROM_ADR_CLEAR BIT(2)
|
360 |
|
|
|
361 |
|
|
#define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
|
362 |
|
|
|
363 |
|
|
#define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
|
364 |
|
|
|
365 |
|
|
#define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
|
366 |
|
|
# define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
|
367 |
|
|
# define OEM1 BIT(2) /* OEM select */
|
368 |
|
|
# define OPTB BIT(3) /* KME mode select */
|
369 |
|
|
# define OPTC BIT(4) /* KME mode select */
|
370 |
|
|
# define OPTD BIT(5) /* KME mode select */
|
371 |
|
|
# define OPTE BIT(6) /* KME mode select */
|
372 |
|
|
# define OPTF BIT(7) /* Power management */
|
373 |
|
|
|
374 |
|
|
#define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
|
375 |
|
|
#define MISC_RD 0x0c
|
376 |
|
|
# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
|
377 |
|
|
# define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
|
378 |
|
|
# define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
|
379 |
|
|
# define DELAYED_BMSTART BIT(3)
|
380 |
|
|
# define MASTER_TERMINATION_SELECT BIT(4)
|
381 |
|
|
# define BMREQ_NEGATE_TIMING_SEL BIT(5)
|
382 |
|
|
# define AUTOSEL_TIMING_SEL BIT(6)
|
383 |
|
|
# define MISC_MABORT_MASK BIT(7)
|
384 |
|
|
# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
|
385 |
|
|
|
386 |
|
|
#define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
|
387 |
|
|
# define BM_CYCLE0 BIT(0)
|
388 |
|
|
# define BM_CYCLE1 BIT(1)
|
389 |
|
|
# define BM_FRAME_ASSERT_TIMING BIT(2)
|
390 |
|
|
# define BM_IRDY_ASSERT_TIMING BIT(3)
|
391 |
|
|
# define BM_SINGLE_BUS_MASTER BIT(4)
|
392 |
|
|
# define MEMRD_CMD0 BIT(5)
|
393 |
|
|
# define SGT_AUTO_PARA_MEMED_CMD BIT(6)
|
394 |
|
|
# define MEMRD_CMD1 BIT(7)
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
#define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
|
398 |
|
|
# define SREQ_EDGH_SELECT BIT(0)
|
399 |
|
|
|
400 |
|
|
#define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */ /* For hardware testing. Don't use it. */
|
401 |
|
|
# define REQCNT_UP BIT(0)
|
402 |
|
|
# define ACKCNT_UP BIT(1)
|
403 |
|
|
# define BMADR_UP BIT(4)
|
404 |
|
|
# define BMCNT_UP BIT(5)
|
405 |
|
|
# define SGT_CNT_UP BIT(7)
|
406 |
|
|
|
407 |
|
|
#define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
|
408 |
|
|
#define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
|
409 |
|
|
#define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
|
410 |
|
|
#define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
|
411 |
|
|
#define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
|
412 |
|
|
|
413 |
|
|
#define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
|
414 |
|
|
# define SROM_CTL BIT(0)
|
415 |
|
|
# define SROM_ENABLE BIT(1)
|
416 |
|
|
# define SROM_DATA BIT(2)
|
417 |
|
|
|
418 |
|
|
#define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
|
419 |
|
|
#define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
|
420 |
|
|
#define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
|
421 |
|
|
#define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
|
422 |
|
|
#define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
|
423 |
|
|
#define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
|
424 |
|
|
#define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
|
425 |
|
|
#define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
|
426 |
|
|
#define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
|
427 |
|
|
#define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
|
428 |
|
|
#define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
|
429 |
|
|
#define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
|
430 |
|
|
#define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
|
431 |
|
|
#define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
/*
|
435 |
|
|
* Useful Bus Monitor status combinations.
|
436 |
|
|
*/
|
437 |
|
|
#define BUSMON_BUS_FREE 0
|
438 |
|
|
#define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
|
439 |
|
|
#define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
|
440 |
|
|
#define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
|
441 |
|
|
#define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
|
442 |
|
|
#define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
|
443 |
|
|
#define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
|
444 |
|
|
#define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
|
445 |
|
|
#define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
|
446 |
|
|
|
447 |
|
|
#define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
|
448 |
|
|
#define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
|
449 |
|
|
#define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
|
450 |
|
|
#define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
|
451 |
|
|
#define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
|
452 |
|
|
#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
|
453 |
|
|
#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
|
454 |
|
|
|
455 |
|
|
|
456 |
|
|
/************************************************************************
|
457 |
|
|
* structure for DMA/Scatter Gather list
|
458 |
|
|
*/
|
459 |
|
|
#define NSP32_SG_SIZE SG_ALL
|
460 |
|
|
|
461 |
|
|
/* All values must be little endian */
|
462 |
|
|
typedef struct _nsp32_sgtable {
|
463 |
|
|
u32_le addr; /* transfer address */
|
464 |
|
|
u32_le len; /* transfer length. BIT(31) is for SGTEND mark */
|
465 |
|
|
} __attribute__ ((packed)) nsp32_sgtable;
|
466 |
|
|
|
467 |
|
|
/* All values must be little endian */
|
468 |
|
|
typedef struct _nsp32_sglun {
|
469 |
|
|
nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
|
470 |
|
|
} __attribute__ ((packed)) nsp32_sglun;
|
471 |
|
|
#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
|
472 |
|
|
|
473 |
|
|
/* Auto parameter mode memory map. */
|
474 |
|
|
/* All values must be little endian. */
|
475 |
|
|
typedef struct _nsp32_autoparam {
|
476 |
|
|
u8 cdb[4 * 0x10]; /* SCSI Command */
|
477 |
|
|
u32_le msgout; /* outgoing messages */
|
478 |
|
|
u8 syncreg; /* sync register value */
|
479 |
|
|
u8 ackwidth; /* ack width register value */
|
480 |
|
|
u8 target_id; /* target/host device id */
|
481 |
|
|
u8 sample_reg; /* hazard killer sampling rate */
|
482 |
|
|
u16_le command_control; /* command control register */
|
483 |
|
|
u16_le transfer_control; /* transfer control register */
|
484 |
|
|
u32_le sgt_pointer; /* SG table physical address for DMA */
|
485 |
|
|
u32_le dummy[2];
|
486 |
|
|
} __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
|
487 |
|
|
|
488 |
|
|
/*
|
489 |
|
|
* host data structure
|
490 |
|
|
*/
|
491 |
|
|
/* message in/out buffer */
|
492 |
|
|
#define MSGOUTBUF_MAX 20
|
493 |
|
|
#define MSGINBUF_MAX 20
|
494 |
|
|
|
495 |
|
|
/* flag for trans_method */
|
496 |
|
|
#define NSP32_TRANSFER_BUSMASTER BIT(0)
|
497 |
|
|
#define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
|
498 |
|
|
#define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
/*
|
502 |
|
|
* structure for connected LUN dynamic data
|
503 |
|
|
*
|
504 |
|
|
* Note: Currently tagged queuing is disabled, each nsp32_lunt holds
|
505 |
|
|
* one SCSI command and one state.
|
506 |
|
|
*/
|
507 |
|
|
#define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
|
508 |
|
|
#define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
|
509 |
|
|
|
510 |
|
|
typedef struct _nsp32_lunt {
|
511 |
|
|
Scsi_Cmnd *SCpnt; /* Current Handling Scsi_Cmnd */
|
512 |
|
|
unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
|
513 |
|
|
int msgin03; /* auto msg in 03 flag */
|
514 |
|
|
unsigned int sg_num; /* Total number of SG entries */
|
515 |
|
|
int cur_entry; /* Current SG entry number */
|
516 |
|
|
nsp32_sglun *sglun; /* sg table per lun */
|
517 |
|
|
dma_addr_t sglun_paddr; /* sglun physical address */
|
518 |
|
|
} nsp32_lunt;
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
/*
|
522 |
|
|
* SCSI TARGET/LUN definition
|
523 |
|
|
*/
|
524 |
|
|
#define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */
|
525 |
|
|
#define MAX_TARGET 8
|
526 |
|
|
#define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
|
527 |
|
|
|
528 |
|
|
|
529 |
|
|
typedef struct _nsp32_sync_table {
|
530 |
|
|
unsigned char period_num; /* period number */
|
531 |
|
|
unsigned char ackwidth; /* ack width designated by period */
|
532 |
|
|
unsigned char start_period; /* search range - start period */
|
533 |
|
|
unsigned char end_period; /* search range - end period */
|
534 |
|
|
unsigned char sample_rate; /* hazard killer parameter */
|
535 |
|
|
} nsp32_sync_table;
|
536 |
|
|
|
537 |
|
|
|
538 |
|
|
/*
|
539 |
|
|
* structure for target device static data
|
540 |
|
|
*/
|
541 |
|
|
/* flag for nsp32_target.sync_flag */
|
542 |
|
|
#define SDTR_NONE 0 /* initial state */
|
543 |
|
|
#define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
|
544 |
|
|
#define SDTR_TARGET BIT(1) /* sending SDTR from target */
|
545 |
|
|
#define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
|
546 |
|
|
|
547 |
|
|
/* syncronous period value for nsp32_target.config_max */
|
548 |
|
|
#define FAST5M 0x32
|
549 |
|
|
#define FAST10M 0x19
|
550 |
|
|
#define ULTRA20M 0x0c
|
551 |
|
|
|
552 |
|
|
/* flag for nsp32_target.{sync_offset, period} */
|
553 |
|
|
#define ASYNC_OFFSET 0 /* asynchronous transfer */
|
554 |
|
|
#define MAX_OFFSET 0xf /* synchronous transfer max offset */
|
555 |
|
|
|
556 |
|
|
/* syncreg:
|
557 |
|
|
bit:07 06 05 04 03 02 01 00
|
558 |
|
|
---PERIOD-- ---OFFSET-- */
|
559 |
|
|
#define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
|
560 |
|
|
|
561 |
|
|
typedef struct _nsp32_target {
|
562 |
|
|
unsigned char syncreg; /* value for SYNCREG */
|
563 |
|
|
unsigned char ackwidth; /* value for ACKWIDTH */
|
564 |
|
|
unsigned char period; /* sync period (0-255) */
|
565 |
|
|
unsigned char offset; /* sync offset (0-15) */
|
566 |
|
|
int sync_flag; /* SDTR_*, 0 */
|
567 |
|
|
int limit_entry; /* max speed limit entry designated
|
568 |
|
|
by EEPROM configuration */
|
569 |
|
|
unsigned char sample_reg; /* SREQ hazard killer register */
|
570 |
|
|
} nsp32_target;
|
571 |
|
|
|
572 |
|
|
typedef struct _nsp32_hw_data {
|
573 |
|
|
int IrqNumber;
|
574 |
|
|
int BaseAddress;
|
575 |
|
|
int NumAddress;
|
576 |
|
|
unsigned long MmioAddress;
|
577 |
|
|
#define NSP32_MMIO_OFFSET 0x0800
|
578 |
|
|
unsigned long MmioLength;
|
579 |
|
|
|
580 |
|
|
Scsi_Cmnd *CurrentSC;
|
581 |
|
|
|
582 |
|
|
struct pci_dev *Pci;
|
583 |
|
|
const struct pci_device_id *pci_devid;
|
584 |
|
|
struct Scsi_Host *Host;
|
585 |
|
|
spinlock_t Lock;
|
586 |
|
|
|
587 |
|
|
char info_str[100];
|
588 |
|
|
|
589 |
|
|
/* allocated memory region */
|
590 |
|
|
nsp32_sglun *sg_list; /* sglist virtuxal address */
|
591 |
|
|
dma_addr_t sg_paddr; /* physical address of hw_sg_table */
|
592 |
|
|
nsp32_autoparam *autoparam; /* auto parameter transfer region */
|
593 |
|
|
dma_addr_t auto_paddr; /* physical address of autoparam */
|
594 |
|
|
int cur_entry; /* current sgt entry */
|
595 |
|
|
|
596 |
|
|
/* target/LUN */
|
597 |
|
|
nsp32_lunt *cur_lunt; /* Current connected LUN table */
|
598 |
|
|
nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
|
599 |
|
|
|
600 |
|
|
nsp32_target *cur_target; /* Current connected SCSI ID */
|
601 |
|
|
nsp32_target target[MAX_TARGET]; /* SCSI ID */
|
602 |
|
|
int cur_id; /* Current connected target ID */
|
603 |
|
|
int cur_lun; /* Current connected target LUN */
|
604 |
|
|
|
605 |
|
|
/* behavior setting parameters */
|
606 |
|
|
int trans_method; /* transfer method flag */
|
607 |
|
|
int resettime; /* Reset time */
|
608 |
|
|
int clock; /* clock dividing flag */
|
609 |
|
|
nsp32_sync_table *synct; /* sync_table determined by clock */
|
610 |
|
|
int syncnum; /* the max number of synct element */
|
611 |
|
|
|
612 |
|
|
/* message buffer */
|
613 |
|
|
unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
|
614 |
|
|
char msgout_len; /* msgoutbuf length */
|
615 |
|
|
unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
|
616 |
|
|
char msgin_len; /* msginbuf length */
|
617 |
|
|
|
618 |
|
|
#ifdef CONFIG_PM
|
619 |
|
|
u32 PciState[16]; /* save PCI state to this area */
|
620 |
|
|
#endif
|
621 |
|
|
} nsp32_hw_data;
|
622 |
|
|
|
623 |
|
|
/*
|
624 |
|
|
* TIME definition
|
625 |
|
|
*/
|
626 |
|
|
#define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
|
627 |
|
|
minimum is 25us) */
|
628 |
|
|
#define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
|
629 |
|
|
(25.6us/1unit) */
|
630 |
|
|
#define ARBIT_TIMEOUT_TIME 100 /* 100us */
|
631 |
|
|
#define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
|
632 |
|
|
or negation, 10000us == 10ms */
|
633 |
|
|
|
634 |
|
|
/**************************************************************************
|
635 |
|
|
* Compatibility functions
|
636 |
|
|
*/
|
637 |
|
|
|
638 |
|
|
/* for Kernel 2.4 */
|
639 |
|
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
|
640 |
|
|
# define scsi_register_host(template) scsi_register_module(MODULE_SCSI_HA, template)
|
641 |
|
|
# define scsi_unregister_host(template) scsi_unregister_module(MODULE_SCSI_HA, template)
|
642 |
|
|
# define scsi_host_put(host) scsi_unregister(host)
|
643 |
|
|
# define pci_name(pci_dev) ((pci_dev)->slot_name)
|
644 |
|
|
|
645 |
|
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23))
|
646 |
|
|
typedef void irqreturn_t;
|
647 |
|
|
# define IRQ_NONE /* */
|
648 |
|
|
# define IRQ_HANDLED /* */
|
649 |
|
|
# define IRQ_RETVAL(x) /* */
|
650 |
|
|
#endif
|
651 |
|
|
|
652 |
|
|
/* This is ad-hoc version of scsi_host_get_next() */
|
653 |
|
|
static inline struct Scsi_Host *scsi_host_get_next(struct Scsi_Host *host)
|
654 |
|
|
{
|
655 |
|
|
if (host == NULL) {
|
656 |
|
|
return scsi_hostlist;
|
657 |
|
|
} else {
|
658 |
|
|
return host->next;
|
659 |
|
|
}
|
660 |
|
|
}
|
661 |
|
|
|
662 |
|
|
/* This is ad-hoc version of scsi_host_hn_get() */
|
663 |
|
|
static inline struct Scsi_Host *scsi_host_hn_get(unsigned short hostno)
|
664 |
|
|
{
|
665 |
|
|
struct Scsi_Host *host;
|
666 |
|
|
|
667 |
|
|
for (host = scsi_host_get_next(NULL); host != NULL;
|
668 |
|
|
host = scsi_host_get_next(host)) {
|
669 |
|
|
if (host->host_no == hostno) {
|
670 |
|
|
break;
|
671 |
|
|
}
|
672 |
|
|
}
|
673 |
|
|
|
674 |
|
|
return host;
|
675 |
|
|
}
|
676 |
|
|
|
677 |
|
|
/* host spin lock */
|
678 |
|
|
# define HOST_LOCK (&io_request_lock)
|
679 |
|
|
#endif
|
680 |
|
|
|
681 |
|
|
/* for Kernel 2.6 */
|
682 |
|
|
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
|
683 |
|
|
# define __devinitdata /* */
|
684 |
|
|
|
685 |
|
|
/* host spin lock */
|
686 |
|
|
# define HOST_LOCK (data->Host->host_lock)
|
687 |
|
|
#endif
|
688 |
|
|
|
689 |
|
|
#endif /* _NSP32_H */
|
690 |
|
|
/* end */
|