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1275 |
phoenix |
/*
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* QLogic ISP1020 Intelligent SCSI Processor Driver (PCI)
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* Written by Erik H. Moe, ehm@cris.com
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* Copyright 1995, Erik H. Moe
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* Copyright 1996, 1997 Michael A. Griffith <grif@acm.org>
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* Copyright 2000, Jayson C. Vantuyl <vantuyl@csc.smsu.edu>
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* and Bryon W. Roche <bryon@csc.smsu.edu>
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*
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* 64-bit addressing added by Kanoj Sarcar <kanoj@sgi.com>
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* and Leo Dagum <dagum@sgi.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/blk.h>
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/unistd.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/byteorder.h>
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#include "sd.h"
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#include "hosts.h"
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#include "qlogicisp.h"
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/* Configuration section *****************************************************/
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/* Set the following macro to 1 to reload the ISP1020's firmware. This is
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the latest firmware provided by QLogic. This may be an earlier/later
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revision than supplied by your board. */
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#define RELOAD_FIRMWARE 1
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/* Set the following macro to 1 to reload the ISP1020's defaults from nvram.
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If you are not sure of your settings, leave this alone, the driver will
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use a set of 'safe' defaults */
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#define USE_NVRAM_DEFAULTS 0
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/* Macros used for debugging */
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#define DEBUG_ISP1020 0
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#define DEBUG_ISP1020_INTR 0
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#define DEBUG_ISP1020_SETUP 0
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#define TRACE_ISP 0
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#define DEFAULT_LOOP_COUNT 1000000
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/* End Configuration section *************************************************/
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#include <linux/module.h>
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#if TRACE_ISP
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# define TRACE_BUF_LEN (32*1024)
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struct {
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u_long next;
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struct {
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u_long time;
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u_int index;
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u_int addr;
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u_char * name;
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} buf[TRACE_BUF_LEN];
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} trace;
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#define TRACE(w, i, a) \
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{ \
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unsigned long flags; \
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\
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save_flags(flags); \
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cli(); \
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trace.buf[trace.next].name = (w); \
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trace.buf[trace.next].time = jiffies; \
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trace.buf[trace.next].index = (i); \
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trace.buf[trace.next].addr = (long) (a); \
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trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1); \
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restore_flags(flags); \
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}
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#else
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# define TRACE(w, i, a)
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#endif
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#if DEBUG_ISP1020
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#define ENTER(x) printk("isp1020 : entering %s()\n", x);
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#define LEAVE(x) printk("isp1020 : leaving %s()\n", x);
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#define DEBUG(x) x
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#else
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#define ENTER(x)
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#define LEAVE(x)
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#define DEBUG(x)
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#endif /* DEBUG_ISP1020 */
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#if DEBUG_ISP1020_INTR
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#define ENTER_INTR(x) printk("isp1020 : entering %s()\n", x);
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#define LEAVE_INTR(x) printk("isp1020 : leaving %s()\n", x);
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#define DEBUG_INTR(x) x
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#else
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#define ENTER_INTR(x)
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#define LEAVE_INTR(x)
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#define DEBUG_INTR(x)
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#endif /* DEBUG ISP1020_INTR */
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#define ISP1020_REV_ID 1
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#define MAX_TARGETS 16
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#define MAX_LUNS 8
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/* host configuration and control registers */
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#define HOST_HCCR 0xc0 /* host command and control */
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/* pci bus interface registers */
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#define PCI_ID_LOW 0x00 /* vendor id */
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#define PCI_ID_HIGH 0x02 /* device id */
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#define ISP_CFG0 0x04 /* configuration register #0 */
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#define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
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#define ISP_CFG0_1020 0x0001 /* ISP1020 */
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#define ISP_CFG0_1020A 0x0002 /* ISP1020A */
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#define ISP_CFG0_1040 0x0003 /* ISP1040 */
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#define ISP_CFG0_1040A 0x0004 /* ISP1040A */
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#define ISP_CFG0_1040B 0x0005 /* ISP1040B */
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#define ISP_CFG0_1040C 0x0006 /* ISP1040C */
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#define ISP_CFG1 0x06 /* configuration register #1 */
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#define ISP_CFG1_F128 0x0040 /* 128-byte FIFO threshold */
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#define ISP_CFG1_F64 0x0030 /* 128-byte FIFO threshold */
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#define ISP_CFG1_F32 0x0020 /* 128-byte FIFO threshold */
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#define ISP_CFG1_F16 0x0010 /* 128-byte FIFO threshold */
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#define ISP_CFG1_BENAB 0x0004 /* Global Bus burst enable */
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#define ISP_CFG1_SXP 0x0001 /* SXP register select */
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#define PCI_INTF_CTL 0x08 /* pci interface control */
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#define PCI_INTF_STS 0x0a /* pci interface status */
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#define PCI_SEMAPHORE 0x0c /* pci semaphore */
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#define PCI_NVRAM 0x0e /* pci nvram interface */
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#define CDMA_CONF 0x20 /* Command DMA Config */
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#define DDMA_CONF 0x40 /* Data DMA Config */
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#define DMA_CONF_SENAB 0x0008 /* SXP to DMA Data enable */
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#define DMA_CONF_RIRQ 0x0004 /* RISC interrupt enable */
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#define DMA_CONF_BENAB 0x0002 /* Bus burst enable */
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#define DMA_CONF_DIR 0x0001 /* DMA direction (0=fifo->host 1=host->fifo) */
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/* mailbox registers */
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#define MBOX0 0x70 /* mailbox 0 */
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#define MBOX1 0x72 /* mailbox 1 */
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#define MBOX2 0x74 /* mailbox 2 */
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#define MBOX3 0x76 /* mailbox 3 */
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#define MBOX4 0x78 /* mailbox 4 */
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#define MBOX5 0x7a /* mailbox 5 */
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#define MBOX6 0x7c /* mailbox 6 */
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#define MBOX7 0x7e /* mailbox 7 */
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/* mailbox command complete status codes */
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#define MBOX_COMMAND_COMPLETE 0x4000
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#define INVALID_COMMAND 0x4001
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#define HOST_INTERFACE_ERROR 0x4002
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#define TEST_FAILED 0x4003
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#define COMMAND_ERROR 0x4005
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#define COMMAND_PARAM_ERROR 0x4006
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/* async event status codes */
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#define ASYNC_SCSI_BUS_RESET 0x8001
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#define SYSTEM_ERROR 0x8002
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#define REQUEST_TRANSFER_ERROR 0x8003
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#define RESPONSE_TRANSFER_ERROR 0x8004
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#define REQUEST_QUEUE_WAKEUP 0x8005
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#define EXECUTION_TIMEOUT_RESET 0x8006
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#ifdef CONFIG_QL_ISP_A64
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#define IOCB_SEGS 2
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#define CONTINUATION_SEGS 5
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#define MAX_CONTINUATION_ENTRIES 254
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#else
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#define IOCB_SEGS 4
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#define CONTINUATION_SEGS 7
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#endif /* CONFIG_QL_ISP_A64 */
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struct Entry_header {
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u_char entry_type;
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u_char entry_cnt;
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u_char sys_def_1;
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u_char flags;
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};
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/* entry header type commands */
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#ifdef CONFIG_QL_ISP_A64
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#define ENTRY_COMMAND 9
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#define ENTRY_CONTINUATION 0xa
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#else
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#define ENTRY_COMMAND 1
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#define ENTRY_CONTINUATION 2
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#endif /* CONFIG_QL_ISP_A64 */
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#define ENTRY_STATUS 3
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#define ENTRY_MARKER 4
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#define ENTRY_EXTENDED_COMMAND 5
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| 213 |
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/* entry header flag definitions */
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#define EFLAG_CONTINUATION 1
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#define EFLAG_BUSY 2
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#define EFLAG_BAD_HEADER 4
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#define EFLAG_BAD_PAYLOAD 8
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| 219 |
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struct dataseg {
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| 220 |
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u_int d_base;
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#ifdef CONFIG_QL_ISP_A64
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u_int d_base_hi;
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#endif
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| 224 |
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u_int d_count;
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};
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struct Command_Entry {
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struct Entry_header hdr;
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u_int handle;
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u_char target_lun;
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u_char target_id;
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u_short cdb_length;
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u_short control_flags;
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u_short rsvd;
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u_short time_out;
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u_short segment_cnt;
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| 237 |
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u_char cdb[12];
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| 238 |
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#ifdef CONFIG_QL_ISP_A64
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u_int rsvd1;
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u_int rsvd2;
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#endif
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struct dataseg dataseg[IOCB_SEGS];
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| 243 |
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};
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| 244 |
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| 245 |
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/* command entry control flag definitions */
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| 246 |
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#define CFLAG_NODISC 0x01
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#define CFLAG_HEAD_TAG 0x02
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#define CFLAG_ORDERED_TAG 0x04
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| 249 |
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#define CFLAG_SIMPLE_TAG 0x08
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| 250 |
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#define CFLAG_TAR_RTN 0x10
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| 251 |
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#define CFLAG_READ 0x20
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| 252 |
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#define CFLAG_WRITE 0x40
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| 253 |
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| 254 |
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struct Ext_Command_Entry {
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| 255 |
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struct Entry_header hdr;
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| 256 |
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u_int handle;
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| 257 |
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u_char target_lun;
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| 258 |
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u_char target_id;
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| 259 |
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u_short cdb_length;
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| 260 |
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u_short control_flags;
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| 261 |
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u_short rsvd;
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| 262 |
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u_short time_out;
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| 263 |
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u_short segment_cnt;
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| 264 |
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u_char cdb[44];
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| 265 |
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};
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| 266 |
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| 267 |
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struct Continuation_Entry {
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| 268 |
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struct Entry_header hdr;
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| 269 |
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#ifndef CONFIG_QL_ISP_A64
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| 270 |
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u_int reserved;
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| 271 |
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#endif
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| 272 |
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struct dataseg dataseg[CONTINUATION_SEGS];
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| 273 |
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};
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| 274 |
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| 275 |
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struct Marker_Entry {
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| 276 |
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struct Entry_header hdr;
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| 277 |
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u_int reserved;
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| 278 |
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u_char target_lun;
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| 279 |
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u_char target_id;
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| 280 |
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u_char modifier;
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| 281 |
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u_char rsvd;
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| 282 |
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u_char rsvds[52];
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| 283 |
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};
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| 284 |
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| 285 |
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/* marker entry modifier definitions */
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| 286 |
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#define SYNC_DEVICE 0
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| 287 |
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#define SYNC_TARGET 1
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| 288 |
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#define SYNC_ALL 2
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| 289 |
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| 290 |
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struct Status_Entry {
|
| 291 |
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struct Entry_header hdr;
|
| 292 |
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u_int handle;
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| 293 |
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u_short scsi_status;
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| 294 |
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u_short completion_status;
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| 295 |
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u_short state_flags;
|
| 296 |
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u_short status_flags;
|
| 297 |
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u_short time;
|
| 298 |
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u_short req_sense_len;
|
| 299 |
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u_int residual;
|
| 300 |
|
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u_char rsvd[8];
|
| 301 |
|
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u_char req_sense_data[32];
|
| 302 |
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};
|
| 303 |
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| 304 |
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/* status entry completion status definitions */
|
| 305 |
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#define CS_COMPLETE 0x0000
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| 306 |
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#define CS_INCOMPLETE 0x0001
|
| 307 |
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#define CS_DMA_ERROR 0x0002
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| 308 |
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#define CS_TRANSPORT_ERROR 0x0003
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| 309 |
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#define CS_RESET_OCCURRED 0x0004
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| 310 |
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#define CS_ABORTED 0x0005
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| 311 |
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#define CS_TIMEOUT 0x0006
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| 312 |
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#define CS_DATA_OVERRUN 0x0007
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| 313 |
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#define CS_COMMAND_OVERRUN 0x0008
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| 314 |
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#define CS_STATUS_OVERRUN 0x0009
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| 315 |
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#define CS_BAD_MESSAGE 0x000a
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| 316 |
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#define CS_NO_MESSAGE_OUT 0x000b
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| 317 |
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#define CS_EXT_ID_FAILED 0x000c
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| 318 |
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#define CS_IDE_MSG_FAILED 0x000d
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| 319 |
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#define CS_ABORT_MSG_FAILED 0x000e
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| 320 |
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#define CS_REJECT_MSG_FAILED 0x000f
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| 321 |
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#define CS_NOP_MSG_FAILED 0x0010
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| 322 |
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#define CS_PARITY_ERROR_MSG_FAILED 0x0011
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| 323 |
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#define CS_DEVICE_RESET_MSG_FAILED 0x0012
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| 324 |
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#define CS_ID_MSG_FAILED 0x0013
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| 325 |
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#define CS_UNEXP_BUS_FREE 0x0014
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| 326 |
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#define CS_DATA_UNDERRUN 0x0015
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| 327 |
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| 328 |
|
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/* status entry state flag definitions */
|
| 329 |
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#define SF_GOT_BUS 0x0100
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| 330 |
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#define SF_GOT_TARGET 0x0200
|
| 331 |
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#define SF_SENT_CDB 0x0400
|
| 332 |
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#define SF_TRANSFERRED_DATA 0x0800
|
| 333 |
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#define SF_GOT_STATUS 0x1000
|
| 334 |
|
|
#define SF_GOT_SENSE 0x2000
|
| 335 |
|
|
|
| 336 |
|
|
/* status entry status flag definitions */
|
| 337 |
|
|
#define STF_DISCONNECT 0x0001
|
| 338 |
|
|
#define STF_SYNCHRONOUS 0x0002
|
| 339 |
|
|
#define STF_PARITY_ERROR 0x0004
|
| 340 |
|
|
#define STF_BUS_RESET 0x0008
|
| 341 |
|
|
#define STF_DEVICE_RESET 0x0010
|
| 342 |
|
|
#define STF_ABORTED 0x0020
|
| 343 |
|
|
#define STF_TIMEOUT 0x0040
|
| 344 |
|
|
#define STF_NEGOTIATION 0x0080
|
| 345 |
|
|
|
| 346 |
|
|
/* interface control commands */
|
| 347 |
|
|
#define ISP_RESET 0x0001
|
| 348 |
|
|
#define ISP_EN_INT 0x0002
|
| 349 |
|
|
#define ISP_EN_RISC 0x0004
|
| 350 |
|
|
|
| 351 |
|
|
/* host control commands */
|
| 352 |
|
|
#define HCCR_NOP 0x0000
|
| 353 |
|
|
#define HCCR_RESET 0x1000
|
| 354 |
|
|
#define HCCR_PAUSE 0x2000
|
| 355 |
|
|
#define HCCR_RELEASE 0x3000
|
| 356 |
|
|
#define HCCR_SINGLE_STEP 0x4000
|
| 357 |
|
|
#define HCCR_SET_HOST_INTR 0x5000
|
| 358 |
|
|
#define HCCR_CLEAR_HOST_INTR 0x6000
|
| 359 |
|
|
#define HCCR_CLEAR_RISC_INTR 0x7000
|
| 360 |
|
|
#define HCCR_BP_ENABLE 0x8000
|
| 361 |
|
|
#define HCCR_BIOS_DISABLE 0x9000
|
| 362 |
|
|
#define HCCR_TEST_MODE 0xf000
|
| 363 |
|
|
|
| 364 |
|
|
#define RISC_BUSY 0x0004
|
| 365 |
|
|
|
| 366 |
|
|
/* mailbox commands */
|
| 367 |
|
|
#define MBOX_NO_OP 0x0000
|
| 368 |
|
|
#define MBOX_LOAD_RAM 0x0001
|
| 369 |
|
|
#define MBOX_EXEC_FIRMWARE 0x0002
|
| 370 |
|
|
#define MBOX_DUMP_RAM 0x0003
|
| 371 |
|
|
#define MBOX_WRITE_RAM_WORD 0x0004
|
| 372 |
|
|
#define MBOX_READ_RAM_WORD 0x0005
|
| 373 |
|
|
#define MBOX_MAILBOX_REG_TEST 0x0006
|
| 374 |
|
|
#define MBOX_VERIFY_CHECKSUM 0x0007
|
| 375 |
|
|
#define MBOX_ABOUT_FIRMWARE 0x0008
|
| 376 |
|
|
#define MBOX_CHECK_FIRMWARE 0x000e
|
| 377 |
|
|
#define MBOX_INIT_REQ_QUEUE 0x0010
|
| 378 |
|
|
#define MBOX_INIT_RES_QUEUE 0x0011
|
| 379 |
|
|
#define MBOX_EXECUTE_IOCB 0x0012
|
| 380 |
|
|
#define MBOX_WAKE_UP 0x0013
|
| 381 |
|
|
#define MBOX_STOP_FIRMWARE 0x0014
|
| 382 |
|
|
#define MBOX_ABORT 0x0015
|
| 383 |
|
|
#define MBOX_ABORT_DEVICE 0x0016
|
| 384 |
|
|
#define MBOX_ABORT_TARGET 0x0017
|
| 385 |
|
|
#define MBOX_BUS_RESET 0x0018
|
| 386 |
|
|
#define MBOX_STOP_QUEUE 0x0019
|
| 387 |
|
|
#define MBOX_START_QUEUE 0x001a
|
| 388 |
|
|
#define MBOX_SINGLE_STEP_QUEUE 0x001b
|
| 389 |
|
|
#define MBOX_ABORT_QUEUE 0x001c
|
| 390 |
|
|
#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
|
| 391 |
|
|
#define MBOX_GET_FIRMWARE_STATUS 0x001f
|
| 392 |
|
|
#define MBOX_GET_INIT_SCSI_ID 0x0020
|
| 393 |
|
|
#define MBOX_GET_SELECT_TIMEOUT 0x0021
|
| 394 |
|
|
#define MBOX_GET_RETRY_COUNT 0x0022
|
| 395 |
|
|
#define MBOX_GET_TAG_AGE_LIMIT 0x0023
|
| 396 |
|
|
#define MBOX_GET_CLOCK_RATE 0x0024
|
| 397 |
|
|
#define MBOX_GET_ACT_NEG_STATE 0x0025
|
| 398 |
|
|
#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
|
| 399 |
|
|
#define MBOX_GET_PCI_PARAMS 0x0027
|
| 400 |
|
|
#define MBOX_GET_TARGET_PARAMS 0x0028
|
| 401 |
|
|
#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
|
| 402 |
|
|
#define MBOX_SET_INIT_SCSI_ID 0x0030
|
| 403 |
|
|
#define MBOX_SET_SELECT_TIMEOUT 0x0031
|
| 404 |
|
|
#define MBOX_SET_RETRY_COUNT 0x0032
|
| 405 |
|
|
#define MBOX_SET_TAG_AGE_LIMIT 0x0033
|
| 406 |
|
|
#define MBOX_SET_CLOCK_RATE 0x0034
|
| 407 |
|
|
#define MBOX_SET_ACTIVE_NEG_STATE 0x0035
|
| 408 |
|
|
#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
|
| 409 |
|
|
#define MBOX_SET_PCI_CONTROL_PARAMS 0x0037
|
| 410 |
|
|
#define MBOX_SET_TARGET_PARAMS 0x0038
|
| 411 |
|
|
#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
|
| 412 |
|
|
#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
|
| 413 |
|
|
#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
|
| 414 |
|
|
#define MBOX_EXEC_BIOS_IOCB 0x0042
|
| 415 |
|
|
|
| 416 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 417 |
|
|
#define MBOX_CMD_INIT_REQUEST_QUEUE_64 0x0052
|
| 418 |
|
|
#define MBOX_CMD_INIT_RESPONSE_QUEUE_64 0x0053
|
| 419 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 420 |
|
|
|
| 421 |
|
|
#include "qlogicisp_asm.c"
|
| 422 |
|
|
|
| 423 |
|
|
#define PACKB(a, b) (((a)<<4)|(b))
|
| 424 |
|
|
|
| 425 |
|
|
static const u_char mbox_param[] = {
|
| 426 |
|
|
PACKB(1, 1), /* MBOX_NO_OP */
|
| 427 |
|
|
PACKB(5, 5), /* MBOX_LOAD_RAM */
|
| 428 |
|
|
PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
|
| 429 |
|
|
PACKB(5, 5), /* MBOX_DUMP_RAM */
|
| 430 |
|
|
PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
|
| 431 |
|
|
PACKB(2, 3), /* MBOX_READ_RAM_WORD */
|
| 432 |
|
|
PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
|
| 433 |
|
|
PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
|
| 434 |
|
|
PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
|
| 435 |
|
|
PACKB(0, 0), /* 0x0009 */
|
| 436 |
|
|
PACKB(0, 0), /* 0x000a */
|
| 437 |
|
|
PACKB(0, 0), /* 0x000b */
|
| 438 |
|
|
PACKB(0, 0), /* 0x000c */
|
| 439 |
|
|
PACKB(0, 0), /* 0x000d */
|
| 440 |
|
|
PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
|
| 441 |
|
|
PACKB(0, 0), /* 0x000f */
|
| 442 |
|
|
PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
|
| 443 |
|
|
PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
|
| 444 |
|
|
PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
|
| 445 |
|
|
PACKB(2, 2), /* MBOX_WAKE_UP */
|
| 446 |
|
|
PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
|
| 447 |
|
|
PACKB(4, 4), /* MBOX_ABORT */
|
| 448 |
|
|
PACKB(2, 2), /* MBOX_ABORT_DEVICE */
|
| 449 |
|
|
PACKB(3, 3), /* MBOX_ABORT_TARGET */
|
| 450 |
|
|
PACKB(2, 2), /* MBOX_BUS_RESET */
|
| 451 |
|
|
PACKB(2, 3), /* MBOX_STOP_QUEUE */
|
| 452 |
|
|
PACKB(2, 3), /* MBOX_START_QUEUE */
|
| 453 |
|
|
PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
|
| 454 |
|
|
PACKB(2, 3), /* MBOX_ABORT_QUEUE */
|
| 455 |
|
|
PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
|
| 456 |
|
|
PACKB(0, 0), /* 0x001e */
|
| 457 |
|
|
PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
|
| 458 |
|
|
PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
|
| 459 |
|
|
PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
|
| 460 |
|
|
PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
|
| 461 |
|
|
PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
|
| 462 |
|
|
PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
|
| 463 |
|
|
PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
|
| 464 |
|
|
PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
|
| 465 |
|
|
PACKB(1, 3), /* MBOX_GET_PCI_PARAMS */
|
| 466 |
|
|
PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
|
| 467 |
|
|
PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
|
| 468 |
|
|
PACKB(0, 0), /* 0x002a */
|
| 469 |
|
|
PACKB(0, 0), /* 0x002b */
|
| 470 |
|
|
PACKB(0, 0), /* 0x002c */
|
| 471 |
|
|
PACKB(0, 0), /* 0x002d */
|
| 472 |
|
|
PACKB(0, 0), /* 0x002e */
|
| 473 |
|
|
PACKB(0, 0), /* 0x002f */
|
| 474 |
|
|
PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
|
| 475 |
|
|
PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
|
| 476 |
|
|
PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
|
| 477 |
|
|
PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
|
| 478 |
|
|
PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
|
| 479 |
|
|
PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
|
| 480 |
|
|
PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
|
| 481 |
|
|
PACKB(3, 3), /* MBOX_SET_PCI_CONTROL_PARAMS */
|
| 482 |
|
|
PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
|
| 483 |
|
|
PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
|
| 484 |
|
|
PACKB(0, 0), /* 0x003a */
|
| 485 |
|
|
PACKB(0, 0), /* 0x003b */
|
| 486 |
|
|
PACKB(0, 0), /* 0x003c */
|
| 487 |
|
|
PACKB(0, 0), /* 0x003d */
|
| 488 |
|
|
PACKB(0, 0), /* 0x003e */
|
| 489 |
|
|
PACKB(0, 0), /* 0x003f */
|
| 490 |
|
|
PACKB(1, 2), /* MBOX_RETURN_BIOS_BLOCK_ADDR */
|
| 491 |
|
|
PACKB(6, 1), /* MBOX_WRITE_FOUR_RAM_WORDS */
|
| 492 |
|
|
PACKB(2, 3) /* MBOX_EXEC_BIOS_IOCB */
|
| 493 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 494 |
|
|
,PACKB(0, 0), /* 0x0043 */
|
| 495 |
|
|
PACKB(0, 0), /* 0x0044 */
|
| 496 |
|
|
PACKB(0, 0), /* 0x0045 */
|
| 497 |
|
|
PACKB(0, 0), /* 0x0046 */
|
| 498 |
|
|
PACKB(0, 0), /* 0x0047 */
|
| 499 |
|
|
PACKB(0, 0), /* 0x0048 */
|
| 500 |
|
|
PACKB(0, 0), /* 0x0049 */
|
| 501 |
|
|
PACKB(0, 0), /* 0x004a */
|
| 502 |
|
|
PACKB(0, 0), /* 0x004b */
|
| 503 |
|
|
PACKB(0, 0), /* 0x004c */
|
| 504 |
|
|
PACKB(0, 0), /* 0x004d */
|
| 505 |
|
|
PACKB(0, 0), /* 0x004e */
|
| 506 |
|
|
PACKB(0, 0), /* 0x004f */
|
| 507 |
|
|
PACKB(0, 0), /* 0x0050 */
|
| 508 |
|
|
PACKB(0, 0), /* 0x0051 */
|
| 509 |
|
|
PACKB(8, 8), /* MBOX_CMD_INIT_REQUEST_QUEUE_64 (0x0052) */
|
| 510 |
|
|
PACKB(8, 8) /* MBOX_CMD_INIT_RESPONSE_QUEUE_64 (0x0053) */
|
| 511 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 512 |
|
|
};
|
| 513 |
|
|
|
| 514 |
|
|
#define MAX_MBOX_COMMAND (sizeof(mbox_param)/sizeof(u_short))
|
| 515 |
|
|
|
| 516 |
|
|
struct host_param {
|
| 517 |
|
|
u_short fifo_threshold;
|
| 518 |
|
|
u_short host_adapter_enable;
|
| 519 |
|
|
u_short initiator_scsi_id;
|
| 520 |
|
|
u_short bus_reset_delay;
|
| 521 |
|
|
u_short retry_count;
|
| 522 |
|
|
u_short retry_delay;
|
| 523 |
|
|
u_short async_data_setup_time;
|
| 524 |
|
|
u_short req_ack_active_negation;
|
| 525 |
|
|
u_short data_line_active_negation;
|
| 526 |
|
|
u_short data_dma_burst_enable;
|
| 527 |
|
|
u_short command_dma_burst_enable;
|
| 528 |
|
|
u_short tag_aging;
|
| 529 |
|
|
u_short selection_timeout;
|
| 530 |
|
|
u_short max_queue_depth;
|
| 531 |
|
|
};
|
| 532 |
|
|
|
| 533 |
|
|
/*
|
| 534 |
|
|
* Device Flags:
|
| 535 |
|
|
*
|
| 536 |
|
|
* Bit Name
|
| 537 |
|
|
* ---------
|
| 538 |
|
|
* 7 Disconnect Privilege
|
| 539 |
|
|
* 6 Parity Checking
|
| 540 |
|
|
* 5 Wide Data Transfers
|
| 541 |
|
|
* 4 Synchronous Data Transfers
|
| 542 |
|
|
* 3 Tagged Queuing
|
| 543 |
|
|
* 2 Automatic Request Sense
|
| 544 |
|
|
* 1 Stop Queue on Check Condition
|
| 545 |
|
|
* 0 Renegotiate on Error
|
| 546 |
|
|
*/
|
| 547 |
|
|
|
| 548 |
|
|
struct dev_param {
|
| 549 |
|
|
u_short device_flags;
|
| 550 |
|
|
u_short execution_throttle;
|
| 551 |
|
|
u_short synchronous_period;
|
| 552 |
|
|
u_short synchronous_offset;
|
| 553 |
|
|
u_short device_enable;
|
| 554 |
|
|
u_short reserved; /* pad */
|
| 555 |
|
|
};
|
| 556 |
|
|
|
| 557 |
|
|
/*
|
| 558 |
|
|
* The result queue can be quite a bit smaller since continuation entries
|
| 559 |
|
|
* do not show up there:
|
| 560 |
|
|
*/
|
| 561 |
|
|
#define RES_QUEUE_LEN ((QLOGICISP_REQ_QUEUE_LEN + 1) / 8 - 1)
|
| 562 |
|
|
#define QUEUE_ENTRY_LEN 64
|
| 563 |
|
|
#define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
|
| 564 |
|
|
|
| 565 |
|
|
struct isp_queue_entry {
|
| 566 |
|
|
char __opaque[QUEUE_ENTRY_LEN];
|
| 567 |
|
|
};
|
| 568 |
|
|
|
| 569 |
|
|
struct isp1020_hostdata {
|
| 570 |
|
|
u_long memaddr;
|
| 571 |
|
|
u_char revision;
|
| 572 |
|
|
struct host_param host_param;
|
| 573 |
|
|
struct dev_param dev_param[MAX_TARGETS];
|
| 574 |
|
|
struct pci_dev *pci_dev;
|
| 575 |
|
|
|
| 576 |
|
|
struct isp_queue_entry *res_cpu; /* CPU-side address of response queue. */
|
| 577 |
|
|
struct isp_queue_entry *req_cpu; /* CPU-size address of request queue. */
|
| 578 |
|
|
|
| 579 |
|
|
/* result and request queues (shared with isp1020): */
|
| 580 |
|
|
u_int req_in_ptr; /* index of next request slot */
|
| 581 |
|
|
u_int res_out_ptr; /* index of next result slot */
|
| 582 |
|
|
|
| 583 |
|
|
/* this is here so the queues are nicely aligned */
|
| 584 |
|
|
long send_marker; /* do we need to send a marker? */
|
| 585 |
|
|
|
| 586 |
|
|
/* The cmd->handle has a fixed size, and is only 32-bits. We
|
| 587 |
|
|
* need to take care to handle 64-bit systems correctly thus what
|
| 588 |
|
|
* we actually place in cmd->handle is an index to the following
|
| 589 |
|
|
* table. Kudos to Matt Jacob for the technique. -DaveM
|
| 590 |
|
|
*/
|
| 591 |
|
|
Scsi_Cmnd *cmd_slots[QLOGICISP_REQ_QUEUE_LEN + 1];
|
| 592 |
|
|
|
| 593 |
|
|
dma_addr_t res_dma; /* PCI side view of response queue */
|
| 594 |
|
|
dma_addr_t req_dma; /* PCI side view of request queue */
|
| 595 |
|
|
};
|
| 596 |
|
|
|
| 597 |
|
|
/* queue length's _must_ be power of two: */
|
| 598 |
|
|
#define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
|
| 599 |
|
|
#define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
|
| 600 |
|
|
QLOGICISP_REQ_QUEUE_LEN)
|
| 601 |
|
|
#define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
|
| 602 |
|
|
|
| 603 |
|
|
static void isp1020_enable_irqs(struct Scsi_Host *);
|
| 604 |
|
|
static void isp1020_disable_irqs(struct Scsi_Host *);
|
| 605 |
|
|
static int isp1020_init(struct Scsi_Host *);
|
| 606 |
|
|
static int isp1020_reset_hardware(struct Scsi_Host *);
|
| 607 |
|
|
static int isp1020_set_defaults(struct Scsi_Host *);
|
| 608 |
|
|
static int isp1020_load_parameters(struct Scsi_Host *);
|
| 609 |
|
|
static int isp1020_mbox_command(struct Scsi_Host *, u_short []);
|
| 610 |
|
|
static int isp1020_return_status(struct Status_Entry *);
|
| 611 |
|
|
static void isp1020_intr_handler(int, void *, struct pt_regs *);
|
| 612 |
|
|
static void do_isp1020_intr_handler(int, void *, struct pt_regs *);
|
| 613 |
|
|
|
| 614 |
|
|
#if USE_NVRAM_DEFAULTS
|
| 615 |
|
|
static int isp1020_get_defaults(struct Scsi_Host *);
|
| 616 |
|
|
static int isp1020_verify_nvram(struct Scsi_Host *);
|
| 617 |
|
|
static u_short isp1020_read_nvram_word(struct Scsi_Host *, u_short);
|
| 618 |
|
|
#endif
|
| 619 |
|
|
|
| 620 |
|
|
#if DEBUG_ISP1020
|
| 621 |
|
|
static void isp1020_print_scsi_cmd(Scsi_Cmnd *);
|
| 622 |
|
|
#endif
|
| 623 |
|
|
#if DEBUG_ISP1020_INTR
|
| 624 |
|
|
static void isp1020_print_status_entry(struct Status_Entry *);
|
| 625 |
|
|
#endif
|
| 626 |
|
|
|
| 627 |
|
|
/* memaddr should be used to determine if memmapped port i/o is being used
|
| 628 |
|
|
* non-null memaddr == mmap'd
|
| 629 |
|
|
* JV 7-Jan-2000
|
| 630 |
|
|
*/
|
| 631 |
|
|
static inline u_short isp_inw(struct Scsi_Host *host, long offset)
|
| 632 |
|
|
{
|
| 633 |
|
|
struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
|
| 634 |
|
|
if (h->memaddr)
|
| 635 |
|
|
return readw(h->memaddr + offset);
|
| 636 |
|
|
else
|
| 637 |
|
|
return inw(host->io_port + offset);
|
| 638 |
|
|
}
|
| 639 |
|
|
|
| 640 |
|
|
static inline void isp_outw(u_short val, struct Scsi_Host *host, long offset)
|
| 641 |
|
|
{
|
| 642 |
|
|
struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
|
| 643 |
|
|
if (h->memaddr)
|
| 644 |
|
|
writew(val, h->memaddr + offset);
|
| 645 |
|
|
else
|
| 646 |
|
|
outw(val, host->io_port + offset);
|
| 647 |
|
|
}
|
| 648 |
|
|
|
| 649 |
|
|
static inline void isp1020_enable_irqs(struct Scsi_Host *host)
|
| 650 |
|
|
{
|
| 651 |
|
|
isp_outw(ISP_EN_INT|ISP_EN_RISC, host, PCI_INTF_CTL);
|
| 652 |
|
|
}
|
| 653 |
|
|
|
| 654 |
|
|
|
| 655 |
|
|
static inline void isp1020_disable_irqs(struct Scsi_Host *host)
|
| 656 |
|
|
{
|
| 657 |
|
|
isp_outw(0x0, host, PCI_INTF_CTL);
|
| 658 |
|
|
}
|
| 659 |
|
|
|
| 660 |
|
|
|
| 661 |
|
|
int isp1020_detect(Scsi_Host_Template *tmpt)
|
| 662 |
|
|
{
|
| 663 |
|
|
int hosts = 0;
|
| 664 |
|
|
struct Scsi_Host *host;
|
| 665 |
|
|
struct isp1020_hostdata *hostdata;
|
| 666 |
|
|
struct pci_dev *pdev = NULL;
|
| 667 |
|
|
|
| 668 |
|
|
ENTER("isp1020_detect");
|
| 669 |
|
|
|
| 670 |
|
|
tmpt->proc_name = "isp1020";
|
| 671 |
|
|
|
| 672 |
|
|
if (pci_present() == 0) {
|
| 673 |
|
|
printk("qlogicisp : PCI not present\n");
|
| 674 |
|
|
return 0;
|
| 675 |
|
|
}
|
| 676 |
|
|
|
| 677 |
|
|
while ((pdev = pci_find_device(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, pdev)))
|
| 678 |
|
|
{
|
| 679 |
|
|
if (pci_enable_device(pdev))
|
| 680 |
|
|
continue;
|
| 681 |
|
|
|
| 682 |
|
|
host = scsi_register(tmpt, sizeof(struct isp1020_hostdata));
|
| 683 |
|
|
if (!host)
|
| 684 |
|
|
continue;
|
| 685 |
|
|
|
| 686 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 687 |
|
|
|
| 688 |
|
|
memset(hostdata, 0, sizeof(struct isp1020_hostdata));
|
| 689 |
|
|
|
| 690 |
|
|
hostdata->pci_dev = pdev;
|
| 691 |
|
|
scsi_set_pci_device(host, pdev);
|
| 692 |
|
|
|
| 693 |
|
|
if (isp1020_init(host))
|
| 694 |
|
|
goto fail_and_unregister;
|
| 695 |
|
|
|
| 696 |
|
|
if (isp1020_reset_hardware(host)
|
| 697 |
|
|
#if USE_NVRAM_DEFAULTS
|
| 698 |
|
|
|| isp1020_get_defaults(host)
|
| 699 |
|
|
#else
|
| 700 |
|
|
|| isp1020_set_defaults(host)
|
| 701 |
|
|
#endif /* USE_NVRAM_DEFAULTS */
|
| 702 |
|
|
|| isp1020_load_parameters(host)) {
|
| 703 |
|
|
goto fail_uninit;
|
| 704 |
|
|
}
|
| 705 |
|
|
|
| 706 |
|
|
host->this_id = hostdata->host_param.initiator_scsi_id;
|
| 707 |
|
|
host->max_sectors = 64;
|
| 708 |
|
|
|
| 709 |
|
|
if (request_irq(host->irq, do_isp1020_intr_handler, SA_INTERRUPT | SA_SHIRQ,
|
| 710 |
|
|
"qlogicisp", host))
|
| 711 |
|
|
{
|
| 712 |
|
|
printk("qlogicisp : interrupt %d already in use\n",
|
| 713 |
|
|
host->irq);
|
| 714 |
|
|
goto fail_uninit;
|
| 715 |
|
|
}
|
| 716 |
|
|
|
| 717 |
|
|
isp_outw(0x0, host, PCI_SEMAPHORE);
|
| 718 |
|
|
isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
|
| 719 |
|
|
isp1020_enable_irqs(host);
|
| 720 |
|
|
|
| 721 |
|
|
hosts++;
|
| 722 |
|
|
continue;
|
| 723 |
|
|
|
| 724 |
|
|
fail_uninit:
|
| 725 |
|
|
if (hostdata->memaddr) iounmap((void *)hostdata->memaddr);
|
| 726 |
|
|
if (host->io_port) release_region(host->io_port, 0xff);
|
| 727 |
|
|
fail_and_unregister:
|
| 728 |
|
|
if (hostdata->res_cpu)
|
| 729 |
|
|
pci_free_consistent(hostdata->pci_dev,
|
| 730 |
|
|
QSIZE(RES_QUEUE_LEN),
|
| 731 |
|
|
hostdata->res_cpu,
|
| 732 |
|
|
hostdata->res_dma);
|
| 733 |
|
|
if (hostdata->req_cpu)
|
| 734 |
|
|
pci_free_consistent(hostdata->pci_dev,
|
| 735 |
|
|
QSIZE(QLOGICISP_REQ_QUEUE_LEN),
|
| 736 |
|
|
hostdata->req_cpu,
|
| 737 |
|
|
hostdata->req_dma);
|
| 738 |
|
|
scsi_unregister(host);
|
| 739 |
|
|
}
|
| 740 |
|
|
|
| 741 |
|
|
LEAVE("isp1020_detect");
|
| 742 |
|
|
|
| 743 |
|
|
return hosts;
|
| 744 |
|
|
}
|
| 745 |
|
|
|
| 746 |
|
|
|
| 747 |
|
|
int isp1020_release(struct Scsi_Host *host)
|
| 748 |
|
|
{
|
| 749 |
|
|
struct isp1020_hostdata *hostdata;
|
| 750 |
|
|
|
| 751 |
|
|
ENTER("isp1020_release");
|
| 752 |
|
|
|
| 753 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 754 |
|
|
|
| 755 |
|
|
isp_outw(0x0, host, PCI_INTF_CTL);
|
| 756 |
|
|
free_irq(host->irq, host);
|
| 757 |
|
|
|
| 758 |
|
|
if (hostdata->memaddr) iounmap((void *)hostdata->memaddr);
|
| 759 |
|
|
|
| 760 |
|
|
if (host->io_port) release_region(host->io_port, 0xff);
|
| 761 |
|
|
|
| 762 |
|
|
LEAVE("isp1020_release");
|
| 763 |
|
|
|
| 764 |
|
|
return 0;
|
| 765 |
|
|
}
|
| 766 |
|
|
|
| 767 |
|
|
|
| 768 |
|
|
const char *isp1020_info(struct Scsi_Host *host)
|
| 769 |
|
|
{
|
| 770 |
|
|
static char buf[80];
|
| 771 |
|
|
struct isp1020_hostdata *hostdata;
|
| 772 |
|
|
|
| 773 |
|
|
ENTER("isp1020_info");
|
| 774 |
|
|
|
| 775 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 776 |
|
|
sprintf(buf,
|
| 777 |
|
|
"QLogic ISP1020 SCSI on PCI bus %02x device %02x irq %d %s base 0x%lx",
|
| 778 |
|
|
hostdata->pci_dev->bus->number, hostdata->pci_dev->devfn, host->irq,
|
| 779 |
|
|
(hostdata->memaddr ? "MEM" : "I/O"),
|
| 780 |
|
|
(hostdata->memaddr ? hostdata->memaddr : host->io_port));
|
| 781 |
|
|
|
| 782 |
|
|
LEAVE("isp1020_info");
|
| 783 |
|
|
|
| 784 |
|
|
return buf;
|
| 785 |
|
|
}
|
| 786 |
|
|
|
| 787 |
|
|
|
| 788 |
|
|
/*
|
| 789 |
|
|
* The middle SCSI layer ensures that queuecommand never gets invoked
|
| 790 |
|
|
* concurrently with itself or the interrupt handler (though the
|
| 791 |
|
|
* interrupt handler may call this routine as part of
|
| 792 |
|
|
* request-completion handling).
|
| 793 |
|
|
*/
|
| 794 |
|
|
int isp1020_queuecommand(Scsi_Cmnd *Cmnd, void (*done)(Scsi_Cmnd *))
|
| 795 |
|
|
{
|
| 796 |
|
|
int i, n, num_free;
|
| 797 |
|
|
u_int in_ptr, out_ptr;
|
| 798 |
|
|
struct dataseg * ds;
|
| 799 |
|
|
struct scatterlist *sg;
|
| 800 |
|
|
struct Command_Entry *cmd;
|
| 801 |
|
|
struct Continuation_Entry *cont;
|
| 802 |
|
|
struct Scsi_Host *host;
|
| 803 |
|
|
struct isp1020_hostdata *hostdata;
|
| 804 |
|
|
dma_addr_t dma_addr;
|
| 805 |
|
|
|
| 806 |
|
|
ENTER("isp1020_queuecommand");
|
| 807 |
|
|
|
| 808 |
|
|
host = Cmnd->host;
|
| 809 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 810 |
|
|
Cmnd->scsi_done = done;
|
| 811 |
|
|
|
| 812 |
|
|
DEBUG(isp1020_print_scsi_cmd(Cmnd));
|
| 813 |
|
|
|
| 814 |
|
|
out_ptr = isp_inw(host, + MBOX4);
|
| 815 |
|
|
in_ptr = hostdata->req_in_ptr;
|
| 816 |
|
|
|
| 817 |
|
|
DEBUG(printk("qlogicisp : request queue depth %d\n",
|
| 818 |
|
|
REQ_QUEUE_DEPTH(in_ptr, out_ptr)));
|
| 819 |
|
|
|
| 820 |
|
|
cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
|
| 821 |
|
|
in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
|
| 822 |
|
|
if (in_ptr == out_ptr) {
|
| 823 |
|
|
printk("qlogicisp : request queue overflow\n");
|
| 824 |
|
|
return 1;
|
| 825 |
|
|
}
|
| 826 |
|
|
|
| 827 |
|
|
if (hostdata->send_marker) {
|
| 828 |
|
|
struct Marker_Entry *marker;
|
| 829 |
|
|
|
| 830 |
|
|
TRACE("queue marker", in_ptr, 0);
|
| 831 |
|
|
|
| 832 |
|
|
DEBUG(printk("qlogicisp : adding marker entry\n"));
|
| 833 |
|
|
marker = (struct Marker_Entry *) cmd;
|
| 834 |
|
|
memset(marker, 0, sizeof(struct Marker_Entry));
|
| 835 |
|
|
|
| 836 |
|
|
marker->hdr.entry_type = ENTRY_MARKER;
|
| 837 |
|
|
marker->hdr.entry_cnt = 1;
|
| 838 |
|
|
marker->modifier = SYNC_ALL;
|
| 839 |
|
|
|
| 840 |
|
|
hostdata->send_marker = 0;
|
| 841 |
|
|
|
| 842 |
|
|
if (((in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN) == out_ptr) {
|
| 843 |
|
|
isp_outw(in_ptr, host, MBOX4);
|
| 844 |
|
|
hostdata->req_in_ptr = in_ptr;
|
| 845 |
|
|
printk("qlogicisp : request queue overflow\n");
|
| 846 |
|
|
return 1;
|
| 847 |
|
|
}
|
| 848 |
|
|
cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
|
| 849 |
|
|
in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
|
| 850 |
|
|
}
|
| 851 |
|
|
|
| 852 |
|
|
TRACE("queue command", in_ptr, Cmnd);
|
| 853 |
|
|
|
| 854 |
|
|
memset(cmd, 0, sizeof(struct Command_Entry));
|
| 855 |
|
|
|
| 856 |
|
|
cmd->hdr.entry_type = ENTRY_COMMAND;
|
| 857 |
|
|
cmd->hdr.entry_cnt = 1;
|
| 858 |
|
|
|
| 859 |
|
|
cmd->target_lun = Cmnd->lun;
|
| 860 |
|
|
cmd->target_id = Cmnd->target;
|
| 861 |
|
|
cmd->cdb_length = cpu_to_le16(Cmnd->cmd_len);
|
| 862 |
|
|
cmd->control_flags = cpu_to_le16(CFLAG_READ | CFLAG_WRITE);
|
| 863 |
|
|
cmd->time_out = cpu_to_le16(30);
|
| 864 |
|
|
|
| 865 |
|
|
memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
|
| 866 |
|
|
|
| 867 |
|
|
if (Cmnd->use_sg) {
|
| 868 |
|
|
int sg_count;
|
| 869 |
|
|
|
| 870 |
|
|
sg = (struct scatterlist *) Cmnd->request_buffer;
|
| 871 |
|
|
ds = cmd->dataseg;
|
| 872 |
|
|
|
| 873 |
|
|
sg_count = pci_map_sg(hostdata->pci_dev, sg, Cmnd->use_sg,
|
| 874 |
|
|
scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
|
| 875 |
|
|
|
| 876 |
|
|
cmd->segment_cnt = cpu_to_le16(sg_count);
|
| 877 |
|
|
|
| 878 |
|
|
/* fill in first four sg entries: */
|
| 879 |
|
|
n = sg_count;
|
| 880 |
|
|
if (n > IOCB_SEGS)
|
| 881 |
|
|
n = IOCB_SEGS;
|
| 882 |
|
|
for (i = 0; i < n; i++) {
|
| 883 |
|
|
dma_addr = sg_dma_address(sg);
|
| 884 |
|
|
ds[i].d_base = cpu_to_le32((u32) dma_addr);
|
| 885 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 886 |
|
|
ds[i].d_base_hi = cpu_to_le32((u32) (dma_addr>>32));
|
| 887 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 888 |
|
|
ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
|
| 889 |
|
|
++sg;
|
| 890 |
|
|
}
|
| 891 |
|
|
sg_count -= IOCB_SEGS;
|
| 892 |
|
|
|
| 893 |
|
|
while (sg_count > 0) {
|
| 894 |
|
|
++cmd->hdr.entry_cnt;
|
| 895 |
|
|
cont = (struct Continuation_Entry *)
|
| 896 |
|
|
&hostdata->req_cpu[in_ptr];
|
| 897 |
|
|
in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
|
| 898 |
|
|
if (in_ptr == out_ptr) {
|
| 899 |
|
|
printk("isp1020: unexpected request queue "
|
| 900 |
|
|
"overflow\n");
|
| 901 |
|
|
return 1;
|
| 902 |
|
|
}
|
| 903 |
|
|
TRACE("queue continuation", in_ptr, 0);
|
| 904 |
|
|
cont->hdr.entry_type = ENTRY_CONTINUATION;
|
| 905 |
|
|
cont->hdr.entry_cnt = 0;
|
| 906 |
|
|
cont->hdr.sys_def_1 = 0;
|
| 907 |
|
|
cont->hdr.flags = 0;
|
| 908 |
|
|
#ifndef CONFIG_QL_ISP_A64
|
| 909 |
|
|
cont->reserved = 0;
|
| 910 |
|
|
#endif
|
| 911 |
|
|
ds = cont->dataseg;
|
| 912 |
|
|
n = sg_count;
|
| 913 |
|
|
if (n > CONTINUATION_SEGS)
|
| 914 |
|
|
n = CONTINUATION_SEGS;
|
| 915 |
|
|
for (i = 0; i < n; ++i) {
|
| 916 |
|
|
dma_addr = sg_dma_address(sg);
|
| 917 |
|
|
ds[i].d_base = cpu_to_le32((u32) dma_addr);
|
| 918 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 919 |
|
|
ds[i].d_base_hi = cpu_to_le32((u32)(dma_addr>>32));
|
| 920 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 921 |
|
|
ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
|
| 922 |
|
|
++sg;
|
| 923 |
|
|
}
|
| 924 |
|
|
sg_count -= n;
|
| 925 |
|
|
}
|
| 926 |
|
|
} else if (Cmnd->request_bufflen) {
|
| 927 |
|
|
/*Cmnd->SCp.ptr = (char *)(unsigned long)*/
|
| 928 |
|
|
dma_addr = pci_map_single(hostdata->pci_dev,
|
| 929 |
|
|
Cmnd->request_buffer,
|
| 930 |
|
|
Cmnd->request_bufflen,
|
| 931 |
|
|
scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
|
| 932 |
|
|
Cmnd->SCp.ptr = (char *)(unsigned long) dma_addr;
|
| 933 |
|
|
|
| 934 |
|
|
cmd->dataseg[0].d_base =
|
| 935 |
|
|
cpu_to_le32((u32) dma_addr);
|
| 936 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 937 |
|
|
cmd->dataseg[0].d_base_hi =
|
| 938 |
|
|
cpu_to_le32((u32) (dma_addr>>32));
|
| 939 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 940 |
|
|
cmd->dataseg[0].d_count =
|
| 941 |
|
|
cpu_to_le32((u32)Cmnd->request_bufflen);
|
| 942 |
|
|
cmd->segment_cnt = cpu_to_le16(1);
|
| 943 |
|
|
} else {
|
| 944 |
|
|
cmd->dataseg[0].d_base = 0;
|
| 945 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 946 |
|
|
cmd->dataseg[0].d_base_hi = 0;
|
| 947 |
|
|
#endif /* CONFIG_QL_ISP_A64 */
|
| 948 |
|
|
cmd->dataseg[0].d_count = 0;
|
| 949 |
|
|
cmd->segment_cnt = cpu_to_le16(1); /* Shouldn't this be 0? */
|
| 950 |
|
|
}
|
| 951 |
|
|
|
| 952 |
|
|
/* Committed, record Scsi_Cmd so we can find it later. */
|
| 953 |
|
|
cmd->handle = in_ptr;
|
| 954 |
|
|
hostdata->cmd_slots[in_ptr] = Cmnd;
|
| 955 |
|
|
|
| 956 |
|
|
isp_outw(in_ptr, host, MBOX4);
|
| 957 |
|
|
hostdata->req_in_ptr = in_ptr;
|
| 958 |
|
|
|
| 959 |
|
|
num_free = QLOGICISP_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr);
|
| 960 |
|
|
host->can_queue = host->host_busy + num_free;
|
| 961 |
|
|
host->sg_tablesize = QLOGICISP_MAX_SG(num_free);
|
| 962 |
|
|
|
| 963 |
|
|
LEAVE("isp1020_queuecommand");
|
| 964 |
|
|
|
| 965 |
|
|
return 0;
|
| 966 |
|
|
}
|
| 967 |
|
|
|
| 968 |
|
|
|
| 969 |
|
|
#define ASYNC_EVENT_INTERRUPT 0x01
|
| 970 |
|
|
|
| 971 |
|
|
void do_isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
|
| 972 |
|
|
{
|
| 973 |
|
|
unsigned long flags;
|
| 974 |
|
|
|
| 975 |
|
|
spin_lock_irqsave(&io_request_lock, flags);
|
| 976 |
|
|
isp1020_intr_handler(irq, dev_id, regs);
|
| 977 |
|
|
spin_unlock_irqrestore(&io_request_lock, flags);
|
| 978 |
|
|
}
|
| 979 |
|
|
|
| 980 |
|
|
void isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
|
| 981 |
|
|
{
|
| 982 |
|
|
Scsi_Cmnd *Cmnd;
|
| 983 |
|
|
struct Status_Entry *sts;
|
| 984 |
|
|
struct Scsi_Host *host = dev_id;
|
| 985 |
|
|
struct isp1020_hostdata *hostdata;
|
| 986 |
|
|
u_int in_ptr, out_ptr;
|
| 987 |
|
|
u_short status;
|
| 988 |
|
|
|
| 989 |
|
|
ENTER_INTR("isp1020_intr_handler");
|
| 990 |
|
|
|
| 991 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 992 |
|
|
|
| 993 |
|
|
DEBUG_INTR(printk("qlogicisp : interrupt on line %d\n", irq));
|
| 994 |
|
|
|
| 995 |
|
|
if (!(isp_inw(host, PCI_INTF_STS) & 0x04)) {
|
| 996 |
|
|
/* spurious interrupts can happen legally */
|
| 997 |
|
|
DEBUG_INTR(printk("qlogicisp: got spurious interrupt\n"));
|
| 998 |
|
|
return;
|
| 999 |
|
|
}
|
| 1000 |
|
|
in_ptr = isp_inw(host, MBOX5);
|
| 1001 |
|
|
isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
|
| 1002 |
|
|
|
| 1003 |
|
|
if ((isp_inw(host, PCI_SEMAPHORE) & ASYNC_EVENT_INTERRUPT)) {
|
| 1004 |
|
|
status = isp_inw(host, MBOX0);
|
| 1005 |
|
|
|
| 1006 |
|
|
DEBUG_INTR(printk("qlogicisp : mbox completion status: %x\n",
|
| 1007 |
|
|
status));
|
| 1008 |
|
|
|
| 1009 |
|
|
switch (status) {
|
| 1010 |
|
|
case ASYNC_SCSI_BUS_RESET:
|
| 1011 |
|
|
case EXECUTION_TIMEOUT_RESET:
|
| 1012 |
|
|
hostdata->send_marker = 1;
|
| 1013 |
|
|
break;
|
| 1014 |
|
|
case INVALID_COMMAND:
|
| 1015 |
|
|
case HOST_INTERFACE_ERROR:
|
| 1016 |
|
|
case COMMAND_ERROR:
|
| 1017 |
|
|
case COMMAND_PARAM_ERROR:
|
| 1018 |
|
|
printk("qlogicisp : bad mailbox return status\n");
|
| 1019 |
|
|
break;
|
| 1020 |
|
|
}
|
| 1021 |
|
|
isp_outw(0x0, host, PCI_SEMAPHORE);
|
| 1022 |
|
|
}
|
| 1023 |
|
|
out_ptr = hostdata->res_out_ptr;
|
| 1024 |
|
|
|
| 1025 |
|
|
DEBUG_INTR(printk("qlogicisp : response queue update\n"));
|
| 1026 |
|
|
DEBUG_INTR(printk("qlogicisp : response queue depth %d\n",
|
| 1027 |
|
|
QUEUE_DEPTH(in_ptr, out_ptr, RES_QUEUE_LEN)));
|
| 1028 |
|
|
|
| 1029 |
|
|
while (out_ptr != in_ptr) {
|
| 1030 |
|
|
u_int cmd_slot;
|
| 1031 |
|
|
|
| 1032 |
|
|
sts = (struct Status_Entry *) &hostdata->res_cpu[out_ptr];
|
| 1033 |
|
|
out_ptr = (out_ptr + 1) & RES_QUEUE_LEN;
|
| 1034 |
|
|
|
| 1035 |
|
|
cmd_slot = sts->handle;
|
| 1036 |
|
|
Cmnd = hostdata->cmd_slots[cmd_slot];
|
| 1037 |
|
|
hostdata->cmd_slots[cmd_slot] = NULL;
|
| 1038 |
|
|
|
| 1039 |
|
|
TRACE("done", out_ptr, Cmnd);
|
| 1040 |
|
|
|
| 1041 |
|
|
if (le16_to_cpu(sts->completion_status) == CS_RESET_OCCURRED
|
| 1042 |
|
|
|| le16_to_cpu(sts->completion_status) == CS_ABORTED
|
| 1043 |
|
|
|| (le16_to_cpu(sts->status_flags) & STF_BUS_RESET))
|
| 1044 |
|
|
hostdata->send_marker = 1;
|
| 1045 |
|
|
|
| 1046 |
|
|
if (le16_to_cpu(sts->state_flags) & SF_GOT_SENSE)
|
| 1047 |
|
|
memcpy(Cmnd->sense_buffer, sts->req_sense_data,
|
| 1048 |
|
|
sizeof(Cmnd->sense_buffer));
|
| 1049 |
|
|
|
| 1050 |
|
|
DEBUG_INTR(isp1020_print_status_entry(sts));
|
| 1051 |
|
|
|
| 1052 |
|
|
if (sts->hdr.entry_type == ENTRY_STATUS)
|
| 1053 |
|
|
Cmnd->result = isp1020_return_status(sts);
|
| 1054 |
|
|
else
|
| 1055 |
|
|
Cmnd->result = DID_ERROR << 16;
|
| 1056 |
|
|
|
| 1057 |
|
|
if (Cmnd->use_sg)
|
| 1058 |
|
|
pci_unmap_sg(hostdata->pci_dev,
|
| 1059 |
|
|
(struct scatterlist *)Cmnd->buffer,
|
| 1060 |
|
|
Cmnd->use_sg,
|
| 1061 |
|
|
scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
|
| 1062 |
|
|
else if (Cmnd->request_bufflen)
|
| 1063 |
|
|
pci_unmap_single(hostdata->pci_dev,
|
| 1064 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1065 |
|
|
(dma_addr_t)((long)Cmnd->SCp.ptr),
|
| 1066 |
|
|
#else
|
| 1067 |
|
|
(u32)((long)Cmnd->SCp.ptr),
|
| 1068 |
|
|
#endif
|
| 1069 |
|
|
Cmnd->request_bufflen,
|
| 1070 |
|
|
scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
|
| 1071 |
|
|
|
| 1072 |
|
|
isp_outw(out_ptr, host, MBOX5);
|
| 1073 |
|
|
(*Cmnd->scsi_done)(Cmnd);
|
| 1074 |
|
|
}
|
| 1075 |
|
|
hostdata->res_out_ptr = out_ptr;
|
| 1076 |
|
|
|
| 1077 |
|
|
LEAVE_INTR("isp1020_intr_handler");
|
| 1078 |
|
|
}
|
| 1079 |
|
|
|
| 1080 |
|
|
|
| 1081 |
|
|
static int isp1020_return_status(struct Status_Entry *sts)
|
| 1082 |
|
|
{
|
| 1083 |
|
|
int host_status = DID_ERROR;
|
| 1084 |
|
|
#if DEBUG_ISP1020_INTR
|
| 1085 |
|
|
static char *reason[] = {
|
| 1086 |
|
|
"DID_OK",
|
| 1087 |
|
|
"DID_NO_CONNECT",
|
| 1088 |
|
|
"DID_BUS_BUSY",
|
| 1089 |
|
|
"DID_TIME_OUT",
|
| 1090 |
|
|
"DID_BAD_TARGET",
|
| 1091 |
|
|
"DID_ABORT",
|
| 1092 |
|
|
"DID_PARITY",
|
| 1093 |
|
|
"DID_ERROR",
|
| 1094 |
|
|
"DID_RESET",
|
| 1095 |
|
|
"DID_BAD_INTR"
|
| 1096 |
|
|
};
|
| 1097 |
|
|
#endif /* DEBUG_ISP1020_INTR */
|
| 1098 |
|
|
|
| 1099 |
|
|
ENTER("isp1020_return_status");
|
| 1100 |
|
|
|
| 1101 |
|
|
DEBUG(printk("qlogicisp : completion status = 0x%04x\n",
|
| 1102 |
|
|
le16_to_cpu(sts->completion_status)));
|
| 1103 |
|
|
|
| 1104 |
|
|
switch(le16_to_cpu(sts->completion_status)) {
|
| 1105 |
|
|
case CS_COMPLETE:
|
| 1106 |
|
|
host_status = DID_OK;
|
| 1107 |
|
|
break;
|
| 1108 |
|
|
case CS_INCOMPLETE:
|
| 1109 |
|
|
if (!(le16_to_cpu(sts->state_flags) & SF_GOT_BUS))
|
| 1110 |
|
|
host_status = DID_NO_CONNECT;
|
| 1111 |
|
|
else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_TARGET))
|
| 1112 |
|
|
host_status = DID_BAD_TARGET;
|
| 1113 |
|
|
else if (!(le16_to_cpu(sts->state_flags) & SF_SENT_CDB))
|
| 1114 |
|
|
host_status = DID_ERROR;
|
| 1115 |
|
|
else if (!(le16_to_cpu(sts->state_flags) & SF_TRANSFERRED_DATA))
|
| 1116 |
|
|
host_status = DID_ERROR;
|
| 1117 |
|
|
else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_STATUS))
|
| 1118 |
|
|
host_status = DID_ERROR;
|
| 1119 |
|
|
else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_SENSE))
|
| 1120 |
|
|
host_status = DID_ERROR;
|
| 1121 |
|
|
break;
|
| 1122 |
|
|
case CS_DMA_ERROR:
|
| 1123 |
|
|
case CS_TRANSPORT_ERROR:
|
| 1124 |
|
|
host_status = DID_ERROR;
|
| 1125 |
|
|
break;
|
| 1126 |
|
|
case CS_RESET_OCCURRED:
|
| 1127 |
|
|
host_status = DID_RESET;
|
| 1128 |
|
|
break;
|
| 1129 |
|
|
case CS_ABORTED:
|
| 1130 |
|
|
host_status = DID_ABORT;
|
| 1131 |
|
|
break;
|
| 1132 |
|
|
case CS_TIMEOUT:
|
| 1133 |
|
|
host_status = DID_TIME_OUT;
|
| 1134 |
|
|
break;
|
| 1135 |
|
|
case CS_DATA_OVERRUN:
|
| 1136 |
|
|
case CS_COMMAND_OVERRUN:
|
| 1137 |
|
|
case CS_STATUS_OVERRUN:
|
| 1138 |
|
|
case CS_BAD_MESSAGE:
|
| 1139 |
|
|
case CS_NO_MESSAGE_OUT:
|
| 1140 |
|
|
case CS_EXT_ID_FAILED:
|
| 1141 |
|
|
case CS_IDE_MSG_FAILED:
|
| 1142 |
|
|
case CS_ABORT_MSG_FAILED:
|
| 1143 |
|
|
case CS_NOP_MSG_FAILED:
|
| 1144 |
|
|
case CS_PARITY_ERROR_MSG_FAILED:
|
| 1145 |
|
|
case CS_DEVICE_RESET_MSG_FAILED:
|
| 1146 |
|
|
case CS_ID_MSG_FAILED:
|
| 1147 |
|
|
case CS_UNEXP_BUS_FREE:
|
| 1148 |
|
|
host_status = DID_ERROR;
|
| 1149 |
|
|
break;
|
| 1150 |
|
|
case CS_DATA_UNDERRUN:
|
| 1151 |
|
|
host_status = DID_OK;
|
| 1152 |
|
|
break;
|
| 1153 |
|
|
default:
|
| 1154 |
|
|
printk("qlogicisp : unknown completion status 0x%04x\n",
|
| 1155 |
|
|
le16_to_cpu(sts->completion_status));
|
| 1156 |
|
|
host_status = DID_ERROR;
|
| 1157 |
|
|
break;
|
| 1158 |
|
|
}
|
| 1159 |
|
|
|
| 1160 |
|
|
DEBUG_INTR(printk("qlogicisp : host status (%s) scsi status %x\n",
|
| 1161 |
|
|
reason[host_status], le16_to_cpu(sts->scsi_status)));
|
| 1162 |
|
|
|
| 1163 |
|
|
LEAVE("isp1020_return_status");
|
| 1164 |
|
|
|
| 1165 |
|
|
return (le16_to_cpu(sts->scsi_status) & STATUS_MASK) | (host_status << 16);
|
| 1166 |
|
|
}
|
| 1167 |
|
|
|
| 1168 |
|
|
|
| 1169 |
|
|
int isp1020_abort(Scsi_Cmnd *Cmnd)
|
| 1170 |
|
|
{
|
| 1171 |
|
|
u_short param[6];
|
| 1172 |
|
|
struct Scsi_Host *host;
|
| 1173 |
|
|
struct isp1020_hostdata *hostdata;
|
| 1174 |
|
|
int return_status = SCSI_ABORT_SUCCESS;
|
| 1175 |
|
|
u_int cmd_cookie;
|
| 1176 |
|
|
int i;
|
| 1177 |
|
|
|
| 1178 |
|
|
ENTER("isp1020_abort");
|
| 1179 |
|
|
|
| 1180 |
|
|
host = Cmnd->host;
|
| 1181 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 1182 |
|
|
|
| 1183 |
|
|
for (i = 0; i < QLOGICISP_REQ_QUEUE_LEN + 1; i++)
|
| 1184 |
|
|
if (hostdata->cmd_slots[i] == Cmnd)
|
| 1185 |
|
|
break;
|
| 1186 |
|
|
cmd_cookie = i;
|
| 1187 |
|
|
|
| 1188 |
|
|
isp1020_disable_irqs(host);
|
| 1189 |
|
|
|
| 1190 |
|
|
param[0] = MBOX_ABORT;
|
| 1191 |
|
|
param[1] = (((u_short) Cmnd->target) << 8) | Cmnd->lun;
|
| 1192 |
|
|
param[2] = cmd_cookie >> 16;
|
| 1193 |
|
|
param[3] = cmd_cookie & 0xffff;
|
| 1194 |
|
|
|
| 1195 |
|
|
isp1020_mbox_command(host, param);
|
| 1196 |
|
|
|
| 1197 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1198 |
|
|
printk("qlogicisp : scsi abort failure: %x\n", param[0]);
|
| 1199 |
|
|
return_status = SCSI_ABORT_ERROR;
|
| 1200 |
|
|
}
|
| 1201 |
|
|
|
| 1202 |
|
|
isp1020_enable_irqs(host);
|
| 1203 |
|
|
|
| 1204 |
|
|
LEAVE("isp1020_abort");
|
| 1205 |
|
|
|
| 1206 |
|
|
return return_status;
|
| 1207 |
|
|
}
|
| 1208 |
|
|
|
| 1209 |
|
|
|
| 1210 |
|
|
int isp1020_reset(Scsi_Cmnd *Cmnd, unsigned int reset_flags)
|
| 1211 |
|
|
{
|
| 1212 |
|
|
u_short param[6];
|
| 1213 |
|
|
struct Scsi_Host *host;
|
| 1214 |
|
|
struct isp1020_hostdata *hostdata;
|
| 1215 |
|
|
int return_status = SCSI_RESET_SUCCESS;
|
| 1216 |
|
|
|
| 1217 |
|
|
ENTER("isp1020_reset");
|
| 1218 |
|
|
|
| 1219 |
|
|
host = Cmnd->host;
|
| 1220 |
|
|
hostdata = (struct isp1020_hostdata *) host->hostdata;
|
| 1221 |
|
|
|
| 1222 |
|
|
param[0] = MBOX_BUS_RESET;
|
| 1223 |
|
|
param[1] = hostdata->host_param.bus_reset_delay;
|
| 1224 |
|
|
|
| 1225 |
|
|
isp1020_disable_irqs(host);
|
| 1226 |
|
|
|
| 1227 |
|
|
isp1020_mbox_command(host, param);
|
| 1228 |
|
|
|
| 1229 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1230 |
|
|
printk("qlogicisp : scsi bus reset failure: %x\n", param[0]);
|
| 1231 |
|
|
return_status = SCSI_RESET_ERROR;
|
| 1232 |
|
|
}
|
| 1233 |
|
|
|
| 1234 |
|
|
isp1020_enable_irqs(host);
|
| 1235 |
|
|
|
| 1236 |
|
|
LEAVE("isp1020_reset");
|
| 1237 |
|
|
|
| 1238 |
|
|
return return_status;;
|
| 1239 |
|
|
}
|
| 1240 |
|
|
|
| 1241 |
|
|
|
| 1242 |
|
|
int isp1020_biosparam(Disk *disk, kdev_t n, int ip[])
|
| 1243 |
|
|
{
|
| 1244 |
|
|
int size = disk->capacity;
|
| 1245 |
|
|
|
| 1246 |
|
|
ENTER("isp1020_biosparam");
|
| 1247 |
|
|
|
| 1248 |
|
|
ip[0] = 64;
|
| 1249 |
|
|
ip[1] = 32;
|
| 1250 |
|
|
ip[2] = size >> 11;
|
| 1251 |
|
|
if (ip[2] > 1024) {
|
| 1252 |
|
|
ip[0] = 255;
|
| 1253 |
|
|
ip[1] = 63;
|
| 1254 |
|
|
ip[2] = size / (ip[0] * ip[1]);
|
| 1255 |
|
|
#if 0
|
| 1256 |
|
|
if (ip[2] > 1023)
|
| 1257 |
|
|
ip[2] = 1023;
|
| 1258 |
|
|
#endif
|
| 1259 |
|
|
}
|
| 1260 |
|
|
|
| 1261 |
|
|
LEAVE("isp1020_biosparam");
|
| 1262 |
|
|
|
| 1263 |
|
|
return 0;
|
| 1264 |
|
|
}
|
| 1265 |
|
|
|
| 1266 |
|
|
|
| 1267 |
|
|
static int isp1020_reset_hardware(struct Scsi_Host *host)
|
| 1268 |
|
|
{
|
| 1269 |
|
|
u_short param[6];
|
| 1270 |
|
|
int loop_count;
|
| 1271 |
|
|
|
| 1272 |
|
|
ENTER("isp1020_reset_hardware");
|
| 1273 |
|
|
|
| 1274 |
|
|
isp_outw(ISP_RESET, host, PCI_INTF_CTL);
|
| 1275 |
|
|
udelay(100);
|
| 1276 |
|
|
isp_outw(HCCR_RESET, host, HOST_HCCR);
|
| 1277 |
|
|
udelay(100);
|
| 1278 |
|
|
isp_outw(HCCR_RELEASE, host, HOST_HCCR);
|
| 1279 |
|
|
isp_outw(HCCR_BIOS_DISABLE, host, HOST_HCCR);
|
| 1280 |
|
|
|
| 1281 |
|
|
loop_count = DEFAULT_LOOP_COUNT;
|
| 1282 |
|
|
while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY) {
|
| 1283 |
|
|
barrier();
|
| 1284 |
|
|
cpu_relax();
|
| 1285 |
|
|
}
|
| 1286 |
|
|
if (!loop_count)
|
| 1287 |
|
|
printk("qlogicisp: reset_hardware loop timeout\n");
|
| 1288 |
|
|
|
| 1289 |
|
|
isp_outw(0, host, ISP_CFG1);
|
| 1290 |
|
|
|
| 1291 |
|
|
#if DEBUG_ISP1020
|
| 1292 |
|
|
printk("qlogicisp : mbox 0 0x%04x \n", isp_inw(host, MBOX0));
|
| 1293 |
|
|
printk("qlogicisp : mbox 1 0x%04x \n", isp_inw(host, MBOX1));
|
| 1294 |
|
|
printk("qlogicisp : mbox 2 0x%04x \n", isp_inw(host, MBOX2));
|
| 1295 |
|
|
printk("qlogicisp : mbox 3 0x%04x \n", isp_inw(host, MBOX3));
|
| 1296 |
|
|
printk("qlogicisp : mbox 4 0x%04x \n", isp_inw(host, MBOX4));
|
| 1297 |
|
|
printk("qlogicisp : mbox 5 0x%04x \n", isp_inw(host, MBOX5));
|
| 1298 |
|
|
#endif /* DEBUG_ISP1020 */
|
| 1299 |
|
|
|
| 1300 |
|
|
param[0] = MBOX_NO_OP;
|
| 1301 |
|
|
isp1020_mbox_command(host, param);
|
| 1302 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1303 |
|
|
printk("qlogicisp : NOP test failed\n");
|
| 1304 |
|
|
return 1;
|
| 1305 |
|
|
}
|
| 1306 |
|
|
|
| 1307 |
|
|
DEBUG(printk("qlogicisp : loading risc ram\n"));
|
| 1308 |
|
|
|
| 1309 |
|
|
#if RELOAD_FIRMWARE
|
| 1310 |
|
|
for (loop_count = 0; loop_count < risc_code_length01; loop_count++) {
|
| 1311 |
|
|
param[0] = MBOX_WRITE_RAM_WORD;
|
| 1312 |
|
|
param[1] = risc_code_addr01 + loop_count;
|
| 1313 |
|
|
param[2] = risc_code01[loop_count];
|
| 1314 |
|
|
isp1020_mbox_command(host, param);
|
| 1315 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1316 |
|
|
printk("qlogicisp : firmware load failure at %d\n",
|
| 1317 |
|
|
loop_count);
|
| 1318 |
|
|
return 1;
|
| 1319 |
|
|
}
|
| 1320 |
|
|
}
|
| 1321 |
|
|
#endif /* RELOAD_FIRMWARE */
|
| 1322 |
|
|
|
| 1323 |
|
|
DEBUG(printk("qlogicisp : verifying checksum\n"));
|
| 1324 |
|
|
|
| 1325 |
|
|
param[0] = MBOX_VERIFY_CHECKSUM;
|
| 1326 |
|
|
param[1] = risc_code_addr01;
|
| 1327 |
|
|
|
| 1328 |
|
|
isp1020_mbox_command(host, param);
|
| 1329 |
|
|
|
| 1330 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1331 |
|
|
printk("qlogicisp : ram checksum failure\n");
|
| 1332 |
|
|
return 1;
|
| 1333 |
|
|
}
|
| 1334 |
|
|
|
| 1335 |
|
|
DEBUG(printk("qlogicisp : executing firmware\n"));
|
| 1336 |
|
|
|
| 1337 |
|
|
param[0] = MBOX_EXEC_FIRMWARE;
|
| 1338 |
|
|
param[1] = risc_code_addr01;
|
| 1339 |
|
|
|
| 1340 |
|
|
isp1020_mbox_command(host, param);
|
| 1341 |
|
|
|
| 1342 |
|
|
param[0] = MBOX_ABOUT_FIRMWARE;
|
| 1343 |
|
|
|
| 1344 |
|
|
isp1020_mbox_command(host, param);
|
| 1345 |
|
|
|
| 1346 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1347 |
|
|
printk("qlogicisp : about firmware failure\n");
|
| 1348 |
|
|
return 1;
|
| 1349 |
|
|
}
|
| 1350 |
|
|
|
| 1351 |
|
|
DEBUG(printk("qlogicisp : firmware major revision %d\n", param[1]));
|
| 1352 |
|
|
DEBUG(printk("qlogicisp : firmware minor revision %d\n", param[2]));
|
| 1353 |
|
|
|
| 1354 |
|
|
LEAVE("isp1020_reset_hardware");
|
| 1355 |
|
|
|
| 1356 |
|
|
return 0;
|
| 1357 |
|
|
}
|
| 1358 |
|
|
|
| 1359 |
|
|
|
| 1360 |
|
|
static int isp1020_init(struct Scsi_Host *sh)
|
| 1361 |
|
|
{
|
| 1362 |
|
|
u_long io_base, mem_base, io_flags, mem_flags;
|
| 1363 |
|
|
struct isp1020_hostdata *hostdata;
|
| 1364 |
|
|
u_char revision;
|
| 1365 |
|
|
u_int irq;
|
| 1366 |
|
|
u_short command;
|
| 1367 |
|
|
struct pci_dev *pdev;
|
| 1368 |
|
|
|
| 1369 |
|
|
ENTER("isp1020_init");
|
| 1370 |
|
|
|
| 1371 |
|
|
hostdata = (struct isp1020_hostdata *) sh->hostdata;
|
| 1372 |
|
|
pdev = hostdata->pci_dev;
|
| 1373 |
|
|
|
| 1374 |
|
|
if (pci_read_config_word(pdev, PCI_COMMAND, &command)
|
| 1375 |
|
|
|| pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision))
|
| 1376 |
|
|
{
|
| 1377 |
|
|
printk("qlogicisp : error reading PCI configuration\n");
|
| 1378 |
|
|
return 1;
|
| 1379 |
|
|
}
|
| 1380 |
|
|
|
| 1381 |
|
|
io_base = pci_resource_start(pdev, 0);
|
| 1382 |
|
|
mem_base = pci_resource_start(pdev, 1);
|
| 1383 |
|
|
io_flags = pci_resource_flags(pdev, 0);
|
| 1384 |
|
|
mem_flags = pci_resource_flags(pdev, 1);
|
| 1385 |
|
|
irq = pdev->irq;
|
| 1386 |
|
|
|
| 1387 |
|
|
if (pdev->vendor != PCI_VENDOR_ID_QLOGIC) {
|
| 1388 |
|
|
printk("qlogicisp : 0x%04x is not QLogic vendor ID\n",
|
| 1389 |
|
|
pdev->vendor);
|
| 1390 |
|
|
return 1;
|
| 1391 |
|
|
}
|
| 1392 |
|
|
|
| 1393 |
|
|
if (pdev->device != PCI_DEVICE_ID_QLOGIC_ISP1020) {
|
| 1394 |
|
|
printk("qlogicisp : 0x%04x does not match ISP1020 device id\n",
|
| 1395 |
|
|
pdev->device);
|
| 1396 |
|
|
return 1;
|
| 1397 |
|
|
}
|
| 1398 |
|
|
|
| 1399 |
|
|
if (!(command & PCI_COMMAND_MASTER)) {
|
| 1400 |
|
|
printk("qlogicisp : bus mastering is disabled\n");
|
| 1401 |
|
|
return 1;
|
| 1402 |
|
|
}
|
| 1403 |
|
|
|
| 1404 |
|
|
sh->io_port = io_base;
|
| 1405 |
|
|
|
| 1406 |
|
|
/*
|
| 1407 |
|
|
By default, we choose to use PCI memory-mapped registers,
|
| 1408 |
|
|
if configured/available.
|
| 1409 |
|
|
|
| 1410 |
|
|
NOTE: we only ioremap() if we are going to use PCI
|
| 1411 |
|
|
memory-mapped registers, or only request_region() if using
|
| 1412 |
|
|
PCI I/O registers; we never do both anymore.
|
| 1413 |
|
|
*/
|
| 1414 |
|
|
if ((command & PCI_COMMAND_MEMORY) &&
|
| 1415 |
|
|
((mem_flags & 1) == 0)) {
|
| 1416 |
|
|
mem_base = (u_long) ioremap(mem_base, PAGE_SIZE);
|
| 1417 |
|
|
if (!mem_base) {
|
| 1418 |
|
|
printk("qlogicisp : i/o remapping failed.\n");
|
| 1419 |
|
|
return 1;
|
| 1420 |
|
|
}
|
| 1421 |
|
|
hostdata->memaddr = mem_base;
|
| 1422 |
|
|
sh->io_port = io_base = 0;
|
| 1423 |
|
|
} else {
|
| 1424 |
|
|
if (command & PCI_COMMAND_IO && (io_flags & 3) != 1) {
|
| 1425 |
|
|
printk("qlogicisp : i/o mapping is disabled\n");
|
| 1426 |
|
|
return 1;
|
| 1427 |
|
|
}
|
| 1428 |
|
|
if (!request_region(sh->io_port, 0xff, "qlogicisp")) {
|
| 1429 |
|
|
printk("qlogicisp : i/o region 0x%lx-0x%lx already "
|
| 1430 |
|
|
"in use\n",
|
| 1431 |
|
|
sh->io_port, sh->io_port + 0xff);
|
| 1432 |
|
|
return 1;
|
| 1433 |
|
|
}
|
| 1434 |
|
|
hostdata->memaddr = 0; /* zero to signify no i/o mapping */
|
| 1435 |
|
|
mem_base = 0;
|
| 1436 |
|
|
}
|
| 1437 |
|
|
|
| 1438 |
|
|
if (revision != ISP1020_REV_ID)
|
| 1439 |
|
|
printk("qlogicisp : new isp1020 revision ID (%d)\n", revision);
|
| 1440 |
|
|
|
| 1441 |
|
|
if (isp_inw(sh, PCI_ID_LOW) != PCI_VENDOR_ID_QLOGIC
|
| 1442 |
|
|
|| isp_inw(sh, PCI_ID_HIGH) != PCI_DEVICE_ID_QLOGIC_ISP1020)
|
| 1443 |
|
|
{
|
| 1444 |
|
|
printk("qlogicisp : can't decode %s address space 0x%lx\n",
|
| 1445 |
|
|
(io_base ? "I/O" : "MEM"),
|
| 1446 |
|
|
(io_base ? io_base : mem_base));
|
| 1447 |
|
|
goto out_unmap;
|
| 1448 |
|
|
}
|
| 1449 |
|
|
|
| 1450 |
|
|
hostdata->revision = revision;
|
| 1451 |
|
|
|
| 1452 |
|
|
sh->irq = irq;
|
| 1453 |
|
|
sh->max_id = MAX_TARGETS;
|
| 1454 |
|
|
sh->max_lun = MAX_LUNS;
|
| 1455 |
|
|
|
| 1456 |
|
|
hostdata->res_cpu = pci_alloc_consistent(hostdata->pci_dev,
|
| 1457 |
|
|
QSIZE(RES_QUEUE_LEN),
|
| 1458 |
|
|
&hostdata->res_dma);
|
| 1459 |
|
|
if (hostdata->res_cpu == NULL) {
|
| 1460 |
|
|
printk("qlogicisp : can't allocate response queue\n");
|
| 1461 |
|
|
goto out_unmap;
|
| 1462 |
|
|
}
|
| 1463 |
|
|
|
| 1464 |
|
|
hostdata->req_cpu = pci_alloc_consistent(hostdata->pci_dev,
|
| 1465 |
|
|
QSIZE(QLOGICISP_REQ_QUEUE_LEN),
|
| 1466 |
|
|
&hostdata->req_dma);
|
| 1467 |
|
|
if (hostdata->req_cpu == NULL) {
|
| 1468 |
|
|
pci_free_consistent(hostdata->pci_dev,
|
| 1469 |
|
|
QSIZE(RES_QUEUE_LEN),
|
| 1470 |
|
|
hostdata->res_cpu,
|
| 1471 |
|
|
hostdata->res_dma);
|
| 1472 |
|
|
printk("qlogicisp : can't allocate request queue\n");
|
| 1473 |
|
|
goto out_unmap;
|
| 1474 |
|
|
}
|
| 1475 |
|
|
|
| 1476 |
|
|
LEAVE("isp1020_init");
|
| 1477 |
|
|
|
| 1478 |
|
|
return 0;
|
| 1479 |
|
|
|
| 1480 |
|
|
out_unmap:
|
| 1481 |
|
|
if (mem_base) iounmap((void *)hostdata->memaddr);
|
| 1482 |
|
|
if (io_base) release_region(sh->io_port, 0xff);
|
| 1483 |
|
|
return 1;
|
| 1484 |
|
|
}
|
| 1485 |
|
|
|
| 1486 |
|
|
|
| 1487 |
|
|
#if USE_NVRAM_DEFAULTS
|
| 1488 |
|
|
|
| 1489 |
|
|
static int isp1020_get_defaults(struct Scsi_Host *host)
|
| 1490 |
|
|
{
|
| 1491 |
|
|
int i;
|
| 1492 |
|
|
u_short value;
|
| 1493 |
|
|
struct isp1020_hostdata *hostdata =
|
| 1494 |
|
|
(struct isp1020_hostdata *) host->hostdata;
|
| 1495 |
|
|
|
| 1496 |
|
|
ENTER("isp1020_get_defaults");
|
| 1497 |
|
|
|
| 1498 |
|
|
if (!isp1020_verify_nvram(host)) {
|
| 1499 |
|
|
printk("qlogicisp : nvram checksum failure\n");
|
| 1500 |
|
|
printk("qlogicisp : attempting to use default parameters\n");
|
| 1501 |
|
|
return isp1020_set_defaults(host);
|
| 1502 |
|
|
}
|
| 1503 |
|
|
|
| 1504 |
|
|
value = isp1020_read_nvram_word(host, 2);
|
| 1505 |
|
|
hostdata->host_param.fifo_threshold = (value >> 8) & 0x03;
|
| 1506 |
|
|
hostdata->host_param.host_adapter_enable = (value >> 11) & 0x01;
|
| 1507 |
|
|
hostdata->host_param.initiator_scsi_id = (value >> 12) & 0x0f;
|
| 1508 |
|
|
|
| 1509 |
|
|
value = isp1020_read_nvram_word(host, 3);
|
| 1510 |
|
|
hostdata->host_param.bus_reset_delay = value & 0xff;
|
| 1511 |
|
|
hostdata->host_param.retry_count = value >> 8;
|
| 1512 |
|
|
|
| 1513 |
|
|
value = isp1020_read_nvram_word(host, 4);
|
| 1514 |
|
|
hostdata->host_param.retry_delay = value & 0xff;
|
| 1515 |
|
|
hostdata->host_param.async_data_setup_time = (value >> 8) & 0x0f;
|
| 1516 |
|
|
hostdata->host_param.req_ack_active_negation = (value >> 12) & 0x01;
|
| 1517 |
|
|
hostdata->host_param.data_line_active_negation = (value >> 13) & 0x01;
|
| 1518 |
|
|
hostdata->host_param.data_dma_burst_enable = (value >> 14) & 0x01;
|
| 1519 |
|
|
hostdata->host_param.command_dma_burst_enable = (value >> 15);
|
| 1520 |
|
|
|
| 1521 |
|
|
value = isp1020_read_nvram_word(host, 5);
|
| 1522 |
|
|
hostdata->host_param.tag_aging = value & 0xff;
|
| 1523 |
|
|
|
| 1524 |
|
|
value = isp1020_read_nvram_word(host, 6);
|
| 1525 |
|
|
hostdata->host_param.selection_timeout = value & 0xffff;
|
| 1526 |
|
|
|
| 1527 |
|
|
value = isp1020_read_nvram_word(host, 7);
|
| 1528 |
|
|
hostdata->host_param.max_queue_depth = value & 0xffff;
|
| 1529 |
|
|
|
| 1530 |
|
|
#if DEBUG_ISP1020_SETUP
|
| 1531 |
|
|
printk("qlogicisp : fifo threshold=%d\n",
|
| 1532 |
|
|
hostdata->host_param.fifo_threshold);
|
| 1533 |
|
|
printk("qlogicisp : initiator scsi id=%d\n",
|
| 1534 |
|
|
hostdata->host_param.initiator_scsi_id);
|
| 1535 |
|
|
printk("qlogicisp : bus reset delay=%d\n",
|
| 1536 |
|
|
hostdata->host_param.bus_reset_delay);
|
| 1537 |
|
|
printk("qlogicisp : retry count=%d\n",
|
| 1538 |
|
|
hostdata->host_param.retry_count);
|
| 1539 |
|
|
printk("qlogicisp : retry delay=%d\n",
|
| 1540 |
|
|
hostdata->host_param.retry_delay);
|
| 1541 |
|
|
printk("qlogicisp : async data setup time=%d\n",
|
| 1542 |
|
|
hostdata->host_param.async_data_setup_time);
|
| 1543 |
|
|
printk("qlogicisp : req/ack active negation=%d\n",
|
| 1544 |
|
|
hostdata->host_param.req_ack_active_negation);
|
| 1545 |
|
|
printk("qlogicisp : data line active negation=%d\n",
|
| 1546 |
|
|
hostdata->host_param.data_line_active_negation);
|
| 1547 |
|
|
printk("qlogicisp : data DMA burst enable=%d\n",
|
| 1548 |
|
|
hostdata->host_param.data_dma_burst_enable);
|
| 1549 |
|
|
printk("qlogicisp : command DMA burst enable=%d\n",
|
| 1550 |
|
|
hostdata->host_param.command_dma_burst_enable);
|
| 1551 |
|
|
printk("qlogicisp : tag age limit=%d\n",
|
| 1552 |
|
|
hostdata->host_param.tag_aging);
|
| 1553 |
|
|
printk("qlogicisp : selection timeout limit=%d\n",
|
| 1554 |
|
|
hostdata->host_param.selection_timeout);
|
| 1555 |
|
|
printk("qlogicisp : max queue depth=%d\n",
|
| 1556 |
|
|
hostdata->host_param.max_queue_depth);
|
| 1557 |
|
|
#endif /* DEBUG_ISP1020_SETUP */
|
| 1558 |
|
|
|
| 1559 |
|
|
for (i = 0; i < MAX_TARGETS; i++) {
|
| 1560 |
|
|
|
| 1561 |
|
|
value = isp1020_read_nvram_word(host, 14 + i * 3);
|
| 1562 |
|
|
hostdata->dev_param[i].device_flags = value & 0xff;
|
| 1563 |
|
|
hostdata->dev_param[i].execution_throttle = value >> 8;
|
| 1564 |
|
|
|
| 1565 |
|
|
value = isp1020_read_nvram_word(host, 15 + i * 3);
|
| 1566 |
|
|
hostdata->dev_param[i].synchronous_period = value & 0xff;
|
| 1567 |
|
|
hostdata->dev_param[i].synchronous_offset = (value >> 8) & 0x0f;
|
| 1568 |
|
|
hostdata->dev_param[i].device_enable = (value >> 12) & 0x01;
|
| 1569 |
|
|
|
| 1570 |
|
|
#if DEBUG_ISP1020_SETUP
|
| 1571 |
|
|
printk("qlogicisp : target 0x%02x\n", i);
|
| 1572 |
|
|
printk("qlogicisp : device flags=0x%02x\n",
|
| 1573 |
|
|
hostdata->dev_param[i].device_flags);
|
| 1574 |
|
|
printk("qlogicisp : execution throttle=%d\n",
|
| 1575 |
|
|
hostdata->dev_param[i].execution_throttle);
|
| 1576 |
|
|
printk("qlogicisp : synchronous period=%d\n",
|
| 1577 |
|
|
hostdata->dev_param[i].synchronous_period);
|
| 1578 |
|
|
printk("qlogicisp : synchronous offset=%d\n",
|
| 1579 |
|
|
hostdata->dev_param[i].synchronous_offset);
|
| 1580 |
|
|
printk("qlogicisp : device enable=%d\n",
|
| 1581 |
|
|
hostdata->dev_param[i].device_enable);
|
| 1582 |
|
|
#endif /* DEBUG_ISP1020_SETUP */
|
| 1583 |
|
|
}
|
| 1584 |
|
|
|
| 1585 |
|
|
LEAVE("isp1020_get_defaults");
|
| 1586 |
|
|
|
| 1587 |
|
|
return 0;
|
| 1588 |
|
|
}
|
| 1589 |
|
|
|
| 1590 |
|
|
|
| 1591 |
|
|
#define ISP1020_NVRAM_LEN 0x40
|
| 1592 |
|
|
#define ISP1020_NVRAM_SIG1 0x5349
|
| 1593 |
|
|
#define ISP1020_NVRAM_SIG2 0x2050
|
| 1594 |
|
|
|
| 1595 |
|
|
static int isp1020_verify_nvram(struct Scsi_Host *host)
|
| 1596 |
|
|
{
|
| 1597 |
|
|
int i;
|
| 1598 |
|
|
u_short value;
|
| 1599 |
|
|
u_char checksum = 0;
|
| 1600 |
|
|
|
| 1601 |
|
|
for (i = 0; i < ISP1020_NVRAM_LEN; i++) {
|
| 1602 |
|
|
value = isp1020_read_nvram_word(host, i);
|
| 1603 |
|
|
|
| 1604 |
|
|
switch (i) {
|
| 1605 |
|
|
case 0:
|
| 1606 |
|
|
if (value != ISP1020_NVRAM_SIG1) return 0;
|
| 1607 |
|
|
break;
|
| 1608 |
|
|
case 1:
|
| 1609 |
|
|
if (value != ISP1020_NVRAM_SIG2) return 0;
|
| 1610 |
|
|
break;
|
| 1611 |
|
|
case 2:
|
| 1612 |
|
|
if ((value & 0xff) != 0x02) return 0;
|
| 1613 |
|
|
break;
|
| 1614 |
|
|
}
|
| 1615 |
|
|
checksum += value & 0xff;
|
| 1616 |
|
|
checksum += value >> 8;
|
| 1617 |
|
|
}
|
| 1618 |
|
|
|
| 1619 |
|
|
return (checksum == 0);
|
| 1620 |
|
|
}
|
| 1621 |
|
|
|
| 1622 |
|
|
#define NVRAM_DELAY() udelay(2) /* 2 microsecond delay */
|
| 1623 |
|
|
|
| 1624 |
|
|
|
| 1625 |
|
|
u_short isp1020_read_nvram_word(struct Scsi_Host *host, u_short byte)
|
| 1626 |
|
|
{
|
| 1627 |
|
|
int i;
|
| 1628 |
|
|
u_short value, output, input;
|
| 1629 |
|
|
|
| 1630 |
|
|
byte &= 0x3f; byte |= 0x0180;
|
| 1631 |
|
|
|
| 1632 |
|
|
for (i = 8; i >= 0; i--) {
|
| 1633 |
|
|
output = ((byte >> i) & 0x1) ? 0x4 : 0x0;
|
| 1634 |
|
|
isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1635 |
|
|
isp_outw(output | 0x3, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1636 |
|
|
isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1637 |
|
|
}
|
| 1638 |
|
|
|
| 1639 |
|
|
for (i = 0xf, value = 0; i >= 0; i--) {
|
| 1640 |
|
|
value <<= 1;
|
| 1641 |
|
|
isp_outw(0x3, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1642 |
|
|
input = isp_inw(host, PCI_NVRAM); NVRAM_DELAY();
|
| 1643 |
|
|
isp_outw(0x2, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1644 |
|
|
if (input & 0x8) value |= 1;
|
| 1645 |
|
|
}
|
| 1646 |
|
|
|
| 1647 |
|
|
isp_outw(0x0, host, PCI_NVRAM); NVRAM_DELAY();
|
| 1648 |
|
|
|
| 1649 |
|
|
return value;
|
| 1650 |
|
|
}
|
| 1651 |
|
|
|
| 1652 |
|
|
#endif /* USE_NVRAM_DEFAULTS */
|
| 1653 |
|
|
|
| 1654 |
|
|
|
| 1655 |
|
|
static int isp1020_set_defaults(struct Scsi_Host *host)
|
| 1656 |
|
|
{
|
| 1657 |
|
|
struct isp1020_hostdata *hostdata =
|
| 1658 |
|
|
(struct isp1020_hostdata *) host->hostdata;
|
| 1659 |
|
|
int i;
|
| 1660 |
|
|
|
| 1661 |
|
|
ENTER("isp1020_set_defaults");
|
| 1662 |
|
|
|
| 1663 |
|
|
hostdata->host_param.fifo_threshold = 2;
|
| 1664 |
|
|
hostdata->host_param.host_adapter_enable = 1;
|
| 1665 |
|
|
hostdata->host_param.initiator_scsi_id = 7;
|
| 1666 |
|
|
hostdata->host_param.bus_reset_delay = 3;
|
| 1667 |
|
|
hostdata->host_param.retry_count = 0;
|
| 1668 |
|
|
hostdata->host_param.retry_delay = 1;
|
| 1669 |
|
|
hostdata->host_param.async_data_setup_time = 6;
|
| 1670 |
|
|
hostdata->host_param.req_ack_active_negation = 1;
|
| 1671 |
|
|
hostdata->host_param.data_line_active_negation = 1;
|
| 1672 |
|
|
hostdata->host_param.data_dma_burst_enable = 1;
|
| 1673 |
|
|
hostdata->host_param.command_dma_burst_enable = 1;
|
| 1674 |
|
|
hostdata->host_param.tag_aging = 8;
|
| 1675 |
|
|
hostdata->host_param.selection_timeout = 250;
|
| 1676 |
|
|
hostdata->host_param.max_queue_depth = 256;
|
| 1677 |
|
|
|
| 1678 |
|
|
for (i = 0; i < MAX_TARGETS; i++) {
|
| 1679 |
|
|
hostdata->dev_param[i].device_flags = 0xfd;
|
| 1680 |
|
|
hostdata->dev_param[i].execution_throttle = 16;
|
| 1681 |
|
|
hostdata->dev_param[i].synchronous_period = 25;
|
| 1682 |
|
|
hostdata->dev_param[i].synchronous_offset = 12;
|
| 1683 |
|
|
hostdata->dev_param[i].device_enable = 1;
|
| 1684 |
|
|
}
|
| 1685 |
|
|
|
| 1686 |
|
|
LEAVE("isp1020_set_defaults");
|
| 1687 |
|
|
|
| 1688 |
|
|
return 0;
|
| 1689 |
|
|
}
|
| 1690 |
|
|
|
| 1691 |
|
|
|
| 1692 |
|
|
static int isp1020_load_parameters(struct Scsi_Host *host)
|
| 1693 |
|
|
{
|
| 1694 |
|
|
int i, k;
|
| 1695 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1696 |
|
|
u_long queue_addr;
|
| 1697 |
|
|
u_short param[8];
|
| 1698 |
|
|
#else
|
| 1699 |
|
|
u_int queue_addr;
|
| 1700 |
|
|
u_short param[6];
|
| 1701 |
|
|
#endif
|
| 1702 |
|
|
u_short isp_cfg1, hwrev;
|
| 1703 |
|
|
unsigned long flags;
|
| 1704 |
|
|
struct isp1020_hostdata *hostdata =
|
| 1705 |
|
|
(struct isp1020_hostdata *) host->hostdata;
|
| 1706 |
|
|
|
| 1707 |
|
|
ENTER("isp1020_load_parameters");
|
| 1708 |
|
|
|
| 1709 |
|
|
save_flags(flags);
|
| 1710 |
|
|
cli();
|
| 1711 |
|
|
|
| 1712 |
|
|
hwrev = isp_inw(host, ISP_CFG0) & ISP_CFG0_HWMSK;
|
| 1713 |
|
|
isp_cfg1 = ISP_CFG1_F64 | ISP_CFG1_BENAB;
|
| 1714 |
|
|
if (hwrev == ISP_CFG0_1040A) {
|
| 1715 |
|
|
/* Busted fifo, says mjacob. */
|
| 1716 |
|
|
isp_cfg1 &= ISP_CFG1_BENAB;
|
| 1717 |
|
|
}
|
| 1718 |
|
|
|
| 1719 |
|
|
isp_outw(isp_inw(host, ISP_CFG1) | isp_cfg1, host, ISP_CFG1);
|
| 1720 |
|
|
isp_outw(isp_inw(host, CDMA_CONF) | DMA_CONF_BENAB, host, CDMA_CONF);
|
| 1721 |
|
|
isp_outw(isp_inw(host, DDMA_CONF) | DMA_CONF_BENAB, host, DDMA_CONF);
|
| 1722 |
|
|
|
| 1723 |
|
|
param[0] = MBOX_SET_INIT_SCSI_ID;
|
| 1724 |
|
|
param[1] = hostdata->host_param.initiator_scsi_id;
|
| 1725 |
|
|
|
| 1726 |
|
|
isp1020_mbox_command(host, param);
|
| 1727 |
|
|
|
| 1728 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1729 |
|
|
restore_flags(flags);
|
| 1730 |
|
|
printk("qlogicisp : set initiator id failure\n");
|
| 1731 |
|
|
return 1;
|
| 1732 |
|
|
}
|
| 1733 |
|
|
|
| 1734 |
|
|
param[0] = MBOX_SET_RETRY_COUNT;
|
| 1735 |
|
|
param[1] = hostdata->host_param.retry_count;
|
| 1736 |
|
|
param[2] = hostdata->host_param.retry_delay;
|
| 1737 |
|
|
|
| 1738 |
|
|
isp1020_mbox_command(host, param);
|
| 1739 |
|
|
|
| 1740 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1741 |
|
|
restore_flags(flags);
|
| 1742 |
|
|
printk("qlogicisp : set retry count failure\n");
|
| 1743 |
|
|
return 1;
|
| 1744 |
|
|
}
|
| 1745 |
|
|
|
| 1746 |
|
|
param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME;
|
| 1747 |
|
|
param[1] = hostdata->host_param.async_data_setup_time;
|
| 1748 |
|
|
|
| 1749 |
|
|
isp1020_mbox_command(host, param);
|
| 1750 |
|
|
|
| 1751 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1752 |
|
|
restore_flags(flags);
|
| 1753 |
|
|
printk("qlogicisp : async data setup time failure\n");
|
| 1754 |
|
|
return 1;
|
| 1755 |
|
|
}
|
| 1756 |
|
|
|
| 1757 |
|
|
param[0] = MBOX_SET_ACTIVE_NEG_STATE;
|
| 1758 |
|
|
param[1] = (hostdata->host_param.req_ack_active_negation << 4)
|
| 1759 |
|
|
| (hostdata->host_param.data_line_active_negation << 5);
|
| 1760 |
|
|
|
| 1761 |
|
|
isp1020_mbox_command(host, param);
|
| 1762 |
|
|
|
| 1763 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1764 |
|
|
restore_flags(flags);
|
| 1765 |
|
|
printk("qlogicisp : set active negation state failure\n");
|
| 1766 |
|
|
return 1;
|
| 1767 |
|
|
}
|
| 1768 |
|
|
|
| 1769 |
|
|
param[0] = MBOX_SET_PCI_CONTROL_PARAMS;
|
| 1770 |
|
|
param[1] = hostdata->host_param.data_dma_burst_enable << 1;
|
| 1771 |
|
|
param[2] = hostdata->host_param.command_dma_burst_enable << 1;
|
| 1772 |
|
|
|
| 1773 |
|
|
isp1020_mbox_command(host, param);
|
| 1774 |
|
|
|
| 1775 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1776 |
|
|
restore_flags(flags);
|
| 1777 |
|
|
printk("qlogicisp : set pci control parameter failure\n");
|
| 1778 |
|
|
return 1;
|
| 1779 |
|
|
}
|
| 1780 |
|
|
|
| 1781 |
|
|
param[0] = MBOX_SET_TAG_AGE_LIMIT;
|
| 1782 |
|
|
param[1] = hostdata->host_param.tag_aging;
|
| 1783 |
|
|
|
| 1784 |
|
|
isp1020_mbox_command(host, param);
|
| 1785 |
|
|
|
| 1786 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1787 |
|
|
restore_flags(flags);
|
| 1788 |
|
|
printk("qlogicisp : set tag age limit failure\n");
|
| 1789 |
|
|
return 1;
|
| 1790 |
|
|
}
|
| 1791 |
|
|
|
| 1792 |
|
|
param[0] = MBOX_SET_SELECT_TIMEOUT;
|
| 1793 |
|
|
param[1] = hostdata->host_param.selection_timeout;
|
| 1794 |
|
|
|
| 1795 |
|
|
isp1020_mbox_command(host, param);
|
| 1796 |
|
|
|
| 1797 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1798 |
|
|
restore_flags(flags);
|
| 1799 |
|
|
printk("qlogicisp : set selection timeout failure\n");
|
| 1800 |
|
|
return 1;
|
| 1801 |
|
|
}
|
| 1802 |
|
|
|
| 1803 |
|
|
for (i = 0; i < MAX_TARGETS; i++) {
|
| 1804 |
|
|
|
| 1805 |
|
|
if (!hostdata->dev_param[i].device_enable)
|
| 1806 |
|
|
continue;
|
| 1807 |
|
|
|
| 1808 |
|
|
param[0] = MBOX_SET_TARGET_PARAMS;
|
| 1809 |
|
|
param[1] = i << 8;
|
| 1810 |
|
|
param[2] = hostdata->dev_param[i].device_flags << 8;
|
| 1811 |
|
|
param[3] = (hostdata->dev_param[i].synchronous_offset << 8)
|
| 1812 |
|
|
| hostdata->dev_param[i].synchronous_period;
|
| 1813 |
|
|
|
| 1814 |
|
|
isp1020_mbox_command(host, param);
|
| 1815 |
|
|
|
| 1816 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1817 |
|
|
restore_flags(flags);
|
| 1818 |
|
|
printk("qlogicisp : set target parameter failure\n");
|
| 1819 |
|
|
return 1;
|
| 1820 |
|
|
}
|
| 1821 |
|
|
|
| 1822 |
|
|
for (k = 0; k < MAX_LUNS; k++) {
|
| 1823 |
|
|
|
| 1824 |
|
|
param[0] = MBOX_SET_DEV_QUEUE_PARAMS;
|
| 1825 |
|
|
param[1] = (i << 8) | k;
|
| 1826 |
|
|
param[2] = hostdata->host_param.max_queue_depth;
|
| 1827 |
|
|
param[3] = hostdata->dev_param[i].execution_throttle;
|
| 1828 |
|
|
|
| 1829 |
|
|
isp1020_mbox_command(host, param);
|
| 1830 |
|
|
|
| 1831 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1832 |
|
|
restore_flags(flags);
|
| 1833 |
|
|
printk("qlogicisp : set device queue "
|
| 1834 |
|
|
"parameter failure\n");
|
| 1835 |
|
|
return 1;
|
| 1836 |
|
|
}
|
| 1837 |
|
|
}
|
| 1838 |
|
|
}
|
| 1839 |
|
|
|
| 1840 |
|
|
queue_addr = hostdata->res_dma;
|
| 1841 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1842 |
|
|
param[0] = MBOX_CMD_INIT_RESPONSE_QUEUE_64;
|
| 1843 |
|
|
#else
|
| 1844 |
|
|
param[0] = MBOX_INIT_RES_QUEUE;
|
| 1845 |
|
|
#endif
|
| 1846 |
|
|
param[1] = RES_QUEUE_LEN + 1;
|
| 1847 |
|
|
param[2] = (u_short) (queue_addr >> 16);
|
| 1848 |
|
|
param[3] = (u_short) (queue_addr & 0xffff);
|
| 1849 |
|
|
param[4] = 0;
|
| 1850 |
|
|
param[5] = 0;
|
| 1851 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1852 |
|
|
param[6] = (u_short) (queue_addr >> 48);
|
| 1853 |
|
|
param[7] = (u_short) (queue_addr >> 32);
|
| 1854 |
|
|
#endif
|
| 1855 |
|
|
|
| 1856 |
|
|
isp1020_mbox_command(host, param);
|
| 1857 |
|
|
|
| 1858 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1859 |
|
|
restore_flags(flags);
|
| 1860 |
|
|
printk("qlogicisp : set response queue failure\n");
|
| 1861 |
|
|
return 1;
|
| 1862 |
|
|
}
|
| 1863 |
|
|
|
| 1864 |
|
|
queue_addr = hostdata->req_dma;
|
| 1865 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1866 |
|
|
param[0] = MBOX_CMD_INIT_REQUEST_QUEUE_64;
|
| 1867 |
|
|
#else
|
| 1868 |
|
|
param[0] = MBOX_INIT_REQ_QUEUE;
|
| 1869 |
|
|
#endif
|
| 1870 |
|
|
param[1] = QLOGICISP_REQ_QUEUE_LEN + 1;
|
| 1871 |
|
|
param[2] = (u_short) (queue_addr >> 16);
|
| 1872 |
|
|
param[3] = (u_short) (queue_addr & 0xffff);
|
| 1873 |
|
|
param[4] = 0;
|
| 1874 |
|
|
|
| 1875 |
|
|
#ifdef CONFIG_QL_ISP_A64
|
| 1876 |
|
|
param[5] = 0;
|
| 1877 |
|
|
param[6] = (u_short) (queue_addr >> 48);
|
| 1878 |
|
|
param[7] = (u_short) (queue_addr >> 32);
|
| 1879 |
|
|
#endif
|
| 1880 |
|
|
|
| 1881 |
|
|
isp1020_mbox_command(host, param);
|
| 1882 |
|
|
|
| 1883 |
|
|
if (param[0] != MBOX_COMMAND_COMPLETE) {
|
| 1884 |
|
|
restore_flags(flags);
|
| 1885 |
|
|
printk("qlogicisp : set request queue failure\n");
|
| 1886 |
|
|
return 1;
|
| 1887 |
|
|
}
|
| 1888 |
|
|
|
| 1889 |
|
|
restore_flags(flags);
|
| 1890 |
|
|
|
| 1891 |
|
|
LEAVE("isp1020_load_parameters");
|
| 1892 |
|
|
|
| 1893 |
|
|
return 0;
|
| 1894 |
|
|
}
|
| 1895 |
|
|
|
| 1896 |
|
|
|
| 1897 |
|
|
/*
|
| 1898 |
|
|
* currently, this is only called during initialization or abort/reset,
|
| 1899 |
|
|
* at which times interrupts are disabled, so polling is OK, I guess...
|
| 1900 |
|
|
*/
|
| 1901 |
|
|
static int isp1020_mbox_command(struct Scsi_Host *host, u_short param[])
|
| 1902 |
|
|
{
|
| 1903 |
|
|
int loop_count;
|
| 1904 |
|
|
|
| 1905 |
|
|
if (mbox_param[param[0]] == 0)
|
| 1906 |
|
|
return 1;
|
| 1907 |
|
|
|
| 1908 |
|
|
loop_count = DEFAULT_LOOP_COUNT;
|
| 1909 |
|
|
while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080) {
|
| 1910 |
|
|
barrier();
|
| 1911 |
|
|
cpu_relax();
|
| 1912 |
|
|
}
|
| 1913 |
|
|
if (!loop_count)
|
| 1914 |
|
|
printk("qlogicisp: mbox_command loop timeout #1\n");
|
| 1915 |
|
|
|
| 1916 |
|
|
switch(mbox_param[param[0]] >> 4) {
|
| 1917 |
|
|
case 8: isp_outw(param[7], host, MBOX7);
|
| 1918 |
|
|
case 7: isp_outw(param[6], host, MBOX6);
|
| 1919 |
|
|
case 6: isp_outw(param[5], host, MBOX5);
|
| 1920 |
|
|
case 5: isp_outw(param[4], host, MBOX4);
|
| 1921 |
|
|
case 4: isp_outw(param[3], host, MBOX3);
|
| 1922 |
|
|
case 3: isp_outw(param[2], host, MBOX2);
|
| 1923 |
|
|
case 2: isp_outw(param[1], host, MBOX1);
|
| 1924 |
|
|
case 1: isp_outw(param[0], host, MBOX0);
|
| 1925 |
|
|
}
|
| 1926 |
|
|
|
| 1927 |
|
|
isp_outw(0x0, host, PCI_SEMAPHORE);
|
| 1928 |
|
|
isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
|
| 1929 |
|
|
isp_outw(HCCR_SET_HOST_INTR, host, HOST_HCCR);
|
| 1930 |
|
|
|
| 1931 |
|
|
loop_count = DEFAULT_LOOP_COUNT;
|
| 1932 |
|
|
while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04)) {
|
| 1933 |
|
|
barrier();
|
| 1934 |
|
|
cpu_relax();
|
| 1935 |
|
|
}
|
| 1936 |
|
|
if (!loop_count)
|
| 1937 |
|
|
printk("qlogicisp: mbox_command loop timeout #2\n");
|
| 1938 |
|
|
|
| 1939 |
|
|
loop_count = DEFAULT_LOOP_COUNT;
|
| 1940 |
|
|
while (--loop_count && isp_inw(host, MBOX0) == 0x04) {
|
| 1941 |
|
|
barrier();
|
| 1942 |
|
|
cpu_relax();
|
| 1943 |
|
|
}
|
| 1944 |
|
|
if (!loop_count)
|
| 1945 |
|
|
printk("qlogicisp: mbox_command loop timeout #3\n");
|
| 1946 |
|
|
|
| 1947 |
|
|
switch(mbox_param[param[0]] & 0xf) {
|
| 1948 |
|
|
case 8: param[7] = isp_inw(host, MBOX7);
|
| 1949 |
|
|
case 7: param[6] = isp_inw(host, MBOX6);
|
| 1950 |
|
|
case 6: param[5] = isp_inw(host, MBOX5);
|
| 1951 |
|
|
case 5: param[4] = isp_inw(host, MBOX4);
|
| 1952 |
|
|
case 4: param[3] = isp_inw(host, MBOX3);
|
| 1953 |
|
|
case 3: param[2] = isp_inw(host, MBOX2);
|
| 1954 |
|
|
case 2: param[1] = isp_inw(host, MBOX1);
|
| 1955 |
|
|
case 1: param[0] = isp_inw(host, MBOX0);
|
| 1956 |
|
|
}
|
| 1957 |
|
|
|
| 1958 |
|
|
isp_outw(0x0, host, PCI_SEMAPHORE);
|
| 1959 |
|
|
isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
|
| 1960 |
|
|
|
| 1961 |
|
|
return 0;
|
| 1962 |
|
|
}
|
| 1963 |
|
|
|
| 1964 |
|
|
|
| 1965 |
|
|
#if DEBUG_ISP1020_INTR
|
| 1966 |
|
|
|
| 1967 |
|
|
void isp1020_print_status_entry(struct Status_Entry *status)
|
| 1968 |
|
|
{
|
| 1969 |
|
|
int i;
|
| 1970 |
|
|
|
| 1971 |
|
|
printk("qlogicisp : entry count = 0x%02x, type = 0x%02x, flags = 0x%02x\n",
|
| 1972 |
|
|
status->hdr.entry_cnt, status->hdr.entry_type, status->hdr.flags);
|
| 1973 |
|
|
printk("qlogicisp : scsi status = 0x%04x, completion status = 0x%04x\n",
|
| 1974 |
|
|
le16_to_cpu(status->scsi_status), le16_to_cpu(status->completion_status));
|
| 1975 |
|
|
printk("qlogicisp : state flags = 0x%04x, status flags = 0x%04x\n",
|
| 1976 |
|
|
le16_to_cpu(status->state_flags), le16_to_cpu(status->status_flags));
|
| 1977 |
|
|
printk("qlogicisp : time = 0x%04x, request sense length = 0x%04x\n",
|
| 1978 |
|
|
le16_to_cpu(status->time), le16_to_cpu(status->req_sense_len));
|
| 1979 |
|
|
printk("qlogicisp : residual transfer length = 0x%08x\n",
|
| 1980 |
|
|
le32_to_cpu(status->residual));
|
| 1981 |
|
|
|
| 1982 |
|
|
for (i = 0; i < le16_to_cpu(status->req_sense_len); i++)
|
| 1983 |
|
|
printk("qlogicisp : sense data = 0x%02x\n", status->req_sense_data[i]);
|
| 1984 |
|
|
}
|
| 1985 |
|
|
|
| 1986 |
|
|
#endif /* DEBUG_ISP1020_INTR */
|
| 1987 |
|
|
|
| 1988 |
|
|
|
| 1989 |
|
|
#if DEBUG_ISP1020
|
| 1990 |
|
|
|
| 1991 |
|
|
void isp1020_print_scsi_cmd(Scsi_Cmnd *cmd)
|
| 1992 |
|
|
{
|
| 1993 |
|
|
int i;
|
| 1994 |
|
|
|
| 1995 |
|
|
printk("qlogicisp : target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n",
|
| 1996 |
|
|
cmd->target, cmd->lun, cmd->cmd_len);
|
| 1997 |
|
|
printk("qlogicisp : command = ");
|
| 1998 |
|
|
for (i = 0; i < cmd->cmd_len; i++)
|
| 1999 |
|
|
printk("0x%02x ", cmd->cmnd[i]);
|
| 2000 |
|
|
printk("\n");
|
| 2001 |
|
|
}
|
| 2002 |
|
|
|
| 2003 |
|
|
#endif /* DEBUG_ISP1020 */
|
| 2004 |
|
|
|
| 2005 |
|
|
MODULE_LICENSE("GPL");
|
| 2006 |
|
|
|
| 2007 |
|
|
static Scsi_Host_Template driver_template = QLOGICISP;
|
| 2008 |
|
|
|
| 2009 |
|
|
#include "scsi_module.c"
|
