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1275 |
phoenix |
/******************************************************************************
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** High Performance device driver for the Symbios 53C896 controller.
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**
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** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
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**
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** This driver also supports all the Symbios 53C8XX controller family,
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** except 53C810 revisions < 16, 53C825 revisions < 16 and all
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** revisions of 53C815 controllers.
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**
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** This driver is based on the Linux port of the FreeBSD ncr driver.
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**
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** Copyright (C) 1994 Wolfgang Stanglmeier
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**
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**-----------------------------------------------------------------------------
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software
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** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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**
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**-----------------------------------------------------------------------------
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**
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** The Linux port of the FreeBSD ncr driver has been achieved in
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** november 1995 by:
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**
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** Gerard Roudier <groudier@free.fr>
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**
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** Being given that this driver originates from the FreeBSD version, and
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** in order to keep synergy on both, any suggested enhancements and corrections
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** received on Linux are automatically a potential candidate for the FreeBSD
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** version.
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**
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** The original driver has been written for 386bsd and FreeBSD by
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** Wolfgang Stanglmeier <wolf@cologne.de>
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** Stefan Esser <se@mi.Uni-Koeln.de>
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**
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**-----------------------------------------------------------------------------
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**
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** Major contributions:
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** --------------------
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**
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** NVRAM detection and reading.
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** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
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**
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** Added support for MIPS big endian systems.
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** Carsten Langgaard, carstenl@mips.com
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** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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**
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*******************************************************************************
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*/
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#ifndef SYM53C8XX_DEFS_H
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#define SYM53C8XX_DEFS_H
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/*
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** Check supported Linux versions
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*/
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#if !defined(LINUX_VERSION_CODE)
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#include <linux/version.h>
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#endif
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#include <linux/config.h>
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#define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
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/*
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* NCR PQS/PDS special device support.
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
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#define SCSI_NCR_PQS_PDS_SUPPORT
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#endif
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/*
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* No more an option, enabled by default.
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*/
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#ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
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#define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
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#endif
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/*
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** These options are not tunable from 'make config'
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*/
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#define SCSI_NCR_PROC_INFO_SUPPORT
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/*
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** If you want a driver as small as possible, donnot define the
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** following options.
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*/
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#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
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#define SCSI_NCR_DEBUG_INFO_SUPPORT
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#define SCSI_NCR_PCI_FIX_UP_SUPPORT
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#ifdef SCSI_NCR_PROC_INFO_SUPPORT
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# define SCSI_NCR_USER_COMMAND_SUPPORT
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# define SCSI_NCR_USER_INFO_SUPPORT
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#endif
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/*
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** To disable integrity checking, do not define the
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** following option.
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
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# define SCSI_NCR_ENABLE_INTEGRITY_CHECK
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#endif
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/*==========================================================
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**
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** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
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**
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**==========================================================
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
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#define SCSI_NCR_NVRAM_SUPPORT
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/* #define SCSI_NCR_DEBUG_NVRAM */
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#endif
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/* ---------------------------------------------------------------------
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** Take into account kernel configured parameters.
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** Most of these options can be overridden at startup by a command line.
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** ---------------------------------------------------------------------
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*/
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/*
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* For Ultra2 and Ultra3 SCSI support option, use special features.
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*
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* Value (default) means:
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* bit 0 : all features enabled, except:
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* bit 1 : PCI Write And Invalidate.
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* bit 2 : Data Phase Mismatch handling from SCRIPTS.
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*
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* Use boot options ncr53c8xx=specf:1 if you want all chip features to be
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* enabled by the driver.
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*/
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#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
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#define SCSI_NCR_MAX_SYNC (80)
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/*
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* Allow tags from 2 to 256, default 8
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
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#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
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#define SCSI_NCR_MAX_TAGS (2)
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#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
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#define SCSI_NCR_MAX_TAGS (256)
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#else
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#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
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#endif
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#else
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#define SCSI_NCR_MAX_TAGS (8)
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#endif
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/*
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* Allow tagged command queuing support if configured with default number
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* of tags set to max (see above).
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
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#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
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#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
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#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
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#else
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#define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
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#endif
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/*
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* Use normal IO if configured. Forced for alpha.
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*/
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#if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
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#define SCSI_NCR_IOMAPPED
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#elif defined(__alpha__)
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#define SCSI_NCR_IOMAPPED
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#elif defined(__powerpc__)
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#if LINUX_VERSION_CODE <= LinuxVersionCode(2,4,3)
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#define SCSI_NCR_IOMAPPED
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#define SCSI_NCR_PCI_MEM_NOT_SUPPORTED
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#endif
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#elif defined(__sparc__)
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#undef SCSI_NCR_IOMAPPED
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#endif
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/*
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* Immediate arbitration
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*/
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#if defined(CONFIG_SCSI_NCR53C8XX_IARB)
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#define SCSI_NCR_IARB_SUPPORT
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#endif
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/*
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* Sync transfer frequency at startup.
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* Allow from 5Mhz to 80Mhz default 20 Mhz.
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*/
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#ifndef CONFIG_SCSI_NCR53C8XX_SYNC
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#define CONFIG_SCSI_NCR53C8XX_SYNC (20)
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#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
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#undef CONFIG_SCSI_NCR53C8XX_SYNC
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#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
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#endif
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#if CONFIG_SCSI_NCR53C8XX_SYNC == 0
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
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#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
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#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
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#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
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#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
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#else
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#define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
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#endif
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/*
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* Disallow disconnections at boot-up
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
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#define SCSI_NCR_SETUP_DISCONNECTION (0)
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#else
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#define SCSI_NCR_SETUP_DISCONNECTION (1)
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#endif
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/*
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* Force synchronous negotiation for all targets
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
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#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
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#else
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#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
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#endif
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/*
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* Disable master parity checking (flawed hardwares need that)
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
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#define SCSI_NCR_SETUP_MASTER_PARITY (0)
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#else
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#define SCSI_NCR_SETUP_MASTER_PARITY (1)
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#endif
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/*
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* Disable scsi parity checking (flawed devices may need that)
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
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#define SCSI_NCR_SETUP_SCSI_PARITY (0)
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#else
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#define SCSI_NCR_SETUP_SCSI_PARITY (1)
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#endif
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/*
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| 259 |
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* Vendor specific stuff
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*/
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#ifdef CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT
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#define SCSI_NCR_SETUP_LED_PIN (1)
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#define SCSI_NCR_SETUP_DIFF_SUPPORT (4)
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#else
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#define SCSI_NCR_SETUP_LED_PIN (0)
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#define SCSI_NCR_SETUP_DIFF_SUPPORT (0)
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#endif
|
| 268 |
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/*
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| 270 |
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* Settle time after reset at boot-up
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| 271 |
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*/
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| 272 |
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#define SCSI_NCR_SETUP_SETTLE_TIME (2)
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| 273 |
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| 274 |
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/*
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| 275 |
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** Bridge quirks work-around option defaulted to 1.
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| 276 |
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*/
|
| 277 |
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#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
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| 278 |
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#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
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| 279 |
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#endif
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| 280 |
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| 281 |
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/*
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| 282 |
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** Work-around common bridge misbehaviour.
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| 283 |
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**
|
| 284 |
|
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** - Do not flush posted writes in the opposite
|
| 285 |
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** direction on read.
|
| 286 |
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** - May reorder DMA writes to memory.
|
| 287 |
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**
|
| 288 |
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** This option should not affect performances
|
| 289 |
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** significantly, so it is the default.
|
| 290 |
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*/
|
| 291 |
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#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
|
| 292 |
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#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
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| 293 |
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#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
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| 294 |
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#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
|
| 295 |
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|
| 296 |
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/*
|
| 297 |
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** Same as option 1, but also deal with
|
| 298 |
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** misconfigured interrupts.
|
| 299 |
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**
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| 300 |
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** - Edge triggerred instead of level sensitive.
|
| 301 |
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** - No interrupt line connected.
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| 302 |
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** - IRQ number misconfigured.
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| 303 |
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**
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| 304 |
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** If no interrupt is delivered, the driver will
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| 305 |
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** catch the interrupt conditions 10 times per
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| 306 |
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** second. No need to say that this option is
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** not recommended.
|
| 308 |
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*/
|
| 309 |
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#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
|
| 310 |
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#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
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| 311 |
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#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
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| 312 |
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#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
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| 313 |
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#define SCSI_NCR_PCIQ_BROKEN_INTR
|
| 314 |
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|
| 315 |
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/*
|
| 316 |
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** Some bridge designers decided to flush
|
| 317 |
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** everything prior to deliver the interrupt.
|
| 318 |
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** This option tries to deal with such a
|
| 319 |
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** behaviour.
|
| 320 |
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*/
|
| 321 |
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#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
|
| 322 |
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#define SCSI_NCR_PCIQ_SYNC_ON_INTR
|
| 323 |
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#endif
|
| 324 |
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| 325 |
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/*
|
| 326 |
|
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** Other parameters not configurable with "make config"
|
| 327 |
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** Avoid to change these constants, unless you know what you are doing.
|
| 328 |
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*/
|
| 329 |
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| 330 |
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#define SCSI_NCR_ALWAYS_SIMPLE_TAG
|
| 331 |
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#define SCSI_NCR_MAX_SCATTER (127)
|
| 332 |
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#define SCSI_NCR_MAX_TARGET (16)
|
| 333 |
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| 334 |
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/*
|
| 335 |
|
|
** Compute some desirable value for CAN_QUEUE
|
| 336 |
|
|
** and CMD_PER_LUN.
|
| 337 |
|
|
** The driver will use lower values if these
|
| 338 |
|
|
** ones appear to be too large.
|
| 339 |
|
|
*/
|
| 340 |
|
|
#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
|
| 341 |
|
|
#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
|
| 342 |
|
|
|
| 343 |
|
|
#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
|
| 344 |
|
|
#define SCSI_NCR_TIMER_INTERVAL (HZ)
|
| 345 |
|
|
|
| 346 |
|
|
#if 1 /* defined CONFIG_SCSI_MULTI_LUN */
|
| 347 |
|
|
#define SCSI_NCR_MAX_LUN (16)
|
| 348 |
|
|
#else
|
| 349 |
|
|
#define SCSI_NCR_MAX_LUN (1)
|
| 350 |
|
|
#endif
|
| 351 |
|
|
|
| 352 |
|
|
#ifndef HOSTS_C
|
| 353 |
|
|
|
| 354 |
|
|
/*
|
| 355 |
|
|
** These simple macros limit expression involving
|
| 356 |
|
|
** kernel time values (jiffies) to some that have
|
| 357 |
|
|
** chance not to be too much incorrect. :-)
|
| 358 |
|
|
*/
|
| 359 |
|
|
#define ktime_get(o) (jiffies + (u_long) o)
|
| 360 |
|
|
#define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
|
| 361 |
|
|
#define ktime_dif(a, b) ((long)(a) - (long)(b))
|
| 362 |
|
|
/* These ones are not used in this driver */
|
| 363 |
|
|
#define ktime_add(a, o) ((a) + (u_long)(o))
|
| 364 |
|
|
#define ktime_sub(a, o) ((a) - (u_long)(o))
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
/*
|
| 368 |
|
|
* IO functions definition for big/little endian CPU support.
|
| 369 |
|
|
* For now, the NCR is only supported in little endian addressing mode,
|
| 370 |
|
|
*/
|
| 371 |
|
|
|
| 372 |
|
|
#ifdef __BIG_ENDIAN
|
| 373 |
|
|
|
| 374 |
|
|
#if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
|
| 375 |
|
|
#error "BIG ENDIAN byte ordering needs kernel version >= 2.1.0"
|
| 376 |
|
|
#endif
|
| 377 |
|
|
|
| 378 |
|
|
#define inw_l2b inw
|
| 379 |
|
|
#define inl_l2b inl
|
| 380 |
|
|
#define outw_b2l outw
|
| 381 |
|
|
#define outl_b2l outl
|
| 382 |
|
|
|
| 383 |
|
|
#define readb_raw readb
|
| 384 |
|
|
#define writeb_raw writeb
|
| 385 |
|
|
|
| 386 |
|
|
#if defined(__hppa__)
|
| 387 |
|
|
#define readw_l2b(a) le16_to_cpu(readw(a))
|
| 388 |
|
|
#define readl_l2b(a) le32_to_cpu(readl(a))
|
| 389 |
|
|
#define writew_b2l(v,a) writew(cpu_to_le16(v),a)
|
| 390 |
|
|
#define writel_b2l(v,a) writel(cpu_to_le32(v),a)
|
| 391 |
|
|
#elif defined(__mips__)
|
| 392 |
|
|
#define readw_l2b readw
|
| 393 |
|
|
#define readl_l2b readl
|
| 394 |
|
|
#define writew_b2l writew
|
| 395 |
|
|
#define writel_b2l writel
|
| 396 |
|
|
#define inw_l2b inw
|
| 397 |
|
|
#define inl_l2b inl
|
| 398 |
|
|
#define outw_b2l outw
|
| 399 |
|
|
#define outl_b2l outl
|
| 400 |
|
|
#else /* Other big-endian */
|
| 401 |
|
|
#define readw_l2b readw
|
| 402 |
|
|
#define readl_l2b readl
|
| 403 |
|
|
#define writew_b2l writew
|
| 404 |
|
|
#define writel_b2l writel
|
| 405 |
|
|
#endif
|
| 406 |
|
|
|
| 407 |
|
|
#else /* little endian */
|
| 408 |
|
|
|
| 409 |
|
|
#define inw_raw inw
|
| 410 |
|
|
#define inl_raw inl
|
| 411 |
|
|
#define outw_raw outw
|
| 412 |
|
|
#define outl_raw outl
|
| 413 |
|
|
|
| 414 |
|
|
#if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
|
| 415 |
|
|
#define readb_raw(a) (*(volatile unsigned char *) (a))
|
| 416 |
|
|
#define readw_raw(a) (*(volatile unsigned short *) (a))
|
| 417 |
|
|
#define readl_raw(a) (*(volatile unsigned int *) (a))
|
| 418 |
|
|
#define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
|
| 419 |
|
|
#define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
|
| 420 |
|
|
#define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
|
| 421 |
|
|
|
| 422 |
|
|
#else /* Other little-endian */
|
| 423 |
|
|
#define readb_raw readb
|
| 424 |
|
|
#define readw_raw readw
|
| 425 |
|
|
#define readl_raw readl
|
| 426 |
|
|
#define writeb_raw writeb
|
| 427 |
|
|
#define writew_raw writew
|
| 428 |
|
|
#define writel_raw writel
|
| 429 |
|
|
|
| 430 |
|
|
#endif
|
| 431 |
|
|
#endif
|
| 432 |
|
|
|
| 433 |
|
|
#ifdef SCSI_NCR_BIG_ENDIAN
|
| 434 |
|
|
#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
|
| 435 |
|
|
#endif
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
/*
|
| 439 |
|
|
* IA32 architecture does not reorder STORES and prevents
|
| 440 |
|
|
* LOADS from passing STORES. It is called `program order'
|
| 441 |
|
|
* by Intel and allows device drivers to deal with memory
|
| 442 |
|
|
* ordering by only ensuring that the code is not reordered
|
| 443 |
|
|
* by the compiler when ordering is required.
|
| 444 |
|
|
* Other architectures implement a weaker ordering that
|
| 445 |
|
|
* requires memory barriers (and also IO barriers when they
|
| 446 |
|
|
* make sense) to be used.
|
| 447 |
|
|
* We want to be paranoid for ppc and ia64. :)
|
| 448 |
|
|
*/
|
| 449 |
|
|
|
| 450 |
|
|
#if defined(__i386__) || defined(__x86_64__)
|
| 451 |
|
|
#define MEMORY_BARRIER() do { ; } while(0)
|
| 452 |
|
|
#elif defined __powerpc__
|
| 453 |
|
|
#define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
|
| 454 |
|
|
#elif defined __ia64__
|
| 455 |
|
|
#define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
|
| 456 |
|
|
#else
|
| 457 |
|
|
#define MEMORY_BARRIER() mb()
|
| 458 |
|
|
#endif
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
/*
|
| 462 |
|
|
* If the NCR uses big endian addressing mode over the
|
| 463 |
|
|
* PCI, actual io register addresses for byte and word
|
| 464 |
|
|
* accesses must be changed according to lane routing.
|
| 465 |
|
|
* Btw, ncr_offb() and ncr_offw() macros only apply to
|
| 466 |
|
|
* constants and so donnot generate bloated code.
|
| 467 |
|
|
*/
|
| 468 |
|
|
|
| 469 |
|
|
#if defined(SCSI_NCR_BIG_ENDIAN)
|
| 470 |
|
|
|
| 471 |
|
|
#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
|
| 472 |
|
|
#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
|
| 473 |
|
|
|
| 474 |
|
|
#else
|
| 475 |
|
|
|
| 476 |
|
|
#define ncr_offb(o) (o)
|
| 477 |
|
|
#define ncr_offw(o) (o)
|
| 478 |
|
|
|
| 479 |
|
|
#endif
|
| 480 |
|
|
|
| 481 |
|
|
/*
|
| 482 |
|
|
* If the CPU and the NCR use same endian-ness adressing,
|
| 483 |
|
|
* no byte reordering is needed for script patching.
|
| 484 |
|
|
* Macro cpu_to_scr() is to be used for script patching.
|
| 485 |
|
|
* Macro scr_to_cpu() is to be used for getting a DWORD
|
| 486 |
|
|
* from the script.
|
| 487 |
|
|
*/
|
| 488 |
|
|
|
| 489 |
|
|
#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
|
| 490 |
|
|
|
| 491 |
|
|
#define cpu_to_scr(dw) cpu_to_le32(dw)
|
| 492 |
|
|
#define scr_to_cpu(dw) le32_to_cpu(dw)
|
| 493 |
|
|
|
| 494 |
|
|
#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
|
| 495 |
|
|
|
| 496 |
|
|
#define cpu_to_scr(dw) cpu_to_be32(dw)
|
| 497 |
|
|
#define scr_to_cpu(dw) be32_to_cpu(dw)
|
| 498 |
|
|
|
| 499 |
|
|
#else
|
| 500 |
|
|
|
| 501 |
|
|
#define cpu_to_scr(dw) (dw)
|
| 502 |
|
|
#define scr_to_cpu(dw) (dw)
|
| 503 |
|
|
|
| 504 |
|
|
#endif
|
| 505 |
|
|
|
| 506 |
|
|
/*
|
| 507 |
|
|
* Access to the controller chip.
|
| 508 |
|
|
*
|
| 509 |
|
|
* If SCSI_NCR_IOMAPPED is defined, the driver will use
|
| 510 |
|
|
* normal IOs instead of the MEMORY MAPPED IO method
|
| 511 |
|
|
* recommended by PCI specifications.
|
| 512 |
|
|
* If all PCI bridges, host brigdes and architectures
|
| 513 |
|
|
* would have been correctly designed for PCI, this
|
| 514 |
|
|
* option would be useless.
|
| 515 |
|
|
*
|
| 516 |
|
|
* If the CPU and the NCR use same endian-ness adressing,
|
| 517 |
|
|
* no byte reordering is needed for accessing chip io
|
| 518 |
|
|
* registers. Functions suffixed by '_raw' are assumed
|
| 519 |
|
|
* to access the chip over the PCI without doing byte
|
| 520 |
|
|
* reordering. Functions suffixed by '_l2b' are
|
| 521 |
|
|
* assumed to perform little-endian to big-endian byte
|
| 522 |
|
|
* reordering, those suffixed by '_b2l' blah, blah,
|
| 523 |
|
|
* blah, ...
|
| 524 |
|
|
*/
|
| 525 |
|
|
|
| 526 |
|
|
#if defined(SCSI_NCR_IOMAPPED)
|
| 527 |
|
|
|
| 528 |
|
|
/*
|
| 529 |
|
|
* IO mapped only input / ouput
|
| 530 |
|
|
*/
|
| 531 |
|
|
|
| 532 |
|
|
#define INB_OFF(o) inb (np->base_io + ncr_offb(o))
|
| 533 |
|
|
#define OUTB_OFF(o, val) outb ((val), np->base_io + ncr_offb(o))
|
| 534 |
|
|
|
| 535 |
|
|
#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
|
| 536 |
|
|
|
| 537 |
|
|
#define INW_OFF(o) inw_l2b (np->base_io + ncr_offw(o))
|
| 538 |
|
|
#define INL_OFF(o) inl_l2b (np->base_io + (o))
|
| 539 |
|
|
|
| 540 |
|
|
#define OUTW_OFF(o, val) outw_b2l ((val), np->base_io + ncr_offw(o))
|
| 541 |
|
|
#define OUTL_OFF(o, val) outl_b2l ((val), np->base_io + (o))
|
| 542 |
|
|
|
| 543 |
|
|
#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
|
| 544 |
|
|
|
| 545 |
|
|
#define INW_OFF(o) inw_b2l (np->base_io + ncr_offw(o))
|
| 546 |
|
|
#define INL_OFF(o) inl_b2l (np->base_io + (o))
|
| 547 |
|
|
|
| 548 |
|
|
#define OUTW_OFF(o, val) outw_l2b ((val), np->base_io + ncr_offw(o))
|
| 549 |
|
|
#define OUTL_OFF(o, val) outl_l2b ((val), np->base_io + (o))
|
| 550 |
|
|
|
| 551 |
|
|
#else
|
| 552 |
|
|
|
| 553 |
|
|
#define INW_OFF(o) inw_raw (np->base_io + ncr_offw(o))
|
| 554 |
|
|
#define INL_OFF(o) inl_raw (np->base_io + (o))
|
| 555 |
|
|
|
| 556 |
|
|
#define OUTW_OFF(o, val) outw_raw ((val), np->base_io + ncr_offw(o))
|
| 557 |
|
|
#define OUTL_OFF(o, val) outl_raw ((val), np->base_io + (o))
|
| 558 |
|
|
|
| 559 |
|
|
#endif /* ENDIANs */
|
| 560 |
|
|
|
| 561 |
|
|
#else /* defined SCSI_NCR_IOMAPPED */
|
| 562 |
|
|
|
| 563 |
|
|
/*
|
| 564 |
|
|
* MEMORY mapped IO input / output
|
| 565 |
|
|
*/
|
| 566 |
|
|
|
| 567 |
|
|
#define INB_OFF(o) readb_raw((char *)np->reg + ncr_offb(o))
|
| 568 |
|
|
#define OUTB_OFF(o, val) writeb_raw((val), (char *)np->reg + ncr_offb(o))
|
| 569 |
|
|
|
| 570 |
|
|
#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
|
| 571 |
|
|
|
| 572 |
|
|
#define INW_OFF(o) readw_l2b((char *)np->reg + ncr_offw(o))
|
| 573 |
|
|
#define INL_OFF(o) readl_l2b((char *)np->reg + (o))
|
| 574 |
|
|
|
| 575 |
|
|
#define OUTW_OFF(o, val) writew_b2l((val), (char *)np->reg + ncr_offw(o))
|
| 576 |
|
|
#define OUTL_OFF(o, val) writel_b2l((val), (char *)np->reg + (o))
|
| 577 |
|
|
|
| 578 |
|
|
#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
|
| 579 |
|
|
|
| 580 |
|
|
#define INW_OFF(o) readw_b2l((char *)np->reg + ncr_offw(o))
|
| 581 |
|
|
#define INL_OFF(o) readl_b2l((char *)np->reg + (o))
|
| 582 |
|
|
|
| 583 |
|
|
#define OUTW_OFF(o, val) writew_l2b((val), (char *)np->reg + ncr_offw(o))
|
| 584 |
|
|
#define OUTL_OFF(o, val) writel_l2b((val), (char *)np->reg + (o))
|
| 585 |
|
|
|
| 586 |
|
|
#else
|
| 587 |
|
|
|
| 588 |
|
|
#define INW_OFF(o) readw_raw((char *)np->reg + ncr_offw(o))
|
| 589 |
|
|
#define INL_OFF(o) readl_raw((char *)np->reg + (o))
|
| 590 |
|
|
|
| 591 |
|
|
#define OUTW_OFF(o, val) writew_raw((val), (char *)np->reg + ncr_offw(o))
|
| 592 |
|
|
#define OUTL_OFF(o, val) writel_raw((val), (char *)np->reg + (o))
|
| 593 |
|
|
|
| 594 |
|
|
#endif
|
| 595 |
|
|
|
| 596 |
|
|
#endif /* defined SCSI_NCR_IOMAPPED */
|
| 597 |
|
|
|
| 598 |
|
|
#define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
|
| 599 |
|
|
#define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
|
| 600 |
|
|
#define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
|
| 601 |
|
|
|
| 602 |
|
|
#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
|
| 603 |
|
|
#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
|
| 604 |
|
|
#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
|
| 605 |
|
|
|
| 606 |
|
|
/*
|
| 607 |
|
|
* Set bit field ON, OFF
|
| 608 |
|
|
*/
|
| 609 |
|
|
|
| 610 |
|
|
#define OUTONB(r, m) OUTB(r, INB(r) | (m))
|
| 611 |
|
|
#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
|
| 612 |
|
|
#define OUTONW(r, m) OUTW(r, INW(r) | (m))
|
| 613 |
|
|
#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
|
| 614 |
|
|
#define OUTONL(r, m) OUTL(r, INL(r) | (m))
|
| 615 |
|
|
#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
|
| 616 |
|
|
|
| 617 |
|
|
/*
|
| 618 |
|
|
* We normally want the chip to have a consistent view
|
| 619 |
|
|
* of driver internal data structures when we restart it.
|
| 620 |
|
|
* Thus these macros.
|
| 621 |
|
|
*/
|
| 622 |
|
|
#define OUTL_DSP(v) \
|
| 623 |
|
|
do { \
|
| 624 |
|
|
MEMORY_BARRIER(); \
|
| 625 |
|
|
OUTL (nc_dsp, (v)); \
|
| 626 |
|
|
} while (0)
|
| 627 |
|
|
|
| 628 |
|
|
#define OUTONB_STD() \
|
| 629 |
|
|
do { \
|
| 630 |
|
|
MEMORY_BARRIER(); \
|
| 631 |
|
|
OUTONB (nc_dcntl, (STD|NOCOM)); \
|
| 632 |
|
|
} while (0)
|
| 633 |
|
|
|
| 634 |
|
|
|
| 635 |
|
|
/*
|
| 636 |
|
|
** NCR53C8XX Device Ids
|
| 637 |
|
|
*/
|
| 638 |
|
|
|
| 639 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C810
|
| 640 |
|
|
#define PCI_DEVICE_ID_NCR_53C810 1
|
| 641 |
|
|
#endif
|
| 642 |
|
|
|
| 643 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C810AP
|
| 644 |
|
|
#define PCI_DEVICE_ID_NCR_53C810AP 5
|
| 645 |
|
|
#endif
|
| 646 |
|
|
|
| 647 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C815
|
| 648 |
|
|
#define PCI_DEVICE_ID_NCR_53C815 4
|
| 649 |
|
|
#endif
|
| 650 |
|
|
|
| 651 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C820
|
| 652 |
|
|
#define PCI_DEVICE_ID_NCR_53C820 2
|
| 653 |
|
|
#endif
|
| 654 |
|
|
|
| 655 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C825
|
| 656 |
|
|
#define PCI_DEVICE_ID_NCR_53C825 3
|
| 657 |
|
|
#endif
|
| 658 |
|
|
|
| 659 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C860
|
| 660 |
|
|
#define PCI_DEVICE_ID_NCR_53C860 6
|
| 661 |
|
|
#endif
|
| 662 |
|
|
|
| 663 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C875
|
| 664 |
|
|
#define PCI_DEVICE_ID_NCR_53C875 0xf
|
| 665 |
|
|
#endif
|
| 666 |
|
|
|
| 667 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C875J
|
| 668 |
|
|
#define PCI_DEVICE_ID_NCR_53C875J 0x8f
|
| 669 |
|
|
#endif
|
| 670 |
|
|
|
| 671 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C885
|
| 672 |
|
|
#define PCI_DEVICE_ID_NCR_53C885 0xd
|
| 673 |
|
|
#endif
|
| 674 |
|
|
|
| 675 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C895
|
| 676 |
|
|
#define PCI_DEVICE_ID_NCR_53C895 0xc
|
| 677 |
|
|
#endif
|
| 678 |
|
|
|
| 679 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C896
|
| 680 |
|
|
#define PCI_DEVICE_ID_NCR_53C896 0xb
|
| 681 |
|
|
#endif
|
| 682 |
|
|
|
| 683 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C895A
|
| 684 |
|
|
#define PCI_DEVICE_ID_NCR_53C895A 0x12
|
| 685 |
|
|
#endif
|
| 686 |
|
|
|
| 687 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C875A
|
| 688 |
|
|
#define PCI_DEVICE_ID_NCR_53C875A 0x13
|
| 689 |
|
|
#endif
|
| 690 |
|
|
|
| 691 |
|
|
#ifndef PCI_DEVICE_ID_NCR_53C1510D
|
| 692 |
|
|
#define PCI_DEVICE_ID_NCR_53C1510D 0xa
|
| 693 |
|
|
#endif
|
| 694 |
|
|
|
| 695 |
|
|
#ifndef PCI_DEVICE_ID_LSI_53C1010
|
| 696 |
|
|
#define PCI_DEVICE_ID_LSI_53C1010 0x20
|
| 697 |
|
|
#endif
|
| 698 |
|
|
|
| 699 |
|
|
#ifndef PCI_DEVICE_ID_LSI_53C1010_66
|
| 700 |
|
|
#define PCI_DEVICE_ID_LSI_53C1010_66 0x21
|
| 701 |
|
|
#endif
|
| 702 |
|
|
|
| 703 |
|
|
|
| 704 |
|
|
/*
|
| 705 |
|
|
** NCR53C8XX devices features table.
|
| 706 |
|
|
*/
|
| 707 |
|
|
typedef struct {
|
| 708 |
|
|
unsigned short device_id;
|
| 709 |
|
|
unsigned short revision_id;
|
| 710 |
|
|
char *name;
|
| 711 |
|
|
unsigned char burst_max; /* log-base-2 of max burst */
|
| 712 |
|
|
unsigned char offset_max;
|
| 713 |
|
|
unsigned char nr_divisor;
|
| 714 |
|
|
unsigned int features;
|
| 715 |
|
|
#define FE_LED0 (1<<0)
|
| 716 |
|
|
#define FE_WIDE (1<<1) /* Wide data transfers */
|
| 717 |
|
|
#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
|
| 718 |
|
|
#define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
|
| 719 |
|
|
#define FE_DBLR (1<<4) /* Clock doubler present */
|
| 720 |
|
|
#define FE_QUAD (1<<5) /* Clock quadrupler present */
|
| 721 |
|
|
#define FE_ERL (1<<6) /* Enable read line */
|
| 722 |
|
|
#define FE_CLSE (1<<7) /* Cache line size enable */
|
| 723 |
|
|
#define FE_WRIE (1<<8) /* Write & Invalidate enable */
|
| 724 |
|
|
#define FE_ERMP (1<<9) /* Enable read multiple */
|
| 725 |
|
|
#define FE_BOF (1<<10) /* Burst opcode fetch */
|
| 726 |
|
|
#define FE_DFS (1<<11) /* DMA fifo size */
|
| 727 |
|
|
#define FE_PFEN (1<<12) /* Prefetch enable */
|
| 728 |
|
|
#define FE_LDSTR (1<<13) /* Load/Store supported */
|
| 729 |
|
|
#define FE_RAM (1<<14) /* On chip RAM present */
|
| 730 |
|
|
#define FE_VARCLK (1<<15) /* SCSI clock may vary */
|
| 731 |
|
|
#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
|
| 732 |
|
|
#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
|
| 733 |
|
|
#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
|
| 734 |
|
|
#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
|
| 735 |
|
|
#define FE_LEDC (1<<20) /* Hardware control of LED */
|
| 736 |
|
|
#define FE_DIFF (1<<21) /* Support Differential SCSI */
|
| 737 |
|
|
#define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */
|
| 738 |
|
|
#define FE_66MHZ (1<<23) /* 66MHz PCI Support */
|
| 739 |
|
|
#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
|
| 740 |
|
|
#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
|
| 741 |
|
|
#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
|
| 742 |
|
|
|
| 743 |
|
|
#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
|
| 744 |
|
|
#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
|
| 745 |
|
|
#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
|
| 746 |
|
|
} ncr_chip;
|
| 747 |
|
|
|
| 748 |
|
|
/*
|
| 749 |
|
|
** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
|
| 750 |
|
|
** Memory Read transaction terminated by a retry followed by
|
| 751 |
|
|
** Memory Read Line command.
|
| 752 |
|
|
*/
|
| 753 |
|
|
#define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
|
| 754 |
|
|
|
| 755 |
|
|
/*
|
| 756 |
|
|
** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
|
| 757 |
|
|
** On paper, this errata is harmless. But it is a good reason for
|
| 758 |
|
|
** using a shorter programmed burst length (64 DWORDS instead of 128).
|
| 759 |
|
|
*/
|
| 760 |
|
|
|
| 761 |
|
|
#define SCSI_NCR_CHIP_TABLE \
|
| 762 |
|
|
{ \
|
| 763 |
|
|
{PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
|
| 764 |
|
|
FE_ERL} \
|
| 765 |
|
|
, \
|
| 766 |
|
|
{PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
|
| 767 |
|
|
FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
|
| 768 |
|
|
, \
|
| 769 |
|
|
{PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
|
| 770 |
|
|
FE_ERL|FE_BOF} \
|
| 771 |
|
|
, \
|
| 772 |
|
|
{PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
|
| 773 |
|
|
FE_WIDE|FE_ERL} \
|
| 774 |
|
|
, \
|
| 775 |
|
|
{PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
|
| 776 |
|
|
FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \
|
| 777 |
|
|
, \
|
| 778 |
|
|
{PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
|
| 779 |
|
|
FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \
|
| 780 |
|
|
, \
|
| 781 |
|
|
{PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
|
| 782 |
|
|
FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
|
| 783 |
|
|
, \
|
| 784 |
|
|
{PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
|
| 785 |
|
|
FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 786 |
|
|
FE_RAM|FE_DIFF|FE_VARCLK} \
|
| 787 |
|
|
, \
|
| 788 |
|
|
{PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, \
|
| 789 |
|
|
FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 790 |
|
|
FE_RAM|FE_DIFF|FE_VARCLK} \
|
| 791 |
|
|
, \
|
| 792 |
|
|
{PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
|
| 793 |
|
|
FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 794 |
|
|
FE_RAM|FE_VARCLK} \
|
| 795 |
|
|
, \
|
| 796 |
|
|
{PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
|
| 797 |
|
|
FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 798 |
|
|
FE_RAM|FE_DIFF|FE_VARCLK} \
|
| 799 |
|
|
, \
|
| 800 |
|
|
{PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
|
| 801 |
|
|
FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 802 |
|
|
FE_RAM} \
|
| 803 |
|
|
, \
|
| 804 |
|
|
{PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \
|
| 805 |
|
|
FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 806 |
|
|
FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ISTAT1} \
|
| 807 |
|
|
, \
|
| 808 |
|
|
{PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \
|
| 809 |
|
|
FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 810 |
|
|
FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
|
| 811 |
|
|
, \
|
| 812 |
|
|
{PCI_DEVICE_ID_NCR_53C875A, 0xff, "875a", 6, 31, 7, \
|
| 813 |
|
|
FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 814 |
|
|
FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
|
| 815 |
|
|
, \
|
| 816 |
|
|
{PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \
|
| 817 |
|
|
FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
|
| 818 |
|
|
FE_RAM|FE_IO256} \
|
| 819 |
|
|
, \
|
| 820 |
|
|
{PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010-33", 6, 62, 7, \
|
| 821 |
|
|
FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
|
| 822 |
|
|
FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \
|
| 823 |
|
|
, \
|
| 824 |
|
|
{PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 62, 7, \
|
| 825 |
|
|
FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
|
| 826 |
|
|
FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3| \
|
| 827 |
|
|
FE_66MHZ} \
|
| 828 |
|
|
}
|
| 829 |
|
|
|
| 830 |
|
|
/*
|
| 831 |
|
|
* List of supported NCR chip ids
|
| 832 |
|
|
*/
|
| 833 |
|
|
#define SCSI_NCR_CHIP_IDS \
|
| 834 |
|
|
{ \
|
| 835 |
|
|
PCI_DEVICE_ID_NCR_53C810, \
|
| 836 |
|
|
PCI_DEVICE_ID_NCR_53C815, \
|
| 837 |
|
|
PCI_DEVICE_ID_NCR_53C820, \
|
| 838 |
|
|
PCI_DEVICE_ID_NCR_53C825, \
|
| 839 |
|
|
PCI_DEVICE_ID_NCR_53C860, \
|
| 840 |
|
|
PCI_DEVICE_ID_NCR_53C875, \
|
| 841 |
|
|
PCI_DEVICE_ID_NCR_53C875J, \
|
| 842 |
|
|
PCI_DEVICE_ID_NCR_53C885, \
|
| 843 |
|
|
PCI_DEVICE_ID_NCR_53C895, \
|
| 844 |
|
|
PCI_DEVICE_ID_NCR_53C896, \
|
| 845 |
|
|
PCI_DEVICE_ID_NCR_53C895A, \
|
| 846 |
|
|
PCI_DEVICE_ID_NCR_53C1510D, \
|
| 847 |
|
|
PCI_DEVICE_ID_LSI_53C1010, \
|
| 848 |
|
|
PCI_DEVICE_ID_LSI_53C1010_66 \
|
| 849 |
|
|
}
|
| 850 |
|
|
|
| 851 |
|
|
/*
|
| 852 |
|
|
** Driver setup structure.
|
| 853 |
|
|
**
|
| 854 |
|
|
** This structure is initialized from linux config options.
|
| 855 |
|
|
** It can be overridden at boot-up by the boot command line.
|
| 856 |
|
|
*/
|
| 857 |
|
|
#define SCSI_NCR_MAX_EXCLUDES 8
|
| 858 |
|
|
struct ncr_driver_setup {
|
| 859 |
|
|
u_char master_parity;
|
| 860 |
|
|
u_char scsi_parity;
|
| 861 |
|
|
u_char disconnection;
|
| 862 |
|
|
u_char special_features;
|
| 863 |
|
|
u_char force_sync_nego;
|
| 864 |
|
|
u_char reverse_probe;
|
| 865 |
|
|
u_char pci_fix_up;
|
| 866 |
|
|
u_char use_nvram;
|
| 867 |
|
|
u_char verbose;
|
| 868 |
|
|
u_char default_tags;
|
| 869 |
|
|
u_short default_sync;
|
| 870 |
|
|
u_short debug;
|
| 871 |
|
|
u_char burst_max;
|
| 872 |
|
|
u_char led_pin;
|
| 873 |
|
|
u_char max_wide;
|
| 874 |
|
|
u_char settle_delay;
|
| 875 |
|
|
u_char diff_support;
|
| 876 |
|
|
u_char irqm;
|
| 877 |
|
|
u_char bus_check;
|
| 878 |
|
|
u_char optimize;
|
| 879 |
|
|
u_char recovery;
|
| 880 |
|
|
u_char host_id;
|
| 881 |
|
|
u_short iarb;
|
| 882 |
|
|
u_long excludes[SCSI_NCR_MAX_EXCLUDES];
|
| 883 |
|
|
char tag_ctrl[100];
|
| 884 |
|
|
};
|
| 885 |
|
|
|
| 886 |
|
|
/*
|
| 887 |
|
|
** Initial setup.
|
| 888 |
|
|
** Can be overriden at startup by a command line.
|
| 889 |
|
|
*/
|
| 890 |
|
|
#define SCSI_NCR_DRIVER_SETUP \
|
| 891 |
|
|
{ \
|
| 892 |
|
|
SCSI_NCR_SETUP_MASTER_PARITY, \
|
| 893 |
|
|
SCSI_NCR_SETUP_SCSI_PARITY, \
|
| 894 |
|
|
SCSI_NCR_SETUP_DISCONNECTION, \
|
| 895 |
|
|
SCSI_NCR_SETUP_SPECIAL_FEATURES, \
|
| 896 |
|
|
SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
|
| 897 |
|
|
0, \
|
| 898 |
|
|
0, \
|
| 899 |
|
|
1, \
|
| 900 |
|
|
0, \
|
| 901 |
|
|
SCSI_NCR_SETUP_DEFAULT_TAGS, \
|
| 902 |
|
|
SCSI_NCR_SETUP_DEFAULT_SYNC, \
|
| 903 |
|
|
0x00, \
|
| 904 |
|
|
7, \
|
| 905 |
|
|
SCSI_NCR_SETUP_LED_PIN, \
|
| 906 |
|
|
1, \
|
| 907 |
|
|
SCSI_NCR_SETUP_SETTLE_TIME, \
|
| 908 |
|
|
SCSI_NCR_SETUP_DIFF_SUPPORT, \
|
| 909 |
|
|
0, \
|
| 910 |
|
|
1, \
|
| 911 |
|
|
0, \
|
| 912 |
|
|
0, \
|
| 913 |
|
|
255, \
|
| 914 |
|
|
0x00 \
|
| 915 |
|
|
}
|
| 916 |
|
|
|
| 917 |
|
|
/*
|
| 918 |
|
|
** Boot fail safe setup.
|
| 919 |
|
|
** Override initial setup from boot command line:
|
| 920 |
|
|
** ncr53c8xx=safe:y
|
| 921 |
|
|
*/
|
| 922 |
|
|
#define SCSI_NCR_DRIVER_SAFE_SETUP \
|
| 923 |
|
|
{ \
|
| 924 |
|
|
0, \
|
| 925 |
|
|
1, \
|
| 926 |
|
|
0, \
|
| 927 |
|
|
0, \
|
| 928 |
|
|
0, \
|
| 929 |
|
|
0, \
|
| 930 |
|
|
0, \
|
| 931 |
|
|
1, \
|
| 932 |
|
|
2, \
|
| 933 |
|
|
0, \
|
| 934 |
|
|
255, \
|
| 935 |
|
|
0x00, \
|
| 936 |
|
|
255, \
|
| 937 |
|
|
0, \
|
| 938 |
|
|
0, \
|
| 939 |
|
|
10, \
|
| 940 |
|
|
1, \
|
| 941 |
|
|
1, \
|
| 942 |
|
|
1, \
|
| 943 |
|
|
0, \
|
| 944 |
|
|
0, \
|
| 945 |
|
|
255 \
|
| 946 |
|
|
}
|
| 947 |
|
|
|
| 948 |
|
|
#ifdef SCSI_NCR_NVRAM_SUPPORT
|
| 949 |
|
|
/*
|
| 950 |
|
|
** Symbios NvRAM data format
|
| 951 |
|
|
*/
|
| 952 |
|
|
#define SYMBIOS_NVRAM_SIZE 368
|
| 953 |
|
|
#define SYMBIOS_NVRAM_ADDRESS 0x100
|
| 954 |
|
|
|
| 955 |
|
|
struct Symbios_nvram {
|
| 956 |
|
|
/* Header 6 bytes */
|
| 957 |
|
|
u_short type; /* 0x0000 */
|
| 958 |
|
|
u_short byte_count; /* excluding header/trailer */
|
| 959 |
|
|
u_short checksum;
|
| 960 |
|
|
|
| 961 |
|
|
/* Controller set up 20 bytes */
|
| 962 |
|
|
u_char v_major; /* 0x00 */
|
| 963 |
|
|
u_char v_minor; /* 0x30 */
|
| 964 |
|
|
u_int32 boot_crc;
|
| 965 |
|
|
u_short flags;
|
| 966 |
|
|
#define SYMBIOS_SCAM_ENABLE (1)
|
| 967 |
|
|
#define SYMBIOS_PARITY_ENABLE (1<<1)
|
| 968 |
|
|
#define SYMBIOS_VERBOSE_MSGS (1<<2)
|
| 969 |
|
|
#define SYMBIOS_CHS_MAPPING (1<<3)
|
| 970 |
|
|
#define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
|
| 971 |
|
|
u_short flags1;
|
| 972 |
|
|
#define SYMBIOS_SCAN_HI_LO (1)
|
| 973 |
|
|
u_short term_state;
|
| 974 |
|
|
#define SYMBIOS_TERM_CANT_PROGRAM (0)
|
| 975 |
|
|
#define SYMBIOS_TERM_ENABLED (1)
|
| 976 |
|
|
#define SYMBIOS_TERM_DISABLED (2)
|
| 977 |
|
|
u_short rmvbl_flags;
|
| 978 |
|
|
#define SYMBIOS_RMVBL_NO_SUPPORT (0)
|
| 979 |
|
|
#define SYMBIOS_RMVBL_BOOT_DEVICE (1)
|
| 980 |
|
|
#define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
|
| 981 |
|
|
u_char host_id;
|
| 982 |
|
|
u_char num_hba; /* 0x04 */
|
| 983 |
|
|
u_char num_devices; /* 0x10 */
|
| 984 |
|
|
u_char max_scam_devices; /* 0x04 */
|
| 985 |
|
|
u_char num_valid_scam_devives; /* 0x00 */
|
| 986 |
|
|
u_char rsvd;
|
| 987 |
|
|
|
| 988 |
|
|
/* Boot order 14 bytes * 4 */
|
| 989 |
|
|
struct Symbios_host{
|
| 990 |
|
|
u_short type; /* 4:8xx / 0:nok */
|
| 991 |
|
|
u_short device_id; /* PCI device id */
|
| 992 |
|
|
u_short vendor_id; /* PCI vendor id */
|
| 993 |
|
|
u_char bus_nr; /* PCI bus number */
|
| 994 |
|
|
u_char device_fn; /* PCI device/function number << 3*/
|
| 995 |
|
|
u_short word8;
|
| 996 |
|
|
u_short flags;
|
| 997 |
|
|
#define SYMBIOS_INIT_SCAN_AT_BOOT (1)
|
| 998 |
|
|
u_short io_port; /* PCI io_port address */
|
| 999 |
|
|
} host[4];
|
| 1000 |
|
|
|
| 1001 |
|
|
/* Targets 8 bytes * 16 */
|
| 1002 |
|
|
struct Symbios_target {
|
| 1003 |
|
|
u_char flags;
|
| 1004 |
|
|
#define SYMBIOS_DISCONNECT_ENABLE (1)
|
| 1005 |
|
|
#define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
|
| 1006 |
|
|
#define SYMBIOS_SCAN_LUNS (1<<2)
|
| 1007 |
|
|
#define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
|
| 1008 |
|
|
u_char rsvd;
|
| 1009 |
|
|
u_char bus_width; /* 0x08/0x10 */
|
| 1010 |
|
|
u_char sync_offset;
|
| 1011 |
|
|
u_short sync_period; /* 4*period factor */
|
| 1012 |
|
|
u_short timeout;
|
| 1013 |
|
|
} target[16];
|
| 1014 |
|
|
/* Scam table 8 bytes * 4 */
|
| 1015 |
|
|
struct Symbios_scam {
|
| 1016 |
|
|
u_short id;
|
| 1017 |
|
|
u_short method;
|
| 1018 |
|
|
#define SYMBIOS_SCAM_DEFAULT_METHOD (0)
|
| 1019 |
|
|
#define SYMBIOS_SCAM_DONT_ASSIGN (1)
|
| 1020 |
|
|
#define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
|
| 1021 |
|
|
#define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
|
| 1022 |
|
|
u_short status;
|
| 1023 |
|
|
#define SYMBIOS_SCAM_UNKNOWN (0)
|
| 1024 |
|
|
#define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
|
| 1025 |
|
|
#define SYMBIOS_SCAM_ID_NOT_SET (2)
|
| 1026 |
|
|
#define SYMBIOS_SCAM_ID_VALID (3)
|
| 1027 |
|
|
u_char target_id;
|
| 1028 |
|
|
u_char rsvd;
|
| 1029 |
|
|
} scam[4];
|
| 1030 |
|
|
|
| 1031 |
|
|
u_char spare_devices[15*8];
|
| 1032 |
|
|
u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
|
| 1033 |
|
|
};
|
| 1034 |
|
|
typedef struct Symbios_nvram Symbios_nvram;
|
| 1035 |
|
|
typedef struct Symbios_host Symbios_host;
|
| 1036 |
|
|
typedef struct Symbios_target Symbios_target;
|
| 1037 |
|
|
typedef struct Symbios_scam Symbios_scam;
|
| 1038 |
|
|
|
| 1039 |
|
|
/*
|
| 1040 |
|
|
** Tekram NvRAM data format.
|
| 1041 |
|
|
*/
|
| 1042 |
|
|
#define TEKRAM_NVRAM_SIZE 64
|
| 1043 |
|
|
#define TEKRAM_93C46_NVRAM_ADDRESS 0
|
| 1044 |
|
|
#define TEKRAM_24C16_NVRAM_ADDRESS 0x40
|
| 1045 |
|
|
|
| 1046 |
|
|
struct Tekram_nvram {
|
| 1047 |
|
|
struct Tekram_target {
|
| 1048 |
|
|
u_char flags;
|
| 1049 |
|
|
#define TEKRAM_PARITY_CHECK (1)
|
| 1050 |
|
|
#define TEKRAM_SYNC_NEGO (1<<1)
|
| 1051 |
|
|
#define TEKRAM_DISCONNECT_ENABLE (1<<2)
|
| 1052 |
|
|
#define TEKRAM_START_CMD (1<<3)
|
| 1053 |
|
|
#define TEKRAM_TAGGED_COMMANDS (1<<4)
|
| 1054 |
|
|
#define TEKRAM_WIDE_NEGO (1<<5)
|
| 1055 |
|
|
u_char sync_index;
|
| 1056 |
|
|
u_short word2;
|
| 1057 |
|
|
} target[16];
|
| 1058 |
|
|
u_char host_id;
|
| 1059 |
|
|
u_char flags;
|
| 1060 |
|
|
#define TEKRAM_MORE_THAN_2_DRIVES (1)
|
| 1061 |
|
|
#define TEKRAM_DRIVES_SUP_1GB (1<<1)
|
| 1062 |
|
|
#define TEKRAM_RESET_ON_POWER_ON (1<<2)
|
| 1063 |
|
|
#define TEKRAM_ACTIVE_NEGATION (1<<3)
|
| 1064 |
|
|
#define TEKRAM_IMMEDIATE_SEEK (1<<4)
|
| 1065 |
|
|
#define TEKRAM_SCAN_LUNS (1<<5)
|
| 1066 |
|
|
#define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
|
| 1067 |
|
|
u_char boot_delay_index;
|
| 1068 |
|
|
u_char max_tags_index;
|
| 1069 |
|
|
u_short flags1;
|
| 1070 |
|
|
#define TEKRAM_F2_F6_ENABLED (1)
|
| 1071 |
|
|
u_short spare[29];
|
| 1072 |
|
|
};
|
| 1073 |
|
|
typedef struct Tekram_nvram Tekram_nvram;
|
| 1074 |
|
|
typedef struct Tekram_target Tekram_target;
|
| 1075 |
|
|
|
| 1076 |
|
|
#endif /* SCSI_NCR_NVRAM_SUPPORT */
|
| 1077 |
|
|
|
| 1078 |
|
|
/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
|
| 1079 |
|
|
|
| 1080 |
|
|
/*-----------------------------------------------------------------
|
| 1081 |
|
|
**
|
| 1082 |
|
|
** The ncr 53c810 register structure.
|
| 1083 |
|
|
**
|
| 1084 |
|
|
**-----------------------------------------------------------------
|
| 1085 |
|
|
*/
|
| 1086 |
|
|
|
| 1087 |
|
|
struct ncr_reg {
|
| 1088 |
|
|
/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
|
| 1089 |
|
|
|
| 1090 |
|
|
/*01*/ u_char nc_scntl1; /* no reset */
|
| 1091 |
|
|
#define ISCON 0x10 /* connected to scsi */
|
| 1092 |
|
|
#define CRST 0x08 /* force reset */
|
| 1093 |
|
|
#define IARB 0x02 /* immediate arbitration */
|
| 1094 |
|
|
|
| 1095 |
|
|
/*02*/ u_char nc_scntl2; /* no disconnect expected */
|
| 1096 |
|
|
#define SDU 0x80 /* cmd: disconnect will raise error */
|
| 1097 |
|
|
#define CHM 0x40 /* sta: chained mode */
|
| 1098 |
|
|
#define WSS 0x08 /* sta: wide scsi send [W]*/
|
| 1099 |
|
|
#define WSR 0x01 /* sta: wide scsi received [W]*/
|
| 1100 |
|
|
|
| 1101 |
|
|
/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
|
| 1102 |
|
|
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
|
| 1103 |
|
|
#define ULTRA 0x80 /* cmd: ULTRA enable */
|
| 1104 |
|
|
/* bits 0-2, 7 rsvd for C1010 */
|
| 1105 |
|
|
|
| 1106 |
|
|
/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
|
| 1107 |
|
|
#define RRE 0x40 /* r/w:e enable response to resel. */
|
| 1108 |
|
|
#define SRE 0x20 /* r/w:e enable response to select */
|
| 1109 |
|
|
|
| 1110 |
|
|
/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
|
| 1111 |
|
|
/* bits 6-7 rsvd for C1010 */
|
| 1112 |
|
|
|
| 1113 |
|
|
/*06*/ u_char nc_sdid; /* ### Destination-ID */
|
| 1114 |
|
|
|
| 1115 |
|
|
/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
|
| 1116 |
|
|
|
| 1117 |
|
|
/*08*/ u_char nc_sfbr; /* ### First byte in phase */
|
| 1118 |
|
|
|
| 1119 |
|
|
/*09*/ u_char nc_socl;
|
| 1120 |
|
|
#define CREQ 0x80 /* r/w: SCSI-REQ */
|
| 1121 |
|
|
#define CACK 0x40 /* r/w: SCSI-ACK */
|
| 1122 |
|
|
#define CBSY 0x20 /* r/w: SCSI-BSY */
|
| 1123 |
|
|
#define CSEL 0x10 /* r/w: SCSI-SEL */
|
| 1124 |
|
|
#define CATN 0x08 /* r/w: SCSI-ATN */
|
| 1125 |
|
|
#define CMSG 0x04 /* r/w: SCSI-MSG */
|
| 1126 |
|
|
#define CC_D 0x02 /* r/w: SCSI-C_D */
|
| 1127 |
|
|
#define CI_O 0x01 /* r/w: SCSI-I_O */
|
| 1128 |
|
|
|
| 1129 |
|
|
/*0a*/ u_char nc_ssid;
|
| 1130 |
|
|
|
| 1131 |
|
|
/*0b*/ u_char nc_sbcl;
|
| 1132 |
|
|
|
| 1133 |
|
|
/*0c*/ u_char nc_dstat;
|
| 1134 |
|
|
#define DFE 0x80 /* sta: dma fifo empty */
|
| 1135 |
|
|
#define MDPE 0x40 /* int: master data parity error */
|
| 1136 |
|
|
#define BF 0x20 /* int: script: bus fault */
|
| 1137 |
|
|
#define ABRT 0x10 /* int: script: command aborted */
|
| 1138 |
|
|
#define SSI 0x08 /* int: script: single step */
|
| 1139 |
|
|
#define SIR 0x04 /* int: script: interrupt instruct. */
|
| 1140 |
|
|
#define IID 0x01 /* int: script: illegal instruct. */
|
| 1141 |
|
|
|
| 1142 |
|
|
/*0d*/ u_char nc_sstat0;
|
| 1143 |
|
|
#define ILF 0x80 /* sta: data in SIDL register lsb */
|
| 1144 |
|
|
#define ORF 0x40 /* sta: data in SODR register lsb */
|
| 1145 |
|
|
#define OLF 0x20 /* sta: data in SODL register lsb */
|
| 1146 |
|
|
#define AIP 0x10 /* sta: arbitration in progress */
|
| 1147 |
|
|
#define LOA 0x08 /* sta: arbitration lost */
|
| 1148 |
|
|
#define WOA 0x04 /* sta: arbitration won */
|
| 1149 |
|
|
#define IRST 0x02 /* sta: scsi reset signal */
|
| 1150 |
|
|
#define SDP 0x01 /* sta: scsi parity signal */
|
| 1151 |
|
|
|
| 1152 |
|
|
/*0e*/ u_char nc_sstat1;
|
| 1153 |
|
|
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
|
| 1154 |
|
|
|
| 1155 |
|
|
/*0f*/ u_char nc_sstat2;
|
| 1156 |
|
|
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
|
| 1157 |
|
|
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
|
| 1158 |
|
|
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
|
| 1159 |
|
|
#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
|
| 1160 |
|
|
#define LDSC 0x02 /* sta: disconnect & reconnect */
|
| 1161 |
|
|
|
| 1162 |
|
|
/*10*/ u_char nc_dsa; /* --> Base page */
|
| 1163 |
|
|
/*11*/ u_char nc_dsa1;
|
| 1164 |
|
|
/*12*/ u_char nc_dsa2;
|
| 1165 |
|
|
/*13*/ u_char nc_dsa3;
|
| 1166 |
|
|
|
| 1167 |
|
|
/*14*/ u_char nc_istat; /* --> Main Command and status */
|
| 1168 |
|
|
#define CABRT 0x80 /* cmd: abort current operation */
|
| 1169 |
|
|
#define SRST 0x40 /* mod: reset chip */
|
| 1170 |
|
|
#define SIGP 0x20 /* r/w: message from host to ncr */
|
| 1171 |
|
|
#define SEM 0x10 /* r/w: message between host + ncr */
|
| 1172 |
|
|
#define CON 0x08 /* sta: connected to scsi */
|
| 1173 |
|
|
#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
|
| 1174 |
|
|
#define SIP 0x02 /* sta: scsi-interrupt */
|
| 1175 |
|
|
#define DIP 0x01 /* sta: host/script interrupt */
|
| 1176 |
|
|
|
| 1177 |
|
|
/*15*/ u_char nc_istat1; /* 896 and later cores only */
|
| 1178 |
|
|
#define FLSH 0x04 /* sta: chip is flushing */
|
| 1179 |
|
|
#define SRUN 0x02 /* sta: scripts are running */
|
| 1180 |
|
|
#define SIRQD 0x01 /* r/w: disable INT pin */
|
| 1181 |
|
|
|
| 1182 |
|
|
/*16*/ u_char nc_mbox0; /* 896 and later cores only */
|
| 1183 |
|
|
/*17*/ u_char nc_mbox1; /* 896 and later cores only */
|
| 1184 |
|
|
|
| 1185 |
|
|
/*18*/ u_char nc_ctest0;
|
| 1186 |
|
|
/*19*/ u_char nc_ctest1;
|
| 1187 |
|
|
|
| 1188 |
|
|
/*1a*/ u_char nc_ctest2;
|
| 1189 |
|
|
#define CSIGP 0x40
|
| 1190 |
|
|
/* bits 0-2,7 rsvd for C1010 */
|
| 1191 |
|
|
|
| 1192 |
|
|
/*1b*/ u_char nc_ctest3;
|
| 1193 |
|
|
#define FLF 0x08 /* cmd: flush dma fifo */
|
| 1194 |
|
|
#define CLF 0x04 /* cmd: clear dma fifo */
|
| 1195 |
|
|
#define FM 0x02 /* mod: fetch pin mode */
|
| 1196 |
|
|
#define WRIE 0x01 /* mod: write and invalidate enable */
|
| 1197 |
|
|
/* bits 4-7 rsvd for C1010 */
|
| 1198 |
|
|
|
| 1199 |
|
|
/*1c*/ u_int32 nc_temp; /* ### Temporary stack */
|
| 1200 |
|
|
|
| 1201 |
|
|
/*20*/ u_char nc_dfifo;
|
| 1202 |
|
|
/*21*/ u_char nc_ctest4;
|
| 1203 |
|
|
#define BDIS 0x80 /* mod: burst disable */
|
| 1204 |
|
|
#define MPEE 0x08 /* mod: master parity error enable */
|
| 1205 |
|
|
|
| 1206 |
|
|
/*22*/ u_char nc_ctest5;
|
| 1207 |
|
|
#define DFS 0x20 /* mod: dma fifo size */
|
| 1208 |
|
|
/* bits 0-1, 3-7 rsvd for C1010 */
|
| 1209 |
|
|
/*23*/ u_char nc_ctest6;
|
| 1210 |
|
|
|
| 1211 |
|
|
/*24*/ u_int32 nc_dbc; /* ### Byte count and command */
|
| 1212 |
|
|
/*28*/ u_int32 nc_dnad; /* ### Next command register */
|
| 1213 |
|
|
/*2c*/ u_int32 nc_dsp; /* --> Script Pointer */
|
| 1214 |
|
|
/*30*/ u_int32 nc_dsps; /* --> Script pointer save/opcode#2 */
|
| 1215 |
|
|
|
| 1216 |
|
|
/*34*/ u_char nc_scratcha; /* Temporary register a */
|
| 1217 |
|
|
/*35*/ u_char nc_scratcha1;
|
| 1218 |
|
|
/*36*/ u_char nc_scratcha2;
|
| 1219 |
|
|
/*37*/ u_char nc_scratcha3;
|
| 1220 |
|
|
|
| 1221 |
|
|
/*38*/ u_char nc_dmode;
|
| 1222 |
|
|
#define BL_2 0x80 /* mod: burst length shift value +2 */
|
| 1223 |
|
|
#define BL_1 0x40 /* mod: burst length shift value +1 */
|
| 1224 |
|
|
#define ERL 0x08 /* mod: enable read line */
|
| 1225 |
|
|
#define ERMP 0x04 /* mod: enable read multiple */
|
| 1226 |
|
|
#define BOF 0x02 /* mod: burst op code fetch */
|
| 1227 |
|
|
|
| 1228 |
|
|
/*39*/ u_char nc_dien;
|
| 1229 |
|
|
/*3a*/ u_char nc_sbr;
|
| 1230 |
|
|
|
| 1231 |
|
|
/*3b*/ u_char nc_dcntl; /* --> Script execution control */
|
| 1232 |
|
|
#define CLSE 0x80 /* mod: cache line size enable */
|
| 1233 |
|
|
#define PFF 0x40 /* cmd: pre-fetch flush */
|
| 1234 |
|
|
#define PFEN 0x20 /* mod: pre-fetch enable */
|
| 1235 |
|
|
#define SSM 0x10 /* mod: single step mode */
|
| 1236 |
|
|
#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
|
| 1237 |
|
|
#define STD 0x04 /* cmd: start dma mode */
|
| 1238 |
|
|
#define IRQD 0x02 /* mod: irq disable */
|
| 1239 |
|
|
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
|
| 1240 |
|
|
/* bits 0-1 rsvd for C1010 */
|
| 1241 |
|
|
|
| 1242 |
|
|
/*3c*/ u_int32 nc_adder;
|
| 1243 |
|
|
|
| 1244 |
|
|
/*40*/ u_short nc_sien; /* -->: interrupt enable */
|
| 1245 |
|
|
/*42*/ u_short nc_sist; /* <--: interrupt status */
|
| 1246 |
|
|
#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
|
| 1247 |
|
|
#define STO 0x0400/* sta: timeout (select) */
|
| 1248 |
|
|
#define GEN 0x0200/* sta: timeout (general) */
|
| 1249 |
|
|
#define HTH 0x0100/* sta: timeout (handshake) */
|
| 1250 |
|
|
#define MA 0x80 /* sta: phase mismatch */
|
| 1251 |
|
|
#define CMP 0x40 /* sta: arbitration complete */
|
| 1252 |
|
|
#define SEL 0x20 /* sta: selected by another device */
|
| 1253 |
|
|
#define RSL 0x10 /* sta: reselected by another device*/
|
| 1254 |
|
|
#define SGE 0x08 /* sta: gross error (over/underflow)*/
|
| 1255 |
|
|
#define UDC 0x04 /* sta: unexpected disconnect */
|
| 1256 |
|
|
#define RST 0x02 /* sta: scsi bus reset detected */
|
| 1257 |
|
|
#define PAR 0x01 /* sta: scsi parity error */
|
| 1258 |
|
|
|
| 1259 |
|
|
/*44*/ u_char nc_slpar;
|
| 1260 |
|
|
/*45*/ u_char nc_swide;
|
| 1261 |
|
|
/*46*/ u_char nc_macntl;
|
| 1262 |
|
|
/*47*/ u_char nc_gpcntl;
|
| 1263 |
|
|
/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
|
| 1264 |
|
|
/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
|
| 1265 |
|
|
/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
|
| 1266 |
|
|
|
| 1267 |
|
|
/*4c*/ u_char nc_stest0;
|
| 1268 |
|
|
|
| 1269 |
|
|
/*4d*/ u_char nc_stest1;
|
| 1270 |
|
|
#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
|
| 1271 |
|
|
#define DBLEN 0x08 /* clock doubler running */
|
| 1272 |
|
|
#define DBLSEL 0x04 /* clock doubler selected */
|
| 1273 |
|
|
|
| 1274 |
|
|
|
| 1275 |
|
|
/*4e*/ u_char nc_stest2;
|
| 1276 |
|
|
#define ROF 0x40 /* reset scsi offset (after gross error!) */
|
| 1277 |
|
|
#define EXT 0x02 /* extended filtering */
|
| 1278 |
|
|
|
| 1279 |
|
|
/*4f*/ u_char nc_stest3;
|
| 1280 |
|
|
#define TE 0x80 /* c: tolerAnt enable */
|
| 1281 |
|
|
#define HSC 0x20 /* c: Halt SCSI Clock */
|
| 1282 |
|
|
#define CSF 0x02 /* c: clear scsi fifo */
|
| 1283 |
|
|
|
| 1284 |
|
|
/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
|
| 1285 |
|
|
/*52*/ u_char nc_stest4;
|
| 1286 |
|
|
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
|
| 1287 |
|
|
#define SMODE_HVD 0x40 /* High Voltage Differential */
|
| 1288 |
|
|
#define SMODE_SE 0x80 /* Single Ended */
|
| 1289 |
|
|
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
|
| 1290 |
|
|
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
|
| 1291 |
|
|
/* bits 0-5 rsvd for C1010 */
|
| 1292 |
|
|
|
| 1293 |
|
|
/*53*/ u_char nc_53_;
|
| 1294 |
|
|
/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
|
| 1295 |
|
|
/*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
|
| 1296 |
|
|
#define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
|
| 1297 |
|
|
#define PMJCTL 0x40 /* Phase Mismatch Jump Control */
|
| 1298 |
|
|
#define ENNDJ 0x20 /* Enable Non Data PM Jump */
|
| 1299 |
|
|
#define DISFC 0x10 /* Disable Auto FIFO Clear */
|
| 1300 |
|
|
#define DILS 0x02 /* Disable Internal Load/Store */
|
| 1301 |
|
|
#define DPR 0x01 /* Disable Pipe Req */
|
| 1302 |
|
|
|
| 1303 |
|
|
/*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
|
| 1304 |
|
|
#define ZMOD 0x80 /* High Impedance Mode */
|
| 1305 |
|
|
#define DIC 0x10 /* Disable Internal Cycles */
|
| 1306 |
|
|
#define DDAC 0x08 /* Disable Dual Address Cycle */
|
| 1307 |
|
|
#define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
|
| 1308 |
|
|
#define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
|
| 1309 |
|
|
#define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
|
| 1310 |
|
|
|
| 1311 |
|
|
/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
|
| 1312 |
|
|
/*5a*/ u_short nc_5a_;
|
| 1313 |
|
|
|
| 1314 |
|
|
/*5c*/ u_char nc_scr0; /* Working register B */
|
| 1315 |
|
|
/*5d*/ u_char nc_scr1; /* */
|
| 1316 |
|
|
/*5e*/ u_char nc_scr2; /* */
|
| 1317 |
|
|
/*5f*/ u_char nc_scr3; /* */
|
| 1318 |
|
|
|
| 1319 |
|
|
/*60*/ u_char nc_scrx[64]; /* Working register C-R */
|
| 1320 |
|
|
/*a0*/ u_int32 nc_mmrs; /* Memory Move Read Selector */
|
| 1321 |
|
|
/*a4*/ u_int32 nc_mmws; /* Memory Move Write Selector */
|
| 1322 |
|
|
/*a8*/ u_int32 nc_sfs; /* Script Fetch Selector */
|
| 1323 |
|
|
/*ac*/ u_int32 nc_drs; /* DSA Relative Selector */
|
| 1324 |
|
|
/*b0*/ u_int32 nc_sbms; /* Static Block Move Selector */
|
| 1325 |
|
|
/*b4*/ u_int32 nc_dbms; /* Dynamic Block Move Selector */
|
| 1326 |
|
|
/*b8*/ u_int32 nc_dnad64; /* DMA Next Address 64 */
|
| 1327 |
|
|
/*bc*/ u_short nc_scntl4; /* C1010 only */
|
| 1328 |
|
|
#define U3EN 0x80 /* Enable Ultra 3 */
|
| 1329 |
|
|
#define AIPEN 0x40 /* Allow check upper byte lanes */
|
| 1330 |
|
|
#define XCLKH_DT 0x08 /* Extra clock of data hold on DT
|
| 1331 |
|
|
transfer edge */
|
| 1332 |
|
|
#define XCLKH_ST 0x04 /* Extra clock of data hold on ST
|
| 1333 |
|
|
transfer edge */
|
| 1334 |
|
|
|
| 1335 |
|
|
/*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */
|
| 1336 |
|
|
/*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */
|
| 1337 |
|
|
|
| 1338 |
|
|
/*c0*/ u_int32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
|
| 1339 |
|
|
/*c4*/ u_int32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
|
| 1340 |
|
|
/*c8*/ u_char nc_rbc; /* Remaining Byte Count */
|
| 1341 |
|
|
/*c9*/ u_char nc_rbc1; /* */
|
| 1342 |
|
|
/*ca*/ u_char nc_rbc2; /* */
|
| 1343 |
|
|
/*cb*/ u_char nc_rbc3; /* */
|
| 1344 |
|
|
|
| 1345 |
|
|
/*cc*/ u_char nc_ua; /* Updated Address */
|
| 1346 |
|
|
/*cd*/ u_char nc_ua1; /* */
|
| 1347 |
|
|
/*ce*/ u_char nc_ua2; /* */
|
| 1348 |
|
|
/*cf*/ u_char nc_ua3; /* */
|
| 1349 |
|
|
/*d0*/ u_int32 nc_esa; /* Entry Storage Address */
|
| 1350 |
|
|
/*d4*/ u_char nc_ia; /* Instruction Address */
|
| 1351 |
|
|
/*d5*/ u_char nc_ia1;
|
| 1352 |
|
|
/*d6*/ u_char nc_ia2;
|
| 1353 |
|
|
/*d7*/ u_char nc_ia3;
|
| 1354 |
|
|
/*d8*/ u_int32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
|
| 1355 |
|
|
/*dc*/ u_int32 nc_csbc; /* Cumulative SCSI Byte Count */
|
| 1356 |
|
|
|
| 1357 |
|
|
/* Following for C1010 only */
|
| 1358 |
|
|
/*e0*/ u_short nc_crcpad; /* CRC Value */
|
| 1359 |
|
|
/*e2*/ u_char nc_crccntl0; /* CRC control register */
|
| 1360 |
|
|
#define SNDCRC 0x10 /* Send CRC Request */
|
| 1361 |
|
|
/*e3*/ u_char nc_crccntl1; /* CRC control register */
|
| 1362 |
|
|
/*e4*/ u_int32 nc_crcdata; /* CRC data register */
|
| 1363 |
|
|
/*e8*/ u_int32 nc_e8_; /* rsvd */
|
| 1364 |
|
|
/*ec*/ u_int32 nc_ec_; /* rsvd */
|
| 1365 |
|
|
/*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */
|
| 1366 |
|
|
|
| 1367 |
|
|
};
|
| 1368 |
|
|
|
| 1369 |
|
|
/*-----------------------------------------------------------
|
| 1370 |
|
|
**
|
| 1371 |
|
|
** Utility macros for the script.
|
| 1372 |
|
|
**
|
| 1373 |
|
|
**-----------------------------------------------------------
|
| 1374 |
|
|
*/
|
| 1375 |
|
|
|
| 1376 |
|
|
#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
|
| 1377 |
|
|
#define REG(r) REGJ (nc_, r)
|
| 1378 |
|
|
|
| 1379 |
|
|
typedef u_int32 ncrcmd;
|
| 1380 |
|
|
|
| 1381 |
|
|
/*-----------------------------------------------------------
|
| 1382 |
|
|
**
|
| 1383 |
|
|
** SCSI phases
|
| 1384 |
|
|
**
|
| 1385 |
|
|
** DT phases illegal for ncr driver.
|
| 1386 |
|
|
**
|
| 1387 |
|
|
**-----------------------------------------------------------
|
| 1388 |
|
|
*/
|
| 1389 |
|
|
|
| 1390 |
|
|
#define SCR_DATA_OUT 0x00000000
|
| 1391 |
|
|
#define SCR_DATA_IN 0x01000000
|
| 1392 |
|
|
#define SCR_COMMAND 0x02000000
|
| 1393 |
|
|
#define SCR_STATUS 0x03000000
|
| 1394 |
|
|
#define SCR_DT_DATA_OUT 0x04000000
|
| 1395 |
|
|
#define SCR_DT_DATA_IN 0x05000000
|
| 1396 |
|
|
#define SCR_MSG_OUT 0x06000000
|
| 1397 |
|
|
#define SCR_MSG_IN 0x07000000
|
| 1398 |
|
|
|
| 1399 |
|
|
#define SCR_ILG_OUT 0x04000000
|
| 1400 |
|
|
#define SCR_ILG_IN 0x05000000
|
| 1401 |
|
|
|
| 1402 |
|
|
/*-----------------------------------------------------------
|
| 1403 |
|
|
**
|
| 1404 |
|
|
** Data transfer via SCSI.
|
| 1405 |
|
|
**
|
| 1406 |
|
|
**-----------------------------------------------------------
|
| 1407 |
|
|
**
|
| 1408 |
|
|
** MOVE_ABS (LEN)
|
| 1409 |
|
|
** <<start address>>
|
| 1410 |
|
|
**
|
| 1411 |
|
|
** MOVE_IND (LEN)
|
| 1412 |
|
|
** <<dnad_offset>>
|
| 1413 |
|
|
**
|
| 1414 |
|
|
** MOVE_TBL
|
| 1415 |
|
|
** <<dnad_offset>>
|
| 1416 |
|
|
**
|
| 1417 |
|
|
**-----------------------------------------------------------
|
| 1418 |
|
|
*/
|
| 1419 |
|
|
|
| 1420 |
|
|
#define OPC_MOVE 0x08000000
|
| 1421 |
|
|
|
| 1422 |
|
|
#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
|
| 1423 |
|
|
#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
|
| 1424 |
|
|
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
|
| 1425 |
|
|
|
| 1426 |
|
|
#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
|
| 1427 |
|
|
#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
|
| 1428 |
|
|
#define SCR_CHMOV_TBL (0x10000000)
|
| 1429 |
|
|
|
| 1430 |
|
|
struct scr_tblmove {
|
| 1431 |
|
|
u_int32 size;
|
| 1432 |
|
|
u_int32 addr;
|
| 1433 |
|
|
};
|
| 1434 |
|
|
|
| 1435 |
|
|
/*-----------------------------------------------------------
|
| 1436 |
|
|
**
|
| 1437 |
|
|
** Selection
|
| 1438 |
|
|
**
|
| 1439 |
|
|
**-----------------------------------------------------------
|
| 1440 |
|
|
**
|
| 1441 |
|
|
** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
|
| 1442 |
|
|
** <<alternate_address>>
|
| 1443 |
|
|
**
|
| 1444 |
|
|
** SEL_TBL | << dnad_offset>> [ | REL_JMP]
|
| 1445 |
|
|
** <<alternate_address>>
|
| 1446 |
|
|
**
|
| 1447 |
|
|
**-----------------------------------------------------------
|
| 1448 |
|
|
*/
|
| 1449 |
|
|
|
| 1450 |
|
|
#define SCR_SEL_ABS 0x40000000
|
| 1451 |
|
|
#define SCR_SEL_ABS_ATN 0x41000000
|
| 1452 |
|
|
#define SCR_SEL_TBL 0x42000000
|
| 1453 |
|
|
#define SCR_SEL_TBL_ATN 0x43000000
|
| 1454 |
|
|
|
| 1455 |
|
|
struct scr_tblsel {
|
| 1456 |
|
|
u_char sel_scntl4;
|
| 1457 |
|
|
u_char sel_sxfer;
|
| 1458 |
|
|
u_char sel_id;
|
| 1459 |
|
|
u_char sel_scntl3;
|
| 1460 |
|
|
};
|
| 1461 |
|
|
|
| 1462 |
|
|
#define SCR_JMP_REL 0x04000000
|
| 1463 |
|
|
#define SCR_ID(id) (((u_int32)(id)) << 16)
|
| 1464 |
|
|
|
| 1465 |
|
|
/*-----------------------------------------------------------
|
| 1466 |
|
|
**
|
| 1467 |
|
|
** Waiting for Disconnect or Reselect
|
| 1468 |
|
|
**
|
| 1469 |
|
|
**-----------------------------------------------------------
|
| 1470 |
|
|
**
|
| 1471 |
|
|
** WAIT_DISC
|
| 1472 |
|
|
** dummy: <<alternate_address>>
|
| 1473 |
|
|
**
|
| 1474 |
|
|
** WAIT_RESEL
|
| 1475 |
|
|
** <<alternate_address>>
|
| 1476 |
|
|
**
|
| 1477 |
|
|
**-----------------------------------------------------------
|
| 1478 |
|
|
*/
|
| 1479 |
|
|
|
| 1480 |
|
|
#define SCR_WAIT_DISC 0x48000000
|
| 1481 |
|
|
#define SCR_WAIT_RESEL 0x50000000
|
| 1482 |
|
|
|
| 1483 |
|
|
/*-----------------------------------------------------------
|
| 1484 |
|
|
**
|
| 1485 |
|
|
** Bit Set / Reset
|
| 1486 |
|
|
**
|
| 1487 |
|
|
**-----------------------------------------------------------
|
| 1488 |
|
|
**
|
| 1489 |
|
|
** SET (flags {|.. })
|
| 1490 |
|
|
**
|
| 1491 |
|
|
** CLR (flags {|.. })
|
| 1492 |
|
|
**
|
| 1493 |
|
|
**-----------------------------------------------------------
|
| 1494 |
|
|
*/
|
| 1495 |
|
|
|
| 1496 |
|
|
#define SCR_SET(f) (0x58000000 | (f))
|
| 1497 |
|
|
#define SCR_CLR(f) (0x60000000 | (f))
|
| 1498 |
|
|
|
| 1499 |
|
|
#define SCR_CARRY 0x00000400
|
| 1500 |
|
|
#define SCR_TRG 0x00000200
|
| 1501 |
|
|
#define SCR_ACK 0x00000040
|
| 1502 |
|
|
#define SCR_ATN 0x00000008
|
| 1503 |
|
|
|
| 1504 |
|
|
|
| 1505 |
|
|
|
| 1506 |
|
|
|
| 1507 |
|
|
/*-----------------------------------------------------------
|
| 1508 |
|
|
**
|
| 1509 |
|
|
** Memory to memory move
|
| 1510 |
|
|
**
|
| 1511 |
|
|
**-----------------------------------------------------------
|
| 1512 |
|
|
**
|
| 1513 |
|
|
** COPY (bytecount)
|
| 1514 |
|
|
** << source_address >>
|
| 1515 |
|
|
** << destination_address >>
|
| 1516 |
|
|
**
|
| 1517 |
|
|
** SCR_COPY sets the NO FLUSH option by default.
|
| 1518 |
|
|
** SCR_COPY_F does not set this option.
|
| 1519 |
|
|
**
|
| 1520 |
|
|
** For chips which do not support this option,
|
| 1521 |
|
|
** ncr_copy_and_bind() will remove this bit.
|
| 1522 |
|
|
**-----------------------------------------------------------
|
| 1523 |
|
|
*/
|
| 1524 |
|
|
|
| 1525 |
|
|
#define SCR_NO_FLUSH 0x01000000
|
| 1526 |
|
|
|
| 1527 |
|
|
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
|
| 1528 |
|
|
#define SCR_COPY_F(n) (0xc0000000 | (n))
|
| 1529 |
|
|
|
| 1530 |
|
|
/*-----------------------------------------------------------
|
| 1531 |
|
|
**
|
| 1532 |
|
|
** Register move and binary operations
|
| 1533 |
|
|
**
|
| 1534 |
|
|
**-----------------------------------------------------------
|
| 1535 |
|
|
**
|
| 1536 |
|
|
** SFBR_REG (reg, op, data) reg = SFBR op data
|
| 1537 |
|
|
** << 0 >>
|
| 1538 |
|
|
**
|
| 1539 |
|
|
** REG_SFBR (reg, op, data) SFBR = reg op data
|
| 1540 |
|
|
** << 0 >>
|
| 1541 |
|
|
**
|
| 1542 |
|
|
** REG_REG (reg, op, data) reg = reg op data
|
| 1543 |
|
|
** << 0 >>
|
| 1544 |
|
|
**
|
| 1545 |
|
|
**-----------------------------------------------------------
|
| 1546 |
|
|
** On 810A, 860, 825A, 875, 895 and 896 chips the content
|
| 1547 |
|
|
** of SFBR register can be used as data (SCR_SFBR_DATA).
|
| 1548 |
|
|
** The 896 has additionnal IO registers starting at
|
| 1549 |
|
|
** offset 0x80. Bit 7 of register offset is stored in
|
| 1550 |
|
|
** bit 7 of the SCRIPTS instruction first DWORD.
|
| 1551 |
|
|
**-----------------------------------------------------------
|
| 1552 |
|
|
*/
|
| 1553 |
|
|
|
| 1554 |
|
|
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
|
| 1555 |
|
|
|
| 1556 |
|
|
#define SCR_SFBR_REG(reg,op,data) \
|
| 1557 |
|
|
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
| 1558 |
|
|
|
| 1559 |
|
|
#define SCR_REG_SFBR(reg,op,data) \
|
| 1560 |
|
|
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
| 1561 |
|
|
|
| 1562 |
|
|
#define SCR_REG_REG(reg,op,data) \
|
| 1563 |
|
|
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
| 1564 |
|
|
|
| 1565 |
|
|
|
| 1566 |
|
|
#define SCR_LOAD 0x00000000
|
| 1567 |
|
|
#define SCR_SHL 0x01000000
|
| 1568 |
|
|
#define SCR_OR 0x02000000
|
| 1569 |
|
|
#define SCR_XOR 0x03000000
|
| 1570 |
|
|
#define SCR_AND 0x04000000
|
| 1571 |
|
|
#define SCR_SHR 0x05000000
|
| 1572 |
|
|
#define SCR_ADD 0x06000000
|
| 1573 |
|
|
#define SCR_ADDC 0x07000000
|
| 1574 |
|
|
|
| 1575 |
|
|
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
|
| 1576 |
|
|
|
| 1577 |
|
|
/*-----------------------------------------------------------
|
| 1578 |
|
|
**
|
| 1579 |
|
|
** FROM_REG (reg) SFBR = reg
|
| 1580 |
|
|
** << 0 >>
|
| 1581 |
|
|
**
|
| 1582 |
|
|
** TO_REG (reg) reg = SFBR
|
| 1583 |
|
|
** << 0 >>
|
| 1584 |
|
|
**
|
| 1585 |
|
|
** LOAD_REG (reg, data) reg = <data>
|
| 1586 |
|
|
** << 0 >>
|
| 1587 |
|
|
**
|
| 1588 |
|
|
** LOAD_SFBR(data) SFBR = <data>
|
| 1589 |
|
|
** << 0 >>
|
| 1590 |
|
|
**
|
| 1591 |
|
|
**-----------------------------------------------------------
|
| 1592 |
|
|
*/
|
| 1593 |
|
|
|
| 1594 |
|
|
#define SCR_FROM_REG(reg) \
|
| 1595 |
|
|
SCR_REG_SFBR(reg,SCR_OR,0)
|
| 1596 |
|
|
|
| 1597 |
|
|
#define SCR_TO_REG(reg) \
|
| 1598 |
|
|
SCR_SFBR_REG(reg,SCR_OR,0)
|
| 1599 |
|
|
|
| 1600 |
|
|
#define SCR_LOAD_REG(reg,data) \
|
| 1601 |
|
|
SCR_REG_REG(reg,SCR_LOAD,data)
|
| 1602 |
|
|
|
| 1603 |
|
|
#define SCR_LOAD_SFBR(data) \
|
| 1604 |
|
|
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
|
| 1605 |
|
|
|
| 1606 |
|
|
/*-----------------------------------------------------------
|
| 1607 |
|
|
**
|
| 1608 |
|
|
** LOAD from memory to register.
|
| 1609 |
|
|
** STORE from register to memory.
|
| 1610 |
|
|
**
|
| 1611 |
|
|
** Only supported by 810A, 860, 825A, 875, 895 and 896.
|
| 1612 |
|
|
**
|
| 1613 |
|
|
**-----------------------------------------------------------
|
| 1614 |
|
|
**
|
| 1615 |
|
|
** LOAD_ABS (LEN)
|
| 1616 |
|
|
** <<start address>>
|
| 1617 |
|
|
**
|
| 1618 |
|
|
** LOAD_REL (LEN) (DSA relative)
|
| 1619 |
|
|
** <<dsa_offset>>
|
| 1620 |
|
|
**
|
| 1621 |
|
|
**-----------------------------------------------------------
|
| 1622 |
|
|
*/
|
| 1623 |
|
|
|
| 1624 |
|
|
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
|
| 1625 |
|
|
#define SCR_NO_FLUSH2 0x02000000
|
| 1626 |
|
|
#define SCR_DSA_REL2 0x10000000
|
| 1627 |
|
|
|
| 1628 |
|
|
#define SCR_LOAD_R(reg, how, n) \
|
| 1629 |
|
|
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
| 1630 |
|
|
|
| 1631 |
|
|
#define SCR_STORE_R(reg, how, n) \
|
| 1632 |
|
|
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
| 1633 |
|
|
|
| 1634 |
|
|
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
|
| 1635 |
|
|
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
|
| 1636 |
|
|
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
|
| 1637 |
|
|
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
|
| 1638 |
|
|
|
| 1639 |
|
|
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
|
| 1640 |
|
|
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
|
| 1641 |
|
|
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
|
| 1642 |
|
|
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
|
| 1643 |
|
|
|
| 1644 |
|
|
|
| 1645 |
|
|
/*-----------------------------------------------------------
|
| 1646 |
|
|
**
|
| 1647 |
|
|
** Waiting for Disconnect or Reselect
|
| 1648 |
|
|
**
|
| 1649 |
|
|
**-----------------------------------------------------------
|
| 1650 |
|
|
**
|
| 1651 |
|
|
** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1652 |
|
|
** <<address>>
|
| 1653 |
|
|
**
|
| 1654 |
|
|
** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1655 |
|
|
** <<distance>>
|
| 1656 |
|
|
**
|
| 1657 |
|
|
** CALL [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1658 |
|
|
** <<address>>
|
| 1659 |
|
|
**
|
| 1660 |
|
|
** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1661 |
|
|
** <<distance>>
|
| 1662 |
|
|
**
|
| 1663 |
|
|
** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1664 |
|
|
** <<dummy>>
|
| 1665 |
|
|
**
|
| 1666 |
|
|
** INT [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1667 |
|
|
** <<ident>>
|
| 1668 |
|
|
**
|
| 1669 |
|
|
** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
|
| 1670 |
|
|
** <<ident>>
|
| 1671 |
|
|
**
|
| 1672 |
|
|
** Conditions:
|
| 1673 |
|
|
** WHEN (phase)
|
| 1674 |
|
|
** IF (phase)
|
| 1675 |
|
|
** CARRYSET
|
| 1676 |
|
|
** DATA (data, mask)
|
| 1677 |
|
|
**
|
| 1678 |
|
|
**-----------------------------------------------------------
|
| 1679 |
|
|
*/
|
| 1680 |
|
|
|
| 1681 |
|
|
#define SCR_NO_OP 0x80000000
|
| 1682 |
|
|
#define SCR_JUMP 0x80080000
|
| 1683 |
|
|
#define SCR_JUMP64 0x80480000
|
| 1684 |
|
|
#define SCR_JUMPR 0x80880000
|
| 1685 |
|
|
#define SCR_CALL 0x88080000
|
| 1686 |
|
|
#define SCR_CALLR 0x88880000
|
| 1687 |
|
|
#define SCR_RETURN 0x90080000
|
| 1688 |
|
|
#define SCR_INT 0x98080000
|
| 1689 |
|
|
#define SCR_INT_FLY 0x98180000
|
| 1690 |
|
|
|
| 1691 |
|
|
#define IFFALSE(arg) (0x00080000 | (arg))
|
| 1692 |
|
|
#define IFTRUE(arg) (0x00000000 | (arg))
|
| 1693 |
|
|
|
| 1694 |
|
|
#define WHEN(phase) (0x00030000 | (phase))
|
| 1695 |
|
|
#define IF(phase) (0x00020000 | (phase))
|
| 1696 |
|
|
|
| 1697 |
|
|
#define DATA(D) (0x00040000 | ((D) & 0xff))
|
| 1698 |
|
|
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
|
| 1699 |
|
|
|
| 1700 |
|
|
#define CARRYSET (0x00200000)
|
| 1701 |
|
|
|
| 1702 |
|
|
/*-----------------------------------------------------------
|
| 1703 |
|
|
**
|
| 1704 |
|
|
** SCSI constants.
|
| 1705 |
|
|
**
|
| 1706 |
|
|
**-----------------------------------------------------------
|
| 1707 |
|
|
*/
|
| 1708 |
|
|
|
| 1709 |
|
|
/*
|
| 1710 |
|
|
** Messages
|
| 1711 |
|
|
*/
|
| 1712 |
|
|
|
| 1713 |
|
|
#define M_COMPLETE (0x00)
|
| 1714 |
|
|
#define M_EXTENDED (0x01)
|
| 1715 |
|
|
#define M_SAVE_DP (0x02)
|
| 1716 |
|
|
#define M_RESTORE_DP (0x03)
|
| 1717 |
|
|
#define M_DISCONNECT (0x04)
|
| 1718 |
|
|
#define M_ID_ERROR (0x05)
|
| 1719 |
|
|
#define M_ABORT (0x06)
|
| 1720 |
|
|
#define M_REJECT (0x07)
|
| 1721 |
|
|
#define M_NOOP (0x08)
|
| 1722 |
|
|
#define M_PARITY (0x09)
|
| 1723 |
|
|
#define M_LCOMPLETE (0x0a)
|
| 1724 |
|
|
#define M_FCOMPLETE (0x0b)
|
| 1725 |
|
|
#define M_RESET (0x0c)
|
| 1726 |
|
|
#define M_ABORT_TAG (0x0d)
|
| 1727 |
|
|
#define M_CLEAR_QUEUE (0x0e)
|
| 1728 |
|
|
#define M_INIT_REC (0x0f)
|
| 1729 |
|
|
#define M_REL_REC (0x10)
|
| 1730 |
|
|
#define M_TERMINATE (0x11)
|
| 1731 |
|
|
#define M_SIMPLE_TAG (0x20)
|
| 1732 |
|
|
#define M_HEAD_TAG (0x21)
|
| 1733 |
|
|
#define M_ORDERED_TAG (0x22)
|
| 1734 |
|
|
#define M_IGN_RESIDUE (0x23)
|
| 1735 |
|
|
#define M_IDENTIFY (0x80)
|
| 1736 |
|
|
|
| 1737 |
|
|
#define M_X_MODIFY_DP (0x00)
|
| 1738 |
|
|
#define M_X_SYNC_REQ (0x01)
|
| 1739 |
|
|
#define M_X_WIDE_REQ (0x03)
|
| 1740 |
|
|
#define M_X_PPR_REQ (0x04)
|
| 1741 |
|
|
|
| 1742 |
|
|
/*
|
| 1743 |
|
|
** Status
|
| 1744 |
|
|
*/
|
| 1745 |
|
|
|
| 1746 |
|
|
#define S_GOOD (0x00)
|
| 1747 |
|
|
#define S_CHECK_COND (0x02)
|
| 1748 |
|
|
#define S_COND_MET (0x04)
|
| 1749 |
|
|
#define S_BUSY (0x08)
|
| 1750 |
|
|
#define S_INT (0x10)
|
| 1751 |
|
|
#define S_INT_COND_MET (0x14)
|
| 1752 |
|
|
#define S_CONFLICT (0x18)
|
| 1753 |
|
|
#define S_TERMINATED (0x20)
|
| 1754 |
|
|
#define S_QUEUE_FULL (0x28)
|
| 1755 |
|
|
#define S_ILLEGAL (0xff)
|
| 1756 |
|
|
#define S_SENSE (0x80)
|
| 1757 |
|
|
|
| 1758 |
|
|
/*
|
| 1759 |
|
|
* End of ncrreg from FreeBSD
|
| 1760 |
|
|
*/
|
| 1761 |
|
|
|
| 1762 |
|
|
#endif /* !defined HOSTS_C */
|
| 1763 |
|
|
|
| 1764 |
|
|
#endif /* defined SYM53C8XX_DEFS_H */
|
