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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [sound/] [hal2.c] - Blame information for rev 1765

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Line No. Rev Author Line
1 1275 phoenix
/*
2
 *  Driver for A2 audio system used in SGI machines
3
 *  Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
4
 *
5
 *  Based on Ulf Carlsson's code.
6
 *
7
 *  This program is free software; you can redistribute it and/or modify
8
 *  it under the terms of the GNU General Public License version 2 as
9
 *  published by the Free Software Foundation.
10
 *
11
 *  This program is distributed in the hope that it will be useful,
12
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
 *  GNU General Public License for more details.
15
 *
16
 *  You should have received a copy of the GNU General Public License
17
 *  along with this program; if not, write to the Free Software
18
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
 *
20
 *  Supported devices:
21
 *  /dev/dsp    standard dsp device, (mostly) OSS compatible
22
 *  /dev/mixer  standard mixer device, (mostly) OSS compatible
23
 *
24
 */
25
#include <linux/kernel.h>
26
#include <linux/module.h>
27
#include <linux/sched.h>
28
#include <linux/init.h>
29
#include <linux/slab.h>
30
#include <linux/poll.h>
31
#include <linux/pci.h>
32
#include <linux/sound.h>
33
#include <linux/soundcard.h>
34
 
35
#include <asm/io.h>
36
#include <asm/sgi/hpc3.h>
37
#include <asm/sgi/ip22.h>
38
 
39
#include "hal2.h"
40
 
41
#if 0
42
#define DEBUG(args...)          printk(args)
43
#else
44
#define DEBUG(args...)
45
#endif
46
 
47
#if 0 
48
#define DEBUG_MIX(args...)      printk(args)
49
#else
50
#define DEBUG_MIX(args...)
51
#endif
52
 
53
/*
54
 * Before touching these look how it works. It is a bit unusual I know,
55
 * but it helps to keep things simple. This driver is considered complete
56
 * and I won't add any new features although hardware has many cool
57
 * capabilities.
58
 * (Historical note: HAL2 driver was first written by Ulf Carlsson - ALSA
59
 * 0.3 running with 2.2.x kernel. Then ALSA changed completely and it
60
 * seemed easier to me to write OSS driver from scratch - this one. Now
61
 * when ALSA is official part of 2.6 kernel it's time to write ALSA driver
62
 * using (hopefully) final version of ALSA interface)
63
 */
64
#define H2_BLOCK_SIZE   1024
65
#define H2_ADC_BUFSIZE  8192
66
#define H2_DAC_BUFSIZE  16834
67
 
68
struct hal2_pbus {
69
        struct hpc3_pbus_dmacregs *pbus;
70
        int pbusnr;
71
        unsigned int ctrl;              /* Current state of pbus->pbdma_ctrl */
72
};
73
 
74
struct hal2_desc {
75
        struct hpc_dma_desc desc;
76
        u32 cnt;                        /* don't touch, it is also padding */
77
};
78
 
79
struct hal2_codec {
80
        unsigned char *buffer;
81
        struct hal2_desc *desc;
82
        int desc_count;
83
        int tail, head;                 /* tail index, head index */
84
        struct hal2_pbus pbus;
85
        unsigned int format;            /* Audio data format */
86
        int voices;                     /* mono/stereo */
87
        unsigned int sample_rate;
88
        unsigned int master;            /* Master frequency */
89
        unsigned short mod;             /* MOD value */
90
        unsigned short inc;             /* INC value */
91
 
92
        wait_queue_head_t dma_wait;
93
        spinlock_t lock;
94
        struct semaphore sem;
95
 
96
        int usecount;                   /* recording and playback are
97
                                         * independent */
98
};
99
 
100
#define H2_MIX_OUTPUT_ATT       0
101
#define H2_MIX_INPUT_GAIN       1
102
#define H2_MIXERS               2
103
struct hal2_mixer {
104
        int modcnt;
105
        unsigned int master;
106
        unsigned int volume[H2_MIXERS];
107
};
108
 
109
struct hal2_card {
110
        int dev_dsp;                    /* audio device */
111
        int dev_mixer;                  /* mixer device */
112
        int dev_midi;                   /* midi device */
113
 
114
        struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
115
        struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
116
        struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
117
        struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
118
 
119
        struct hal2_codec dac;
120
        struct hal2_codec adc;
121
        struct hal2_mixer mixer;
122
};
123
 
124
#define H2_INDIRECT_WAIT(regs)  while (regs->isr & H2_ISR_TSTATUS);
125
 
126
#define H2_READ_ADDR(addr)      (addr | (1<<7))
127
#define H2_WRITE_ADDR(addr)     (addr)
128
 
129
static char *hal2str = "HAL2";
130
 
131
/*
132
 * I doubt anyone has a machine with two HAL2 cards. It's possible to
133
 * have two HPC's, so it is probably possible to have two HAL2 cards.
134
 * Try to deal with it, but note that it is not tested.
135
 */
136
#define MAXCARDS        2
137
static struct hal2_card* hal2_card[MAXCARDS];
138
 
139
static const struct {
140
        unsigned char idx:4, avail:1;
141
} mixtable[SOUND_MIXER_NRDEVICES] = {
142
        [SOUND_MIXER_PCM]       = { H2_MIX_OUTPUT_ATT, 1 },     /* voice */
143
        [SOUND_MIXER_MIC]       = { H2_MIX_INPUT_GAIN, 1 },     /* mic */
144
};
145
 
146
#define H2_SUPPORTED_FORMATS    (AFMT_S16_LE | AFMT_S16_BE)
147
 
148
static inline void hal2_isr_write(struct hal2_card *hal2, u16 val)
149
{
150
        hal2->ctl_regs->isr = val;
151
}
152
 
153
static inline u16 hal2_isr_look(struct hal2_card *hal2)
154
{
155
        return hal2->ctl_regs->isr;
156
}
157
 
158
static inline u16 hal2_rev_look(struct hal2_card *hal2)
159
{
160
        return hal2->ctl_regs->rev;
161
}
162
 
163
#ifdef HAL2_DUMP_REGS
164
static u16 hal2_i_look16(struct hal2_card *hal2, u16 addr)
165
{
166
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
167
 
168
        regs->iar = H2_READ_ADDR(addr);
169
        H2_INDIRECT_WAIT(regs);
170
        return regs->idr0;
171
}
172
#endif
173
 
174
static u32 hal2_i_look32(struct hal2_card *hal2, u16 addr)
175
{
176
        u32 ret;
177
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
178
 
179
        regs->iar = H2_READ_ADDR(addr);
180
        H2_INDIRECT_WAIT(regs);
181
        ret = regs->idr0 & 0xffff;
182
        regs->iar = H2_READ_ADDR(addr | 0x1);
183
        H2_INDIRECT_WAIT(regs);
184
        ret |= (regs->idr0 & 0xffff) << 16;
185
        return ret;
186
}
187
 
188
static void hal2_i_write16(struct hal2_card *hal2, u16 addr, u16 val)
189
{
190
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
191
 
192
        regs->idr0 = val;
193
        regs->idr1 = 0;
194
        regs->idr2 = 0;
195
        regs->idr3 = 0;
196
        regs->iar = H2_WRITE_ADDR(addr);
197
        H2_INDIRECT_WAIT(regs);
198
}
199
 
200
static void hal2_i_write32(struct hal2_card *hal2, u16 addr, u32 val)
201
{
202
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
203
 
204
        regs->idr0 = val & 0xffff;
205
        regs->idr1 = val >> 16;
206
        regs->idr2 = 0;
207
        regs->idr3 = 0;
208
        regs->iar = H2_WRITE_ADDR(addr);
209
        H2_INDIRECT_WAIT(regs);
210
}
211
 
212
static void hal2_i_setbit16(struct hal2_card *hal2, u16 addr, u16 bit)
213
{
214
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
215
 
216
        regs->iar = H2_READ_ADDR(addr);
217
        H2_INDIRECT_WAIT(regs);
218
        regs->idr0 = (regs->idr0 & 0xffff) | bit;
219
        regs->idr1 = 0;
220
        regs->idr2 = 0;
221
        regs->idr3 = 0;
222
        regs->iar = H2_WRITE_ADDR(addr);
223
        H2_INDIRECT_WAIT(regs);
224
}
225
 
226
static void hal2_i_setbit32(struct hal2_card *hal2, u16 addr, u32 bit)
227
{
228
        u32 tmp;
229
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
230
 
231
        regs->iar = H2_READ_ADDR(addr);
232
        H2_INDIRECT_WAIT(regs);
233
        tmp = (regs->idr0 & 0xffff) | (regs->idr1 << 16) | bit;
234
        regs->idr0 = tmp & 0xffff;
235
        regs->idr1 = tmp >> 16;
236
        regs->idr2 = 0;
237
        regs->idr3 = 0;
238
        regs->iar = H2_WRITE_ADDR(addr);
239
        H2_INDIRECT_WAIT(regs);
240
}
241
 
242
static void hal2_i_clearbit16(struct hal2_card *hal2, u16 addr, u16 bit)
243
{
244
        struct hal2_ctl_regs *regs = hal2->ctl_regs;
245
 
246
        regs->iar = H2_READ_ADDR(addr);
247
        H2_INDIRECT_WAIT(regs);
248
        regs->idr0 = (regs->idr0 & 0xffff) & ~bit;
249
        regs->idr1 = 0;
250
        regs->idr2 = 0;
251
        regs->idr3 = 0;
252
        regs->iar = H2_WRITE_ADDR(addr);
253
        H2_INDIRECT_WAIT(regs);
254
}
255
 
256
#if 0
257
static void hal2_i_clearbit32(struct hal2_card *hal2, u16 addr, u32 bit)
258
{
259
        u32 tmp;
260
        hal2_ctl_regs_t *regs = hal2->ctl_regs;
261
 
262
        regs->iar = H2_READ_ADDR(addr);
263
        H2_INDIRECT_WAIT(regs);
264
        tmp = ((regs->idr0 & 0xffff) | (regs->idr1 << 16)) & ~bit;
265
        regs->idr0 = tmp & 0xffff;
266
        regs->idr1 = tmp >> 16;
267
        regs->idr2 = 0;
268
        regs->idr3 = 0;
269
        regs->iar = H2_WRITE_ADDR(addr);
270
        H2_INDIRECT_WAIT(regs);
271
}
272
#endif
273
 
274
#ifdef HAL2_DUMP_REGS
275
static void hal2_dump_regs(struct hal2_card *hal2)
276
{
277
        DEBUG("isr: %08hx ", hal2_isr_look(hal2));
278
        DEBUG("rev: %08hx\n", hal2_rev_look(hal2));
279
        DEBUG("relay: %04hx\n", hal2_i_look16(hal2, H2I_RELAY_C));
280
        DEBUG("port en: %04hx ", hal2_i_look16(hal2, H2I_DMA_PORT_EN));
281
        DEBUG("dma end: %04hx ", hal2_i_look16(hal2, H2I_DMA_END));
282
        DEBUG("dma drv: %04hx\n", hal2_i_look16(hal2, H2I_DMA_DRV));
283
        DEBUG("syn ctl: %04hx ", hal2_i_look16(hal2, H2I_SYNTH_C));
284
        DEBUG("aesrx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESRX_C));
285
        DEBUG("aestx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESTX_C));
286
        DEBUG("dac ctl1: %04hx ", hal2_i_look16(hal2, H2I_ADC_C1));
287
        DEBUG("dac ctl2: %08x ", hal2_i_look32(hal2, H2I_ADC_C2));
288
        DEBUG("adc ctl1: %04hx ", hal2_i_look16(hal2, H2I_DAC_C1));
289
        DEBUG("adc ctl2: %08x ", hal2_i_look32(hal2, H2I_DAC_C2));
290
        DEBUG("syn map: %04hx\n", hal2_i_look16(hal2, H2I_SYNTH_MAP_C));
291
        DEBUG("bres1 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES1_C1));
292
        DEBUG("bres1 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES1_C2));
293
        DEBUG("bres2 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES2_C1));
294
        DEBUG("bres2 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES2_C2));
295
        DEBUG("bres3 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES3_C1));
296
        DEBUG("bres3 ctl2: %04x\n", hal2_i_look32(hal2, H2I_BRES3_C2));
297
}
298
#endif
299
 
300
static struct hal2_card* hal2_dsp_find_card(int minor)
301
{
302
        int i;
303
 
304
        for (i = 0; i < MAXCARDS; i++)
305
                if (hal2_card[i] != NULL && hal2_card[i]->dev_dsp == minor)
306
                        return hal2_card[i];
307
        return NULL;
308
}
309
 
310
static struct hal2_card* hal2_mixer_find_card(int minor)
311
{
312
        int i;
313
 
314
        for (i = 0; i < MAXCARDS; i++)
315
                if (hal2_card[i] != NULL && hal2_card[i]->dev_mixer == minor)
316
                        return hal2_card[i];
317
        return NULL;
318
}
319
 
320
static void hal2_inc_head(struct hal2_codec *codec)
321
{
322
        codec->head++;
323
        if (codec->head == codec->desc_count)
324
                codec->head = 0;
325
}
326
 
327
static void hal2_inc_tail(struct hal2_codec *codec)
328
{
329
        codec->tail++;
330
        if (codec->tail == codec->desc_count)
331
                codec->tail = 0;
332
}
333
 
334
static void hal2_dac_interrupt(struct hal2_codec *dac)
335
{
336
        int running;
337
 
338
        spin_lock(&dac->lock);
339
        /* if tail buffer contains zero samples DMA stream was already
340
         * stopped */
341
        running = dac->desc[dac->tail].cnt;
342
        dac->desc[dac->tail].cnt = 0;
343
        dac->desc[dac->tail].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX;
344
        /* we just proccessed empty buffer, don't update tail pointer */
345
        if (running)
346
                hal2_inc_tail(dac);
347
        spin_unlock(&dac->lock);
348
 
349
        wake_up(&dac->dma_wait);
350
}
351
 
352
static void hal2_adc_interrupt(struct hal2_codec *adc)
353
{
354
        int running;
355
 
356
        spin_lock(&adc->lock);
357
        /* if head buffer contains nonzero samples DMA stream was already
358
         * stopped */
359
        running = !adc->desc[adc->head].cnt;
360
        adc->desc[adc->head].cnt = H2_BLOCK_SIZE;
361
        adc->desc[adc->head].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOR;
362
        /* we just proccessed empty buffer, don't update head pointer */
363
        if (running)
364
                hal2_inc_head(adc);
365
        spin_unlock(&adc->lock);
366
 
367
        wake_up(&adc->dma_wait);
368
}
369
 
370
static void hal2_interrupt(int irq, void *dev_id, struct pt_regs *regs)
371
{
372
        struct hal2_card *hal2 = (struct hal2_card*)dev_id;
373
 
374
        /* decide what caused this interrupt */
375
        if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT)
376
                hal2_dac_interrupt(&hal2->dac);
377
        if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT)
378
                hal2_adc_interrupt(&hal2->adc);
379
}
380
 
381
static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
382
{
383
        unsigned short mod;
384
 
385
        DEBUG("rate: %d\n", rate);
386
 
387
        if (rate < 4000) rate = 4000;
388
        else if (rate > 48000) rate = 48000;
389
 
390
        if (44100 % rate < 48000 % rate) {
391
                mod = 4 * 44100 / rate;
392
                codec->master = 44100;
393
        } else {
394
                mod = 4 * 48000 / rate;
395
                codec->master = 48000;
396
        }
397
 
398
        codec->inc = 4;
399
        codec->mod = mod;
400
        rate = 4 * codec->master / mod;
401
 
402
        DEBUG("real_rate: %d\n", rate);
403
 
404
        return rate;
405
}
406
 
407
static void hal2_set_dac_rate(struct hal2_card *hal2)
408
{
409
        unsigned int master = hal2->dac.master;
410
        int inc = hal2->dac.inc;
411
        int mod = hal2->dac.mod;
412
 
413
        DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
414
 
415
        hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
416
        hal2_i_write32(hal2, H2I_BRES1_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
417
}
418
 
419
static void hal2_set_adc_rate(struct hal2_card *hal2)
420
{
421
        unsigned int master = hal2->adc.master;
422
        int inc = hal2->adc.inc;
423
        int mod = hal2->adc.mod;
424
 
425
        DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
426
 
427
        hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
428
        hal2_i_write32(hal2, H2I_BRES2_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
429
}
430
 
431
static void hal2_setup_dac(struct hal2_card *hal2)
432
{
433
        unsigned int fifobeg, fifoend, highwater, sample_size;
434
        struct hal2_pbus *pbus = &hal2->dac.pbus;
435
 
436
        DEBUG("hal2_setup_dac\n");
437
 
438
        /* Now we set up some PBUS information. The PBUS needs information about
439
         * what portion of the fifo it will use. If it's receiving or
440
         * transmitting, and finally whether the stream is little endian or big
441
         * endian. The information is written later, on the start call.
442
         */
443
        sample_size = 2 * hal2->dac.voices;
444
        /* Fifo should be set to hold exactly four samples. Highwater mark
445
         * should be set to two samples. */
446
        highwater = (sample_size * 2) >> 1;     /* halfwords */
447
        fifobeg = 0;                             /* playback is first */
448
        fifoend = (sample_size * 4) >> 3;       /* doublewords */
449
        pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
450
                     (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
451
                     (hal2->dac.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
452
        /* We disable everything before we do anything at all */
453
        pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
454
        hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
455
        /* Setup the HAL2 for playback */
456
        hal2_set_dac_rate(hal2);
457
        /* Set endianess */
458
        if (hal2->dac.format & AFMT_S16_LE)
459
                hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
460
        else
461
                hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
462
        /* Set DMA bus */
463
        hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
464
        /* We are using 1st Bresenham clock generator for playback */
465
        hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
466
                        | (1 << H2I_C1_CLKID_SHIFT)
467
                        | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
468
}
469
 
470
static void hal2_setup_adc(struct hal2_card *hal2)
471
{
472
        unsigned int fifobeg, fifoend, highwater, sample_size;
473
        struct hal2_pbus *pbus = &hal2->adc.pbus;
474
 
475
        DEBUG("hal2_setup_adc\n");
476
 
477
        sample_size = 2 * hal2->adc.voices;
478
        highwater = (sample_size * 2) >> 1;             /* halfwords */
479
        fifobeg = (4 * 4) >> 3;                         /* record is second */
480
        fifoend = (4 * 4 + sample_size * 4) >> 3;       /* doublewords */
481
        pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
482
                     (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
483
                     (hal2->adc.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
484
        pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
485
        hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
486
        /* Setup the HAL2 for record */
487
        hal2_set_adc_rate(hal2);
488
        /* Set endianess */
489
        if (hal2->adc.format & AFMT_S16_LE)
490
                hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
491
        else
492
                hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
493
        /* Set DMA bus */
494
        hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
495
        /* We are using 2nd Bresenham clock generator for record */
496
        hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
497
                        | (2 << H2I_C1_CLKID_SHIFT)
498
                        | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
499
}
500
 
501
static dma_addr_t hal2_desc_addr(struct hal2_codec *codec, int i)
502
{
503
        if (--i < 0)
504
                i = codec->desc_count - 1;
505
        return codec->desc[i].desc.pnext;
506
}
507
 
508
static void hal2_start_dac(struct hal2_card *hal2)
509
{
510
        struct hal2_codec *dac = &hal2->dac;
511
        struct hal2_pbus *pbus = &dac->pbus;
512
 
513
        pbus->pbus->pbdma_dptr = hal2_desc_addr(dac, dac->tail);
514
        pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
515
        /* enable DAC */
516
        hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
517
}
518
 
519
static void hal2_start_adc(struct hal2_card *hal2)
520
{
521
        struct hal2_codec *adc = &hal2->adc;
522
        struct hal2_pbus *pbus = &adc->pbus;
523
 
524
        pbus->pbus->pbdma_dptr = hal2_desc_addr(adc, adc->head);
525
        pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
526
        /* enable ADC */
527
        hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
528
}
529
 
530
static inline void hal2_stop_dac(struct hal2_card *hal2)
531
{
532
        hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
533
        /* The HAL2 itself may remain enabled safely */
534
}
535
 
536
static inline void hal2_stop_adc(struct hal2_card *hal2)
537
{
538
        hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
539
}
540
 
541
static int hal2_alloc_dmabuf(struct hal2_codec *codec, int size,
542
                             int count, int cntinfo, int dir)
543
{
544
        struct hal2_desc *desc, *dma_addr;
545
        int i;
546
 
547
        DEBUG("allocating %dk DMA buffer.\n", size / 1024);
548
 
549
        codec->buffer = (unsigned char *)__get_free_pages(GFP_KERNEL | GFP_DMA,
550
                                                          get_order(size));
551
        if (!codec->buffer)
552
                return -ENOMEM;
553
        desc = pci_alloc_consistent(NULL, count * sizeof(struct hal2_desc),
554
                                    (dma_addr_t *)&dma_addr);
555
        if (!desc) {
556
                free_pages((unsigned long)codec->buffer, get_order(size));
557
                return -ENOMEM;
558
        }
559
        codec->desc = desc;
560
        for (i = 0; i < count; i++) {
561
                desc->desc.pbuf = pci_map_single(NULL,
562
                        (void *)(codec->buffer + i * H2_BLOCK_SIZE),
563
                        H2_BLOCK_SIZE, dir);
564
                desc->desc.cntinfo = cntinfo;
565
                desc->desc.pnext = (i == count - 1) ?
566
                                   (u32)dma_addr : (u32)(dma_addr + i + 1);
567
                desc->cnt = 0;
568
                desc++;
569
        }
570
        codec->desc_count = count;
571
        codec->head = codec->tail = 0;
572
        return 0;
573
}
574
 
575
static int hal2_alloc_dac_dmabuf(struct hal2_codec *codec)
576
{
577
        return hal2_alloc_dmabuf(codec, H2_DAC_BUFSIZE,
578
                                 H2_DAC_BUFSIZE / H2_BLOCK_SIZE,
579
                                 HPCDMA_XIE | HPCDMA_EOX,
580
                                 PCI_DMA_TODEVICE);
581
}
582
 
583
static int hal2_alloc_adc_dmabuf(struct hal2_codec *codec)
584
{
585
        return hal2_alloc_dmabuf(codec, H2_ADC_BUFSIZE,
586
                                 H2_ADC_BUFSIZE / H2_BLOCK_SIZE,
587
                                 HPCDMA_XIE | H2_BLOCK_SIZE,
588
                                 PCI_DMA_FROMDEVICE);
589
}
590
 
591
static void hal2_free_dmabuf(struct hal2_codec *codec, int size, int dir)
592
{
593
        dma_addr_t dma_addr;
594
        int i;
595
 
596
        dma_addr = codec->desc[codec->desc_count - 1].desc.pnext;
597
        for (i = 0; i < codec->desc_count; i++)
598
                pci_unmap_single(NULL, codec->desc[i].desc.pbuf,
599
                                 H2_BLOCK_SIZE, dir);
600
        pci_free_consistent(NULL, codec->desc_count * sizeof(struct hal2_desc),
601
                            (void *)codec->desc, dma_addr);
602
        free_pages((unsigned long)codec->buffer, get_order(size));
603
}
604
 
605
static void hal2_free_dac_dmabuf(struct hal2_codec *codec)
606
{
607
        return hal2_free_dmabuf(codec, H2_DAC_BUFSIZE, PCI_DMA_TODEVICE);
608
}
609
 
610
static void hal2_free_adc_dmabuf(struct hal2_codec *codec)
611
{
612
        return hal2_free_dmabuf(codec, H2_ADC_BUFSIZE, PCI_DMA_FROMDEVICE);
613
}
614
 
615
/*
616
 * Add 'count' bytes to 'buffer' from DMA ring buffers. Return number of
617
 * bytes added or -EFAULT if copy_from_user failed.
618
 */
619
static int hal2_get_buffer(struct hal2_card *hal2, char *buffer, int count)
620
{
621
        unsigned long flags;
622
        int size, ret = 0;
623
        unsigned char *buf;
624
        struct hal2_desc *tail;
625
        struct hal2_codec *adc = &hal2->adc;
626
 
627
        DEBUG("getting %d bytes ", count);
628
 
629
        spin_lock_irqsave(&adc->lock, flags);
630
        tail = &adc->desc[adc->tail];
631
        /* enable DMA stream if there are no data */
632
        if (!tail->cnt && !(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
633
                hal2_start_adc(hal2);
634
        while (tail->cnt > 0 && count > 0) {
635
                size = min((int)tail->cnt, count);
636
                buf = &adc->buffer[(adc->tail + 1) * H2_BLOCK_SIZE - tail->cnt];
637
                spin_unlock_irqrestore(&adc->lock, flags);
638
                pci_dma_sync_single(NULL, tail->desc.pbuf, size,
639
                                    PCI_DMA_FROMDEVICE);
640
                if (copy_to_user(buffer, buf, size)) {
641
                        ret = -EFAULT;
642
                        goto out;
643
                }
644
                spin_lock_irqsave(&adc->lock, flags);
645
                tail->cnt -= size;
646
                /* buffer is empty, update tail pointer */
647
                if (tail->cnt == 0) {
648
                        tail->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
649
                        hal2_inc_tail(adc);
650
                        tail = &adc->desc[adc->tail];
651
                        /* enable DMA stream again if needed */
652
                        if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
653
                                hal2_start_adc(hal2);
654
                }
655
                buffer += size;
656
                ret += size;
657
                count -= size;
658
 
659
                DEBUG("(%d) ", size);
660
        }
661
        spin_unlock_irqrestore(&adc->lock, flags);
662
out:
663
        DEBUG("\n");
664
 
665
        return ret;
666
}
667
 
668
/*
669
 * Add 'count' bytes from 'buffer' to DMA ring buffers. Return number of
670
 * bytes added or -EFAULT if copy_from_user failed.
671
 */
672
static int hal2_add_buffer(struct hal2_card *hal2, char *buffer, int count)
673
{
674
        unsigned long flags;
675
        unsigned char *buf;
676
        int size, ret = 0;
677
        struct hal2_desc *head;
678
        struct hal2_codec *dac = &hal2->dac;
679
 
680
        DEBUG("adding %d bytes ", count);
681
 
682
        spin_lock_irqsave(&dac->lock, flags);
683
        head = &dac->desc[dac->head];
684
        while (head->cnt == 0 && count > 0) {
685
                size = min((int)H2_BLOCK_SIZE, count);
686
                buf = &dac->buffer[dac->head * H2_BLOCK_SIZE];
687
                spin_unlock_irqrestore(&dac->lock, flags);
688
                if (copy_from_user(buf, buffer, size)) {
689
                        ret = -EFAULT;
690
                        goto out;
691
                }
692
                pci_dma_sync_single(NULL, head->desc.pbuf, size,
693
                                    PCI_DMA_TODEVICE);
694
                spin_lock_irqsave(&dac->lock, flags);
695
                head->desc.cntinfo = size | HPCDMA_XIE;
696
                head->cnt = size;
697
                buffer += size;
698
                ret += size;
699
                count -= size;
700
                hal2_inc_head(dac);
701
                head = &dac->desc[dac->head];
702
 
703
                DEBUG("(%d) ", size);
704
        }
705
        if (!(dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) && ret > 0)
706
                hal2_start_dac(hal2);
707
        spin_unlock_irqrestore(&dac->lock, flags);
708
out:
709
        DEBUG("\n");
710
 
711
        return ret;
712
}
713
 
714
#define hal2_reset_dac_pointer(hal2)    hal2_reset_pointer(hal2, 1)
715
#define hal2_reset_adc_pointer(hal2)    hal2_reset_pointer(hal2, 0)
716
static void hal2_reset_pointer(struct hal2_card *hal2, int is_dac)
717
{
718
        int i;
719
        struct hal2_codec *codec = (is_dac) ? &hal2->dac : &hal2->adc;
720
 
721
        DEBUG("hal2_reset_pointer\n");
722
 
723
        for (i = 0; i < codec->desc_count; i++) {
724
                codec->desc[i].cnt = 0;
725
                codec->desc[i].desc.cntinfo = HPCDMA_XIE | (is_dac) ?
726
                                              HPCDMA_EOX : H2_BLOCK_SIZE;
727
        }
728
        codec->head = codec->tail = 0;
729
}
730
 
731
static int hal2_sync_dac(struct hal2_card *hal2)
732
{
733
        DECLARE_WAITQUEUE(wait, current);
734
        struct hal2_codec *dac = &hal2->dac;
735
        int ret = 0;
736
        unsigned long flags;
737
        signed long timeout = 1000 * H2_BLOCK_SIZE * 2 * dac->voices *
738
                              HZ / dac->sample_rate / 900;
739
 
740
        while (dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) {
741
                add_wait_queue(&dac->dma_wait, &wait);
742
                set_current_state(TASK_INTERRUPTIBLE);
743
                schedule_timeout(timeout);
744
                spin_lock_irqsave(&dac->lock, flags);
745
                if (dac->desc[dac->tail].cnt)
746
                        ret = -ETIME;
747
                spin_unlock_irqrestore(&dac->lock, flags);
748
                if (signal_pending(current))
749
                        ret = -ERESTARTSYS;
750
                if (ret) {
751
                        hal2_stop_dac(hal2);
752
                        hal2_reset_dac_pointer(hal2);
753
                }
754
                remove_wait_queue(&dac->dma_wait, &wait);
755
        }
756
 
757
        return ret;
758
}
759
 
760
static int hal2_write_mixer(struct hal2_card *hal2, int index, int vol)
761
{
762
        unsigned int l, r, tmp;
763
 
764
        DEBUG_MIX("mixer %d write\n", index);
765
 
766
        if (index >= SOUND_MIXER_NRDEVICES || !mixtable[index].avail)
767
                return -EINVAL;
768
 
769
        r = (vol >> 8) & 0xff;
770
        if (r > 100)
771
                r = 100;
772
        l = vol & 0xff;
773
        if (l > 100)
774
                l = 100;
775
 
776
        hal2->mixer.volume[mixtable[index].idx] = l | (r << 8);
777
 
778
        switch (mixtable[index].idx) {
779
        case H2_MIX_OUTPUT_ATT:
780
 
781
                DEBUG_MIX("output attenuator %d,%d\n", l, r);
782
 
783
                if (r | l) {
784
                        tmp = hal2_i_look32(hal2, H2I_DAC_C2);
785
                        tmp &= ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
786
 
787
                        /* Attenuator has five bits */
788
                        l = 31 * (100 - l) / 99;
789
                        r = 31 * (100 - r) / 99;
790
 
791
                        DEBUG_MIX("left: %d, right %d\n", l, r);
792
 
793
                        tmp |= (l << H2I_C2_L_ATT_SHIFT) & H2I_C2_L_ATT_M;
794
                        tmp |= (r << H2I_C2_R_ATT_SHIFT) & H2I_C2_R_ATT_M;
795
                        hal2_i_write32(hal2, H2I_DAC_C2, tmp);
796
                } else
797
                        hal2_i_setbit32(hal2, H2I_DAC_C2, H2I_C2_MUTE);
798
                break;
799
        case H2_MIX_INPUT_GAIN:
800
 
801
                DEBUG_MIX("input gain %d,%d\n", l, r);
802
 
803
                tmp = hal2_i_look32(hal2, H2I_ADC_C2);
804
                tmp &= ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
805
 
806
                /* Gain control has four bits */
807
                l = 16 * l / 100;
808
                r = 16 * r / 100;
809
 
810
                DEBUG_MIX("left: %d, right %d\n", l, r);
811
 
812
                tmp |= (l << H2I_C2_L_GAIN_SHIFT) & H2I_C2_L_GAIN_M;
813
                tmp |= (r << H2I_C2_R_GAIN_SHIFT) & H2I_C2_R_GAIN_M;
814
                hal2_i_write32(hal2, H2I_ADC_C2, tmp);
815
 
816
                break;
817
        }
818
 
819
        return 0;
820
}
821
 
822
static void hal2_init_mixer(struct hal2_card *hal2)
823
{
824
        int i;
825
 
826
        for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
827
                if (mixtable[i].avail)
828
                        hal2->mixer.volume[mixtable[i].idx] = 100 | (100 << 8);
829
 
830
        /* disable attenuator */
831
        hal2_i_write32(hal2, H2I_DAC_C2, 0);
832
        /* set max input gain */
833
        hal2_i_write32(hal2, H2I_ADC_C2, H2I_C2_MUTE |
834
                        (H2I_C2_L_GAIN_M << H2I_C2_L_GAIN_SHIFT) |
835
                        (H2I_C2_R_GAIN_M << H2I_C2_R_GAIN_SHIFT));
836
        /* set max volume */
837
        hal2->mixer.master = 0xff;
838
        hal2->vol_regs->left = 0xff;
839
        hal2->vol_regs->right = 0xff;
840
}
841
 
842
/*
843
 * XXX: later i'll implement mixer for main volume which will be disabled
844
 * by default. enabling it users will be allowed to have master volume level
845
 * control on panel in their favourite X desktop
846
 */
847
static void hal2_volume_control(int direction)
848
{
849
        unsigned int master = hal2_card[0]->mixer.master;
850
        struct hal2_vol_regs *vol = hal2_card[0]->vol_regs;
851
 
852
        /* volume up */
853
        if (direction > 0 && master < 0xff)
854
                master++;
855
        /* volume down */
856
        else if (direction < 0 && master > 0)
857
                master--;
858
        /* TODO: mute/unmute */
859
        vol->left = master;
860
        vol->right = master;
861
        hal2_card[0]->mixer.master = master;
862
}
863
 
864
static int hal2_mixer_ioctl(struct hal2_card *hal2, unsigned int cmd,
865
                            unsigned long arg)
866
{
867
        int val;
868
 
869
        if (cmd == SOUND_MIXER_INFO) {
870
                mixer_info info;
871
 
872
                strncpy(info.id, hal2str, sizeof(info.id));
873
                strncpy(info.name, hal2str, sizeof(info.name));
874
                info.modify_counter = hal2->mixer.modcnt;
875
                if (copy_to_user((void *)arg, &info, sizeof(info)))
876
                        return -EFAULT;
877
                return 0;
878
        }
879
        if (cmd == SOUND_OLD_MIXER_INFO) {
880
                _old_mixer_info info;
881
 
882
                strncpy(info.id, hal2str, sizeof(info.id));
883
                strncpy(info.name, hal2str, sizeof(info.name));
884
                if (copy_to_user((void *)arg, &info, sizeof(info)))
885
                        return -EFAULT;
886
                return 0;
887
        }
888
        if (cmd == OSS_GETVERSION)
889
                return put_user(SOUND_VERSION, (int *)arg);
890
 
891
        if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
892
                return -EINVAL;
893
 
894
        if (_IOC_DIR(cmd) == _IOC_READ) {
895
                switch (_IOC_NR(cmd)) {
896
                /* Give the current record source */
897
                case SOUND_MIXER_RECSRC:
898
                        val = 0; /* FIXME */
899
                        break;
900
                /* Give the supported mixers, all of them support stereo */
901
                case SOUND_MIXER_DEVMASK:
902
                case SOUND_MIXER_STEREODEVS: {
903
                        int i;
904
 
905
                        for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
906
                                if (mixtable[i].avail)
907
                                        val |= 1 << i;
908
                        break;
909
                        }
910
                /* Arg contains a bit for each supported recording source */
911
                case SOUND_MIXER_RECMASK:
912
                        val = 0;
913
                        break;
914
                case SOUND_MIXER_CAPS:
915
                        val = 0;
916
                        break;
917
                /* Read a specific mixer */
918
                default: {
919
                        int i = _IOC_NR(cmd);
920
 
921
                        if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail)
922
                                return -EINVAL;
923
                        val = hal2->mixer.volume[mixtable[i].idx];
924
                        break;
925
                        }
926
                }
927
                return put_user(val, (int *)arg);
928
        }
929
 
930
        if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
931
                return -EINVAL;
932
 
933
        hal2->mixer.modcnt++;
934
 
935
        if (get_user(val, (int *)arg))
936
                return -EFAULT;
937
 
938
        switch (_IOC_NR(cmd)) {
939
        /* Arg contains a bit for each recording source */
940
        case SOUND_MIXER_RECSRC:
941
                return 0;        /* FIXME */
942
        default:
943
                return hal2_write_mixer(hal2, _IOC_NR(cmd), val);
944
        }
945
 
946
        return 0;
947
}
948
 
949
static int hal2_open_mixdev(struct inode *inode, struct file *file)
950
{
951
        struct hal2_card *hal2 = hal2_mixer_find_card(minor(inode->i_rdev));
952
 
953
        if (hal2) {
954
                file->private_data = hal2;
955
                return 0;
956
        }
957
        return -ENODEV;
958
}
959
 
960
static int hal2_release_mixdev(struct inode *inode, struct file *file)
961
{
962
        return 0;
963
}
964
 
965
static int hal2_ioctl_mixdev(struct inode *inode, struct file *file,
966
                             unsigned int cmd, unsigned long arg)
967
{
968
        return hal2_mixer_ioctl((struct hal2_card *)file->private_data, cmd, arg);
969
}
970
 
971
static int hal2_ioctl(struct inode *inode, struct file *file,
972
                      unsigned int cmd, unsigned long arg)
973
{
974
        int val;
975
        struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
976
 
977
        switch (cmd) {
978
        case OSS_GETVERSION:
979
                return put_user(SOUND_VERSION, (int *)arg);
980
 
981
        case SNDCTL_DSP_SYNC:
982
                if (file->f_mode & FMODE_WRITE)
983
                        return hal2_sync_dac(hal2);
984
                return 0;
985
 
986
        case SNDCTL_DSP_SETDUPLEX:
987
                return 0;
988
 
989
        case SNDCTL_DSP_GETCAPS:
990
                return put_user(DSP_CAP_DUPLEX | DSP_CAP_MULTI, (int *)arg);
991
 
992
        case SNDCTL_DSP_RESET:
993
                if (file->f_mode & FMODE_READ) {
994
                        hal2_stop_adc(hal2);
995
                        hal2_reset_adc_pointer(hal2);
996
                }
997
                if (file->f_mode & FMODE_WRITE) {
998
                        hal2_stop_dac(hal2);
999
                        hal2_reset_dac_pointer(hal2);
1000
                }
1001
                return 0;
1002
 
1003
        case SNDCTL_DSP_SPEED:
1004
                if (get_user(val, (int *)arg))
1005
                        return -EFAULT;
1006
                if (file->f_mode & FMODE_READ) {
1007
                        hal2_stop_adc(hal2);
1008
                        val = hal2_compute_rate(&hal2->adc, val);
1009
                        hal2->adc.sample_rate = val;
1010
                        hal2_set_adc_rate(hal2);
1011
                }
1012
                if (file->f_mode & FMODE_WRITE) {
1013
                        hal2_stop_dac(hal2);
1014
                        val = hal2_compute_rate(&hal2->dac, val);
1015
                        hal2->dac.sample_rate = val;
1016
                        hal2_set_dac_rate(hal2);
1017
                }
1018
                return put_user(val, (int *)arg);
1019
 
1020
        case SNDCTL_DSP_STEREO:
1021
                if (get_user(val, (int *)arg))
1022
                        return -EFAULT;
1023
                if (file->f_mode & FMODE_READ) {
1024
                        hal2_stop_adc(hal2);
1025
                        hal2->adc.voices = (val) ? 2 : 1;
1026
                        hal2_setup_adc(hal2);
1027
                }
1028
                if (file->f_mode & FMODE_WRITE) {
1029
                        hal2_stop_dac(hal2);
1030
                        hal2->dac.voices = (val) ? 2 : 1;
1031
                        hal2_setup_dac(hal2);
1032
                }
1033
                return 0;
1034
 
1035
        case SNDCTL_DSP_CHANNELS:
1036
                if (get_user(val, (int *)arg))
1037
                        return -EFAULT;
1038
                if (val != 0) {
1039
                        if (file->f_mode & FMODE_READ) {
1040
                                hal2_stop_adc(hal2);
1041
                                hal2->adc.voices = (val == 1) ? 1 : 2;
1042
                                hal2_setup_adc(hal2);
1043
                        }
1044
                        if (file->f_mode & FMODE_WRITE) {
1045
                                hal2_stop_dac(hal2);
1046
                                hal2->dac.voices = (val == 1) ? 1 : 2;
1047
                                hal2_setup_dac(hal2);
1048
                        }
1049
                }
1050
                val = -EINVAL;
1051
                if (file->f_mode & FMODE_READ)
1052
                        val = hal2->adc.voices;
1053
                if (file->f_mode & FMODE_WRITE)
1054
                        val = hal2->dac.voices;
1055
                return put_user(val, (int *)arg);
1056
 
1057
        case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1058
                return put_user(H2_SUPPORTED_FORMATS, (int *)arg);
1059
 
1060
        case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1061
                if (get_user(val, (int *)arg))
1062
                        return -EFAULT;
1063
                if (val != AFMT_QUERY) {
1064
                        if (!(val & H2_SUPPORTED_FORMATS))
1065
                                return -EINVAL;
1066
                        if (file->f_mode & FMODE_READ) {
1067
                                hal2_stop_adc(hal2);
1068
                                hal2->adc.format = val;
1069
                                hal2_setup_adc(hal2);
1070
                        }
1071
                        if (file->f_mode & FMODE_WRITE) {
1072
                                hal2_stop_dac(hal2);
1073
                                hal2->dac.format = val;
1074
                                hal2_setup_dac(hal2);
1075
                        }
1076
                } else {
1077
                        val = -EINVAL;
1078
                        if (file->f_mode & FMODE_READ)
1079
                                val = hal2->adc.format;
1080
                        if (file->f_mode & FMODE_WRITE)
1081
                                val = hal2->dac.format;
1082
                }
1083
                return put_user(val, (int *)arg);
1084
 
1085
        case SNDCTL_DSP_POST:
1086
                return 0;
1087
 
1088
        case SNDCTL_DSP_GETOSPACE: {
1089
                audio_buf_info info;
1090
                int i;
1091
                unsigned long flags;
1092
                struct hal2_codec *dac = &hal2->dac;
1093
 
1094
                if (!(file->f_mode & FMODE_WRITE))
1095
                        return -EINVAL;
1096
                info.fragments = 0;
1097
                spin_lock_irqsave(&dac->lock, flags);
1098
                for (i = 0; i < dac->desc_count; i++)
1099
                        if (dac->desc[i].cnt == 0)
1100
                                info.fragments++;
1101
                spin_unlock_irqrestore(&dac->lock, flags);
1102
                info.fragstotal = dac->desc_count;
1103
                info.fragsize = H2_BLOCK_SIZE;
1104
                info.bytes = info.fragsize * info.fragments;
1105
 
1106
                return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1107
        }
1108
 
1109
        case SNDCTL_DSP_GETISPACE: {
1110
                audio_buf_info info;
1111
                int i;
1112
                unsigned long flags;
1113
                struct hal2_codec *adc = &hal2->adc;
1114
 
1115
                if (!(file->f_mode & FMODE_READ))
1116
                        return -EINVAL;
1117
                info.fragments = 0;
1118
                info.bytes = 0;
1119
                spin_lock_irqsave(&adc->lock, flags);
1120
                for (i = 0; i < adc->desc_count; i++)
1121
                        if (adc->desc[i].cnt > 0) {
1122
                                info.fragments++;
1123
                                info.bytes += adc->desc[i].cnt;
1124
                        }
1125
                spin_unlock_irqrestore(&adc->lock, flags);
1126
                info.fragstotal = adc->desc_count;
1127
                info.fragsize = H2_BLOCK_SIZE;
1128
 
1129
                return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1130
        }
1131
 
1132
        case SNDCTL_DSP_NONBLOCK:
1133
                file->f_flags |= O_NONBLOCK;
1134
                return 0;
1135
 
1136
        case SNDCTL_DSP_GETBLKSIZE:
1137
                return put_user(H2_BLOCK_SIZE, (int *)arg);
1138
 
1139
        case SNDCTL_DSP_SETFRAGMENT:
1140
                return 0;
1141
 
1142
        case SOUND_PCM_READ_RATE:
1143
                val = -EINVAL;
1144
                if (file->f_mode & FMODE_READ)
1145
                        val = hal2->adc.sample_rate;
1146
                if (file->f_mode & FMODE_WRITE)
1147
                        val = hal2->dac.sample_rate;
1148
                return put_user(val, (int *)arg);
1149
 
1150
        case SOUND_PCM_READ_CHANNELS:
1151
                val = -EINVAL;
1152
                if (file->f_mode & FMODE_READ)
1153
                        val = hal2->adc.voices;
1154
                if (file->f_mode & FMODE_WRITE)
1155
                        val = hal2->dac.voices;
1156
                return put_user(val, (int *)arg);
1157
 
1158
        case SOUND_PCM_READ_BITS:
1159
                return put_user(16, (int *)arg);
1160
        }
1161
 
1162
        return hal2_mixer_ioctl(hal2, cmd, arg);
1163
}
1164
 
1165
static ssize_t hal2_read(struct file *file, char *buffer,
1166
                         size_t count, loff_t *ppos)
1167
{
1168
        ssize_t err;
1169
        struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1170
        struct hal2_codec *adc = &hal2->adc;
1171
 
1172
        if (!count)
1173
                return 0;
1174
        if (ppos != &file->f_pos)
1175
                return -ESPIPE;
1176
        if (down_interruptible(&adc->sem))
1177
                return -EINTR;
1178
        if (file->f_flags & O_NONBLOCK) {
1179
                err = hal2_get_buffer(hal2, buffer, count);
1180
                err = err == 0 ? -EAGAIN : err;
1181
        } else {
1182
                do {
1183
                        /* ~10% longer */
1184
                        signed long timeout = 1000 * H2_BLOCK_SIZE *
1185
                                2 * adc->voices * HZ / adc->sample_rate / 900;
1186
                        unsigned long flags;
1187
                        DECLARE_WAITQUEUE(wait, current);
1188
                        ssize_t cnt = 0;
1189
 
1190
                        err = hal2_get_buffer(hal2, buffer, count);
1191
                        if (err > 0) {
1192
                                count -= err;
1193
                                cnt += err;
1194
                                buffer += err;
1195
                                err = cnt;
1196
                        }
1197
                        if (count > 0 && err >= 0) {
1198
                                add_wait_queue(&adc->dma_wait, &wait);
1199
                                set_current_state(TASK_INTERRUPTIBLE);
1200
                                schedule_timeout(timeout);
1201
                                spin_lock_irqsave(&adc->lock, flags);
1202
                                if (!adc->desc[adc->tail].cnt)
1203
                                        err = -EAGAIN;
1204
                                spin_unlock_irqrestore(&adc->lock, flags);
1205
                                if (signal_pending(current))
1206
                                        err = -ERESTARTSYS;
1207
                                remove_wait_queue(&adc->dma_wait, &wait);
1208
                                if (err < 0) {
1209
                                        hal2_stop_adc(hal2);
1210
                                        hal2_reset_adc_pointer(hal2);
1211
                                }
1212
                        }
1213
                } while (count > 0 && err >= 0);
1214
        }
1215
        up(&adc->sem);
1216
 
1217
        return err;
1218
}
1219
 
1220
static ssize_t hal2_write(struct file *file, const char *buffer,
1221
                          size_t count, loff_t *ppos)
1222
{
1223
        ssize_t err;
1224
        char *buf = (char*) buffer;
1225
        struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1226
        struct hal2_codec *dac = &hal2->dac;
1227
 
1228
        if (!count)
1229
                return 0;
1230
        if (ppos != &file->f_pos)
1231
                return -ESPIPE;
1232
        if (down_interruptible(&dac->sem))
1233
                return -EINTR;
1234
        if (file->f_flags & O_NONBLOCK) {
1235
                err = hal2_add_buffer(hal2, buf, count);
1236
                err = err == 0 ? -EAGAIN : err;
1237
        } else {
1238
                do {
1239
                        /* ~10% longer */
1240
                        signed long timeout = 1000 * H2_BLOCK_SIZE *
1241
                                2 * dac->voices * HZ / dac->sample_rate / 900;
1242
                        unsigned long flags;
1243
                        DECLARE_WAITQUEUE(wait, current);
1244
                        ssize_t cnt = 0;
1245
 
1246
                        err = hal2_add_buffer(hal2, buf, count);
1247
                        if (err > 0) {
1248
                                count -= err;
1249
                                cnt += err;
1250
                                buf += err;
1251
                                err = cnt;
1252
                        }
1253
                        if (count > 0 && err >= 0) {
1254
                                add_wait_queue(&dac->dma_wait, &wait);
1255
                                set_current_state(TASK_INTERRUPTIBLE);
1256
                                schedule_timeout(timeout);
1257
                                spin_lock_irqsave(&dac->lock, flags);
1258
                                if (dac->desc[dac->head].cnt)
1259
                                        err = -EAGAIN;
1260
                                spin_unlock_irqrestore(&dac->lock, flags);
1261
                                if (signal_pending(current))
1262
                                        err = -ERESTARTSYS;
1263
                                remove_wait_queue(&dac->dma_wait, &wait);
1264
                                if (err < 0) {
1265
                                        hal2_stop_dac(hal2);
1266
                                        hal2_reset_dac_pointer(hal2);
1267
                                }
1268
                        }
1269
                } while (count > 0 && err >= 0);
1270
        }
1271
        up(&dac->sem);
1272
 
1273
        return err;
1274
}
1275
 
1276
static unsigned int hal2_poll(struct file *file, struct poll_table_struct *wait)
1277
{
1278
        unsigned long flags;
1279
        unsigned int mask = 0;
1280
        struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1281
 
1282
        if (file->f_mode & FMODE_READ) {
1283
                struct hal2_codec *adc = &hal2->adc;
1284
 
1285
                poll_wait(file, &adc->dma_wait, wait);
1286
                spin_lock_irqsave(&adc->lock, flags);
1287
                if (adc->desc[adc->tail].cnt > 0)
1288
                        mask |= POLLIN;
1289
                spin_unlock_irqrestore(&adc->lock, flags);
1290
        }
1291
 
1292
        if (file->f_mode & FMODE_WRITE) {
1293
                struct hal2_codec *dac = &hal2->dac;
1294
 
1295
                poll_wait(file, &dac->dma_wait, wait);
1296
                spin_lock_irqsave(&dac->lock, flags);
1297
                if (dac->desc[dac->head].cnt == 0)
1298
                        mask |= POLLOUT;
1299
                spin_unlock_irqrestore(&dac->lock, flags);
1300
        }
1301
 
1302
        return mask;
1303
}
1304
 
1305
static int hal2_open(struct inode *inode, struct file *file)
1306
{
1307
        int err;
1308
        struct hal2_card *hal2 = hal2_dsp_find_card(minor(inode->i_rdev));
1309
 
1310
        if (!hal2)
1311
                return -ENODEV;
1312
        file->private_data = hal2;
1313
        if (file->f_mode & FMODE_READ) {
1314
                struct hal2_codec *adc = &hal2->adc;
1315
 
1316
                if (adc->usecount)
1317
                        return -EBUSY;
1318
                /* OSS spec wanted us to use 8 bit, 8 kHz mono by default,
1319
                 * but HAL2 can't do 8bit audio */
1320
                adc->format = AFMT_S16_BE;
1321
                adc->voices = 1;
1322
                adc->sample_rate = hal2_compute_rate(adc, 8000);
1323
                hal2_set_adc_rate(hal2);
1324
                err = hal2_alloc_adc_dmabuf(adc);
1325
                if (err)
1326
                        return err;
1327
                hal2_setup_adc(hal2);
1328
                adc->usecount++;
1329
        }
1330
        if (file->f_mode & FMODE_WRITE) {
1331
                struct hal2_codec *dac = &hal2->dac;
1332
 
1333
                if (dac->usecount)
1334
                        return -EBUSY;
1335
                dac->format = AFMT_S16_BE;
1336
                dac->voices = 1;
1337
                dac->sample_rate = hal2_compute_rate(dac, 8000);
1338
                hal2_set_dac_rate(hal2);
1339
                err = hal2_alloc_dac_dmabuf(dac);
1340
                if (err)
1341
                        return err;
1342
                hal2_setup_dac(hal2);
1343
                dac->usecount++;
1344
        }
1345
 
1346
        return 0;
1347
}
1348
 
1349
static int hal2_release(struct inode *inode, struct file *file)
1350
{
1351
        struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1352
 
1353
        if (file->f_mode & FMODE_READ) {
1354
                struct hal2_codec *adc = &hal2->adc;
1355
 
1356
                down(&adc->sem);
1357
                hal2_stop_adc(hal2);
1358
                hal2_free_adc_dmabuf(adc);
1359
                adc->usecount--;
1360
                up(&adc->sem);
1361
        }
1362
        if (file->f_mode & FMODE_WRITE) {
1363
                struct hal2_codec *dac = &hal2->dac;
1364
 
1365
                down(&dac->sem);
1366
                hal2_sync_dac(hal2);
1367
                hal2_free_dac_dmabuf(dac);
1368
                dac->usecount--;
1369
                up(&dac->sem);
1370
        }
1371
 
1372
        return 0;
1373
}
1374
 
1375
static struct file_operations hal2_audio_fops = {
1376
        .owner          = THIS_MODULE,
1377
        .llseek         = no_llseek,
1378
        .read           = hal2_read,
1379
        .write          = hal2_write,
1380
        .poll           = hal2_poll,
1381
        .ioctl          = hal2_ioctl,
1382
        .open           = hal2_open,
1383
        .release        = hal2_release,
1384
};
1385
 
1386
static struct file_operations hal2_mixer_fops = {
1387
        .owner          = THIS_MODULE,
1388
        .llseek         = no_llseek,
1389
        .ioctl          = hal2_ioctl_mixdev,
1390
        .open           = hal2_open_mixdev,
1391
        .release        = hal2_release_mixdev,
1392
};
1393
 
1394
static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
1395
                            int index)
1396
{
1397
        codec->pbus.pbusnr = index;
1398
        codec->pbus.pbus = &hpc3->pbdma[index];
1399
        init_waitqueue_head(&codec->dma_wait);
1400
        init_MUTEX(&codec->sem);
1401
        spin_lock_init(&codec->lock);
1402
}
1403
 
1404
static int hal2_detect(struct hal2_card *hal2)
1405
{
1406
        unsigned short board, major, minor;
1407
        unsigned short rev;
1408
 
1409
        /* reset HAL2 */
1410
        hal2_isr_write(hal2, 0);
1411
        /* release reset */
1412
        hal2_isr_write(hal2, H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N);
1413
 
1414
        hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
1415
        if ((rev = hal2_rev_look(hal2)) & H2_REV_AUDIO_PRESENT)
1416
                return -ENODEV;
1417
 
1418
        board = (rev & H2_REV_BOARD_M) >> 12;
1419
        major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
1420
        minor = (rev & H2_REV_MINOR_CHIP_M);
1421
 
1422
        printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
1423
               board, major, minor);
1424
 
1425
        return 0;
1426
}
1427
 
1428
static int hal2_init_card(struct hal2_card **phal2, struct hpc3_regs *hpc3)
1429
{
1430
        int ret = 0;
1431
        struct hal2_card *hal2;
1432
 
1433
        hal2 = (struct hal2_card *) kmalloc(sizeof(struct hal2_card), GFP_KERNEL);
1434
        if (!hal2)
1435
                return -ENOMEM;
1436
        memset(hal2, 0, sizeof(struct hal2_card));
1437
 
1438
        hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
1439
        hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
1440
        hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
1441
        hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
1442
 
1443
        if (hal2_detect(hal2) < 0) {
1444
                ret = -ENODEV;
1445
                goto free_card;
1446
        }
1447
 
1448
        hal2_init_codec(&hal2->dac, hpc3, 0);
1449
        hal2_init_codec(&hal2->adc, hpc3, 1);
1450
 
1451
        /*
1452
         * All DMA channel interfaces in HAL2 are designed to operate with
1453
         * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
1454
         * in D5. HAL2 is a 16-bit device which can accept both big and little
1455
         * endian format. It assumes that even address bytes are on high
1456
         * portion of PBUS (15:8) and assumes that HPC3 is programmed to
1457
         * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
1458
         */
1459
#define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
1460
                          (2 << HPC3_DMACFG_D4R_SHIFT) | \
1461
                          (2 << HPC3_DMACFG_D5R_SHIFT) | \
1462
                          (0 << HPC3_DMACFG_D3W_SHIFT) | \
1463
                          (2 << HPC3_DMACFG_D4W_SHIFT) | \
1464
                          (2 << HPC3_DMACFG_D5W_SHIFT) | \
1465
                                HPC3_DMACFG_DS16 | \
1466
                                HPC3_DMACFG_EVENHI | \
1467
                                HPC3_DMACFG_RTIME | \
1468
                          (8 << HPC3_DMACFG_BURST_SHIFT) | \
1469
                                HPC3_DMACFG_DRQLIVE)
1470
        /*
1471
         * Ignore what's mentioned in the specification and write value which
1472
         * works in The Real World (TM)
1473
         */
1474
        hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
1475
        hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
1476
 
1477
        if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, SA_SHIRQ,
1478
                        hal2str, hal2)) {
1479
                printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
1480
                ret = -EAGAIN;
1481
                goto free_card;
1482
        }
1483
 
1484
        hal2->dev_dsp = register_sound_dsp(&hal2_audio_fops, -1);
1485
        if (hal2->dev_dsp < 0) {
1486
                ret = hal2->dev_dsp;
1487
                goto free_irq;
1488
        }
1489
 
1490
        hal2->dev_mixer = register_sound_mixer(&hal2_mixer_fops, -1);
1491
        if (hal2->dev_mixer < 0) {
1492
                ret = hal2->dev_mixer;
1493
                goto unregister_dsp;
1494
        }
1495
 
1496
        hal2_init_mixer(hal2);
1497
 
1498
        *phal2 = hal2;
1499
        return 0;
1500
unregister_dsp:
1501
        unregister_sound_dsp(hal2->dev_dsp);
1502
free_irq:
1503
        free_irq(SGI_HPCDMA_IRQ, hal2);
1504
free_card:
1505
        kfree(hal2);
1506
 
1507
        return ret;
1508
}
1509
 
1510
extern void (*indy_volume_button)(int);
1511
 
1512
/*
1513
 * Assuming only one HAL2 card. Mail me if you ever meet machine with
1514
 * more than one.
1515
 */
1516
static int __init init_hal2(void)
1517
{
1518
        int i, error;
1519
 
1520
        for (i = 0; i < MAXCARDS; i++)
1521
                hal2_card[i] = NULL;
1522
 
1523
        error = hal2_init_card(&hal2_card[0], hpc3c0);
1524
 
1525
        /* let Indy's volume buttons work */
1526
        if (!error && !ip22_is_fullhouse())
1527
                indy_volume_button = hal2_volume_control;
1528
 
1529
        return error;
1530
 
1531
}
1532
 
1533
static void __exit exit_hal2(void)
1534
{
1535
        int i;
1536
 
1537
        /* unregister volume butons callback function */
1538
        indy_volume_button = NULL;
1539
 
1540
        for (i = 0; i < MAXCARDS; i++)
1541
                if (hal2_card[i]) {
1542
                        free_irq(SGI_HPCDMA_IRQ, hal2_card[i]);
1543
                        unregister_sound_dsp(hal2_card[i]->dev_dsp);
1544
                        unregister_sound_mixer(hal2_card[i]->dev_mixer);
1545
                        kfree(hal2_card[i]);
1546
        }
1547
}
1548
 
1549
module_init(init_hal2);
1550
module_exit(exit_hal2);
1551
 
1552
MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio");
1553
MODULE_AUTHOR("Ladislav Michl");
1554
MODULE_LICENSE("GPL");

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