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1275 |
phoenix |
#ifndef __TRID4DWAVE_H
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#define __TRID4DWAVE_H
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/*
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* audio@tridentmicro.com
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* Fri Feb 19 15:55:28 MST 1999
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* Definitions for Trident 4DWave DX/NX chips
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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/* PCI vendor and device ID */
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#ifndef PCI_VENDOR_ID_TRIDENT
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#define PCI_VENDOR_ID_TRIDENT 0x1023
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#endif
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#ifndef PCI_VENDOR_ID_SI
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#define PCI_VENDOR_ID_SI 0x1039
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#endif
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#ifndef PCI_VENDOR_ID_ALI
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#define PCI_VENDOR_ID_ALI 0x10b9
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#endif
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#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
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#endif
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#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
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#endif
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#ifndef PCI_DEVICE_ID_SI_7018
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#define PCI_DEVICE_ID_SI_7018 0x7018
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#endif
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#ifndef PCI_DEVICE_ID_ALI_5451
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#define PCI_DEVICE_ID_ALI_5451 0x5451
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#endif
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#ifndef PCI_DEVICE_ID_ALI_1533
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#define PCI_DEVICE_ID_ALI_1533 0x1533
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#endif
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#ifndef FALSE
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#define FALSE 0
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#define TRUE 1
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#endif
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#define CHANNEL_REGS 5
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#define CHANNEL_START 0xe0 // The first bytes of the contiguous register space.
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#define BANK_A 0
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#define BANK_B 1
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#define NR_BANKS 2
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#define TRIDENT_FMT_STEREO 0x01
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#define TRIDENT_FMT_16BIT 0x02
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#define TRIDENT_FMT_MASK 0x03
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#define DAC_RUNNING 0x01
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#define ADC_RUNNING 0x02
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/* Register Addresses */
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/* operational registers common to DX, NX, 7018 */
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enum trident_op_registers {
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T4D_REC_CH = 0x70,
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T4D_START_A = 0x80, T4D_STOP_A = 0x84,
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T4D_DLY_A = 0x88, T4D_SIGN_CSO_A = 0x8c,
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T4D_CSPF_A = 0x90, T4D_CEBC_A = 0x94,
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T4D_AINT_A = 0x98, T4D_EINT_A = 0x9c,
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T4D_LFO_GC_CIR = 0xa0, T4D_AINTEN_A = 0xa4,
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T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
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T4D_MISCINT = 0xb0, T4D_START_B = 0xb4,
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T4D_STOP_B = 0xb8, T4D_CSPF_B = 0xbc,
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T4D_SBBL_SBCL = 0xc0, T4D_SBCTRL_SBE2R_SBDD = 0xc4,
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T4D_STIMER = 0xc8, T4D_LFO_B_I2S_DELTA = 0xcc,
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T4D_AINT_B = 0xd8, T4D_AINTEN_B = 0xdc,
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ALI_MPUR2 = 0x22, ALI_GPIO = 0x7c,
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ALI_EBUF1 = 0xf4,
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ALI_EBUF2 = 0xf8
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};
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enum ali_op_registers {
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ALI_SCTRL = 0x48,
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ALI_GLOBAL_CONTROL = 0xd4,
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ALI_STIMER = 0xc8,
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ALI_SPDIF_CS = 0x70,
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ALI_SPDIF_CTRL = 0x74
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};
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enum ali_registers_number {
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ALI_GLOBAL_REGS = 56,
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ALI_CHANNEL_REGS = 8,
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ALI_MIXER_REGS = 20
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};
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enum ali_sctrl_control_bit {
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ALI_SPDIF_OUT_ENABLE = 0x20
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};
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enum ali_global_control_bit {
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ALI_SPDIF_OUT_SEL_PCM = 0x00000400,
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ALI_SPDIF_IN_SUPPORT = 0x00000800,
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ALI_SPDIF_OUT_CH_ENABLE = 0x00008000,
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ALI_SPDIF_IN_CH_ENABLE = 0x00080000,
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ALI_PCM_IN_DISABLE = 0x7fffffff,
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ALI_PCM_IN_ENABLE = 0x80000000,
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ALI_SPDIF_IN_CH_DISABLE = 0xfff7ffff,
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ALI_SPDIF_OUT_CH_DISABLE = 0xffff7fff,
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ALI_SPDIF_OUT_SEL_SPDIF = 0xfffffbff
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};
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enum ali_spdif_control_bit {
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ALI_SPDIF_IN_FUNC_ENABLE = 0x02,
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ALI_SPDIF_IN_CH_STATUS = 0x40,
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ALI_SPDIF_OUT_CH_STATUS = 0xbf
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};
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enum ali_control_all {
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ALI_DISABLE_ALL_IRQ = 0,
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ALI_CHANNELS = 32,
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ALI_STOP_ALL_CHANNELS = 0xffffffff,
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ALI_MULTI_CHANNELS_START_STOP = 0x07800000
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};
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enum ali_EMOD_control_bit {
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ALI_EMOD_DEC = 0x00000000,
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ALI_EMOD_INC = 0x10000000,
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ALI_EMOD_Delay = 0x20000000,
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ALI_EMOD_Still = 0x30000000
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};
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enum ali_pcm_in_channel_num {
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ALI_NORMAL_CHANNEL = 0,
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ALI_SPDIF_OUT_CHANNEL = 15,
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ALI_SPDIF_IN_CHANNEL = 19,
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ALI_LEF_CHANNEL = 23,
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ALI_CENTER_CHANNEL = 24,
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ALI_SURR_RIGHT_CHANNEL = 25,
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ALI_SURR_LEFT_CHANNEL = 26,
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ALI_PCM_IN_CHANNEL = 31
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};
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enum ali_pcm_out_channel_num {
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ALI_PCM_OUT_CHANNEL_FIRST = 0,
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ALI_PCM_OUT_CHANNEL_LAST = 31
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};
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enum ali_ac97_power_control_bit {
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ALI_EAPD_POWER_DOWN = 0x8000
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};
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enum ali_update_ptr_flags {
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ALI_ADDRESS_INT_UPDATE = 0x01
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};
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enum ali_revision {
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ALI_5451_V02 = 0x02
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};
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enum ali_spdif_out_control {
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ALI_PCM_TO_SPDIF_OUT = 0,
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ALI_SPDIF_OUT_TO_SPDIF_OUT = 1,
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ALI_SPDIF_OUT_PCM = 0,
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ALI_SPDIF_OUT_NON_PCM = 2
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};
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/* S/PDIF Operational Registers for 4D-NX */
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enum nx_spdif_registers {
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NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
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NX_SPESO = 0x2c, NX_SPCSTATUS = 0x64
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};
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/* OP registers to access each hardware channel */
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enum channel_registers {
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CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
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CH_DX_FMC_RVOL_CVOL = 0xec,
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CH_NX_DELTA_CSO = 0xe0, CH_NX_DELTA_ESO = 0xe8,
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CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
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CH_LBA = 0xe4,
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CH_GVSEL_PAN_VOL_CTRL_EC = 0xf0
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};
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/* registers to read/write/control AC97 codec */
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enum dx_ac97_registers {
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DX_ACR0_AC97_W = 0x40, DX_ACR1_AC97_R = 0x44,
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DX_ACR2_AC97_COM_STAT = 0x48
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};
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enum nx_ac97_registers {
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NX_ACR0_AC97_COM_STAT = 0x40, NX_ACR1_AC97_W = 0x44,
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NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
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};
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enum si_ac97_registers {
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SI_AC97_WRITE = 0x40, SI_AC97_READ = 0x44,
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SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
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};
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enum ali_ac97_registers {
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ALI_AC97_WRITE = 0x40, ALI_AC97_READ = 0x44
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};
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/* Bit mask for operational registers */
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#define AC97_REG_ADDR 0x000000ff
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enum ali_ac97_bits {
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ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
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ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
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ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY = 0x0080,
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ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
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ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
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};
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enum sis7018_ac97_bits {
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SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
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SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
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SI_AC97_SECONDARY = 0x0080
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};
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enum trident_dx_ac97_bits {
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DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
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DX_AC97_READY = 0x0010, DX_AC97_RECORD = 0x0008,
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DX_AC97_PLAYBACK = 0x0002
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};
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enum trident_nx_ac97_bits {
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/* ACR1-3 */
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NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
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| 248 |
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NX_AC97_BUSY_DATA = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
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| 249 |
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/* ACR0 */
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NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
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| 251 |
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NX_AC97_SURROUND_OUTPUT = 0x0010,
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NX_AC97_PRIMARY_READY = 0x0008, NX_AC97_PRIMARY_RECORD = 0x0004,
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| 253 |
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NX_AC97_PCM_OUTPUT = 0x0002,
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| 254 |
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NX_AC97_WARM_RESET = 0x0001
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| 255 |
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};
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| 256 |
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| 257 |
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enum serial_intf_ctrl_bits {
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WARM_REST = 0x00000001, COLD_RESET = 0x00000002,
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| 259 |
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I2S_CLOCK = 0x00000004, PCM_SEC_AC97= 0x00000008,
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| 260 |
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AC97_DBL_RATE = 0x00000010, SPDIF_EN = 0x00000020,
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| 261 |
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I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
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| 262 |
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PCMIN = 0x00000100, LINE1IN = 0x00000200,
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| 263 |
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MICIN = 0x00000400, LINE2IN = 0x00000800,
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| 264 |
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HEAD_SET_IN = 0x00001000, GPIOIN = 0x00002000,
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| 265 |
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/* 7018 spec says id = 01 but the demo board routed to 10
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| 266 |
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SECONDARY_ID= 0x00004000, */
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| 267 |
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SECONDARY_ID= 0x00004000,
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| 268 |
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PCMOUT = 0x00010000, SURROUT = 0x00020000,
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| 269 |
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CENTEROUT = 0x00040000, LFEOUT = 0x00080000,
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| 270 |
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LINE1OUT = 0x00100000, LINE2OUT = 0x00200000,
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| 271 |
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GPIOOUT = 0x00400000,
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| 272 |
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SI_AC97_PRIMARY_READY = 0x01000000,
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| 273 |
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SI_AC97_SECONDARY_READY = 0x02000000,
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| 274 |
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};
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| 275 |
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| 276 |
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enum global_control_bits {
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| 277 |
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CHANNLE_IDX = 0x0000003f, PB_RESET = 0x00000100,
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| 278 |
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PAUSE_ENG = 0x00000200,
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| 279 |
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OVERRUN_IE = 0x00000400, UNDERRUN_IE = 0x00000800,
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| 280 |
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ENDLP_IE = 0x00001000, MIDLP_IE = 0x00002000,
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| 281 |
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ETOG_IE = 0x00004000,
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| 282 |
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EDROP_IE = 0x00008000, BANK_B_EN = 0x00010000
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| 283 |
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};
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| 284 |
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| 285 |
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enum channel_control_bits {
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| 286 |
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CHANNEL_LOOP = 0x00001000, CHANNEL_SIGNED = 0x00002000,
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| 287 |
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CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
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| 288 |
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};
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| 289 |
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| 290 |
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enum channel_attribute {
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| 291 |
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/* playback/record select */
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| 292 |
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CHANNEL_PB = 0x0000, CHANNEL_SPC_PB = 0x4000,
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| 293 |
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CHANNEL_REC = 0x8000, CHANNEL_REC_PB = 0xc000,
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| 294 |
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/* playback destination/record source select */
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| 295 |
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MODEM_LINE1 = 0x0000, MODEM_LINE2 = 0x0400,
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| 296 |
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PCM_LR = 0x0800, HSET = 0x0c00,
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| 297 |
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I2S_LR = 0x1000, CENTER_LFE = 0x1400,
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| 298 |
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SURR_LR = 0x1800, SPDIF_LR = 0x1c00,
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| 299 |
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MIC = 0x1400,
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| 300 |
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/* mist stuff */
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| 301 |
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MONO_LEFT = 0x0000, MONO_RIGHT = 0x0100,
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| 302 |
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MONO_MIX = 0x0200, SRC_ENABLE = 0x0080,
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| 303 |
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};
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| 304 |
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| 305 |
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enum miscint_bits {
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| 306 |
|
|
PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
|
| 307 |
|
|
SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
|
| 308 |
|
|
OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
|
| 309 |
|
|
ENVELOPE_IRQ = 0x00000040, ST_IRQ = 0x00000080,
|
| 310 |
|
|
PB_UNDERRUN = 0x00000100, REC_OVERRUN = 0x00000200,
|
| 311 |
|
|
MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW = 0x00000800,
|
| 312 |
|
|
ST_TARGET_REACHED = 0x00008000, PB_24K_MODE = 0x00010000,
|
| 313 |
|
|
ST_IRQ_EN = 0x00800000, ACGPIO_IRQ = 0x01000000
|
| 314 |
|
|
};
|
| 315 |
|
|
|
| 316 |
|
|
#define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
|
| 317 |
|
|
|
| 318 |
|
|
#define CYBER_PORT_AUDIO 0x3CE
|
| 319 |
|
|
#define CYBER_IDX_AUDIO_ENABLE 0x7B
|
| 320 |
|
|
#define CYBER_BMSK_AUDIO_INT_ENABLE 0x09
|
| 321 |
|
|
#define CYBER_BMSK_AUENZ 0x01
|
| 322 |
|
|
#define CYBER_BMSK_AUENZ_ENABLE 0x00
|
| 323 |
|
|
#define CYBER_IDX_IRQ_ENABLE 0x12
|
| 324 |
|
|
|
| 325 |
|
|
#define VALIDATE_MAGIC(FOO,MAG) \
|
| 326 |
|
|
({ \
|
| 327 |
|
|
if (!(FOO) || (FOO)->magic != MAG) { \
|
| 328 |
|
|
printk(invalid_magic,__FUNCTION__); \
|
| 329 |
|
|
return -ENXIO; \
|
| 330 |
|
|
} \
|
| 331 |
|
|
})
|
| 332 |
|
|
|
| 333 |
|
|
#define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
|
| 334 |
|
|
#define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
|
| 335 |
|
|
|
| 336 |
|
|
static inline unsigned ld2(unsigned int x)
|
| 337 |
|
|
{
|
| 338 |
|
|
unsigned r = 0;
|
| 339 |
|
|
|
| 340 |
|
|
if (x >= 0x10000) {
|
| 341 |
|
|
x >>= 16;
|
| 342 |
|
|
r += 16;
|
| 343 |
|
|
}
|
| 344 |
|
|
if (x >= 0x100) {
|
| 345 |
|
|
x >>= 8;
|
| 346 |
|
|
r += 8;
|
| 347 |
|
|
}
|
| 348 |
|
|
if (x >= 0x10) {
|
| 349 |
|
|
x >>= 4;
|
| 350 |
|
|
r += 4;
|
| 351 |
|
|
}
|
| 352 |
|
|
if (x >= 4) {
|
| 353 |
|
|
x >>= 2;
|
| 354 |
|
|
r += 2;
|
| 355 |
|
|
}
|
| 356 |
|
|
if (x >= 2)
|
| 357 |
|
|
r++;
|
| 358 |
|
|
return r;
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
#ifdef DEBUG
|
| 362 |
|
|
|
| 363 |
|
|
#define TRDBG(msg, args...) do { \
|
| 364 |
|
|
printk(KERN_DEBUG msg , ##args ); \
|
| 365 |
|
|
} while (0)
|
| 366 |
|
|
|
| 367 |
|
|
#else /* !defined(DEBUG) */
|
| 368 |
|
|
|
| 369 |
|
|
#define TRDBG(msg, args...) do { } while (0)
|
| 370 |
|
|
|
| 371 |
|
|
#endif /* DEBUG */
|
| 372 |
|
|
|
| 373 |
|
|
#endif /* __TRID4DWAVE_H */
|
