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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [video/] [au1100fb.h] - Blame information for rev 1780

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1 1275 phoenix 
/*
2 
 * BRIEF MODULE DESCRIPTION
3 
 *      Hardware definitions for the Au1100 LCD controller
4 
 *
5 
 * Copyright 2002 MontaVista Software
6 
 * Copyright 2002 Alchemy Semiconductor
7 
 * Author:      Alchemy Semiconductor, MontaVista Software
8 
 *
9 
 *  This program is free software; you can redistribute  it and/or modify it
10 
 *  under  the terms of  the GNU General  Public License as published by the
11 
 *  Free Software Foundation;  either version 2 of the  License, or (at your
12 
 *  option) any later version.
13 
 *
14 
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
15 
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
16 
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
17 
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
18 
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
20 
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
22 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 
 *
25 
 *  You should have received a copy of the  GNU General Public License along
26 
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
27 
 *  675 Mass Ave, Cambridge, MA 02139, USA.
28 
 */
29 
 
30 
#ifndef _AU1100LCD_H
31 
#define _AU1100LCD_H
32 
 
33 
/********************************************************************/
34 
#define uint32 unsigned long
35 
typedef volatile struct
36 
{
37 
        uint32  lcd_control;
38 
        uint32  lcd_intstatus;
39 
        uint32  lcd_intenable;
40 
        uint32  lcd_horztiming;
41 
        uint32  lcd_verttiming;
42 
        uint32  lcd_clkcontrol;
43 
        uint32  lcd_dmaaddr0;
44 
        uint32  lcd_dmaaddr1;
45 
        uint32  lcd_words;
46 
        uint32  lcd_pwmdiv;
47 
        uint32  lcd_pwmhi;
48 
        uint32  reserved[(0x0400-0x002C)/4];
49 
        uint32  lcd_pallettebase[256];
50 
 
51 
} AU1100_LCD;
52 
 
53 
/********************************************************************/
54 
 
55 
#define AU1100_LCD_ADDR         0xB5000000
56 
 
57 
/*
58 
 * Register bit definitions
59 
 */
60 
 
61 
/* lcd_control */
62 
#define LCD_CONTROL_SBPPF               (7<<18)
63 
#define LCD_CONTROL_SBPPF_655   (0<<18)
64 
#define LCD_CONTROL_SBPPF_565   (1<<18)
65 
#define LCD_CONTROL_SBPPF_556   (2<<18)
66 
#define LCD_CONTROL_SBPPF_1555  (3<<18)
67 
#define LCD_CONTROL_SBPPF_5551  (4<<18)
68 
#define LCD_CONTROL_WP                  (1<<17)
69 
#define LCD_CONTROL_WD                  (1<<16)
70 
#define LCD_CONTROL_C                   (1<<15)
71 
#define LCD_CONTROL_SM                  (3<<13)
72 
#define LCD_CONTROL_SM_0                (0<<13)
73 
#define LCD_CONTROL_SM_90               (1<<13)
74 
#define LCD_CONTROL_SM_180              (2<<13)
75 
#define LCD_CONTROL_SM_270              (3<<13)
76 
#define LCD_CONTROL_DB                  (1<<12)
77 
#define LCD_CONTROL_CCO                 (1<<11)
78 
#define LCD_CONTROL_DP                  (1<<10)
79 
#define LCD_CONTROL_PO                  (3<<8)
80 
#define LCD_CONTROL_PO_00               (0<<8)
81 
#define LCD_CONTROL_PO_01               (1<<8)
82 
#define LCD_CONTROL_PO_10               (2<<8)
83 
#define LCD_CONTROL_PO_11               (3<<8)
84 
#define LCD_CONTROL_MPI                 (1<<7)
85 
#define LCD_CONTROL_PT                  (1<<6)
86 
#define LCD_CONTROL_PC                  (1<<5)
87 
#define LCD_CONTROL_BPP                 (7<<1)
88 
#define LCD_CONTROL_BPP_1               (0<<1)
89 
#define LCD_CONTROL_BPP_2               (1<<1)
90 
#define LCD_CONTROL_BPP_4               (2<<1)
91 
#define LCD_CONTROL_BPP_8               (3<<1)
92 
#define LCD_CONTROL_BPP_12              (4<<1)
93 
#define LCD_CONTROL_BPP_16              (5<<1)
94 
#define LCD_CONTROL_GO                  (1<<0)
95 
 
96 
/* lcd_intstatus, lcd_intenable */
97 
#define LCD_INT_SD                              (1<<7)
98 
#define LCD_INT_OF                              (1<<6)
99 
#define LCD_INT_UF                              (1<<5)
100 
#define LCD_INT_SA                              (1<<3)
101 
#define LCD_INT_SS                              (1<<2)
102 
#define LCD_INT_S1                              (1<<1)
103 
#define LCD_INT_S0                              (1<<0)
104 
 
105 
/* lcd_horztiming */
106 
#define LCD_HORZTIMING_HN2              (255<<24)
107 
#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
108 
#define LCD_HORZTIMING_HN1              (255<<16)
109 
#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
110 
#define LCD_HORZTIMING_HPW              (63<<10)
111 
#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
112 
#define LCD_HORZTIMING_PPL              (1023<<0)
113 
#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
114 
 
115 
/* lcd_verttiming */
116 
#define LCD_VERTTIMING_VN2              (255<<24)
117 
#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
118 
#define LCD_VERTTIMING_VN1              (255<<16)
119 
#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
120 
#define LCD_VERTTIMING_VPW              (63<<10)
121 
#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
122 
#define LCD_VERTTIMING_LPP              (1023<<0)
123 
#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
124 
 
125 
/* lcd_clkcontrol */
126 
#define LCD_CLKCONTROL_IB               (1<<18)
127 
#define LCD_CLKCONTROL_IC               (1<<17)
128 
#define LCD_CLKCONTROL_IH               (1<<16)
129 
#define LCD_CLKCONTROL_IV               (1<<15)
130 
#define LCD_CLKCONTROL_BF               (31<<10)
131 
#define LCD_CLKCONTROL_BF_N(N)  (((N)-1)<<10)
132 
#define LCD_CLKCONTROL_PCD              (1023<<0)
133 
#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
134 
 
135 
/* lcd_pwmdiv */
136 
#define LCD_PWMDIV_EN                   (1<<12)
137 
#define LCD_PWMDIV_PWMDIV               (2047<<0)
138 
#define LCD_PWMDIV_PWMDIV_N(N)  (((N)-1)<<0)
139 
 
140 
/* lcd_pwmhi */
141 
#define LCD_PWMHI_PWMHI1                (2047<<12)
142 
#define LCD_PWMHI_PWMHI1_N(N)   ((N)<<12)
143 
#define LCD_PWMHI_PWMHI0                (2047<<0)
144 
#define LCD_PWMHI_PWMHI0_N(N)   ((N)<<0)
145 
 
146 
/* lcd_pallettebase - MONOCHROME */
147 
#define LCD_PALLETTE_MONO_MI            (15<<0)
148 
#define LCD_PALLETTE_MONO_MI_N(N)       ((N)<<0)
149 
 
150 
/* lcd_pallettebase - COLOR */
151 
#define LCD_PALLETTE_COLOR_BI           (15<<8)
152 
#define LCD_PALLETTE_COLOR_BI_N(N)      ((N)<<8)
153 
#define LCD_PALLETTE_COLOR_GI           (15<<4)
154 
#define LCD_PALLETTE_COLOR_GI_N(N)      ((N)<<4)
155 
#define LCD_PALLETTE_COLOR_RI           (15<<0)
156 
#define LCD_PALLETTE_COLOR_RI_N(N)      ((N)<<0)
157 
 
158 
/* lcd_palletebase - COLOR TFT PALLETIZED */
159 
#define LCD_PALLETTE_TFT_DC                     (65535<<0)
160 
#define LCD_PALLETTE_TFT_DC_N(N)        ((N)<<0)
161 
 
162 
/********************************************************************/
163 
 
164 
struct known_lcd_panels
165 
{
166 
        uint32 xres;
167 
        uint32 yres;
168 
        uint32 bpp;
169 
        unsigned char  panel_name[256];
170 
        uint32 mode_control;
171 
        uint32 mode_horztiming;
172 
        uint32 mode_verttiming;
173 
        uint32 mode_clkcontrol;
174 
        uint32 mode_pwmdiv;
175 
        uint32 mode_pwmhi;
176 
        uint32 mode_toyclksrc;
177 
        uint32 mode_backlight;
178 
 
179 
};
180 
 
181 
#if defined(__BIG_ENDIAN)
182 
#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
183 
#else
184 
#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
185 
#endif
186 
 
187 
/*
188 
 * The fb driver assumes that AUX PLL is at 48MHz.  That can
189 
 * cover up to 800x600 resolution; if you need higher resolution,
190 
 * you should modify the driver as needed, not just this structure.
191 
 */
192 
struct known_lcd_panels panels[] =
193 
{
194 
        { /* 0: Pb1100 LCDA: Sharp 320x240x16bpp TFT panel, no rotate */
195 
                320, /* xres */
196 
                240, /* yres */
197 
                16,  /* bpp  */
198 
 
199 
                "Sharp_320x240_16",
200 
                /* mode_control */
201 
                ( LCD_CONTROL_SBPPF_565
202 
                /*LCD_CONTROL_WP*/
203 
                /*LCD_CONTROL_WD*/
204 
                | LCD_CONTROL_C
205 
                | LCD_CONTROL_SM_0
206 
                /*LCD_CONTROL_DB*/
207 
                /*LCD_CONTROL_CCO*/
208 
                /*LCD_CONTROL_DP*/
209 
                | LCD_CONTROL_PO_00
210 
                /*LCD_CONTROL_MPI*/
211 
                | LCD_CONTROL_PT
212 
                | LCD_CONTROL_PC
213 
                | LCD_CONTROL_BPP_16 ),
214 
 
215 
                /* mode_horztiming */
216 
                ( LCD_HORZTIMING_HN2_N(8)
217 
                | LCD_HORZTIMING_HN1_N(60)
218 
                | LCD_HORZTIMING_HPW_N(12)
219 
                | LCD_HORZTIMING_PPL_N(320) ),
220 
 
221 
                /* mode_verttiming */
222 
                ( LCD_VERTTIMING_VN2_N(5)
223 
                | LCD_VERTTIMING_VN1_N(17)
224 
                | LCD_VERTTIMING_VPW_N(1)
225 
                | LCD_VERTTIMING_LPP_N(240) ),
226 
 
227 
                /* mode_clkcontrol */
228 
                ( 0
229 
                /*LCD_CLKCONTROL_IB*/
230 
                /*LCD_CLKCONTROL_IC*/
231 
                /*LCD_CLKCONTROL_IH*/
232 
                /*LCD_CLKCONTROL_IV*/
233 
                | LCD_CLKCONTROL_PCD_N(1) ),
234 
 
235 
                /* mode_pwmdiv */
236 
                0,
237 
 
238 
                /* mode_pwmhi */
239 
                0,
240 
 
241 
                /* mode_toyclksrc */
242 
                ((1<<7) | (1<<6) | (1<<5)),
243 
 
244 
                /* mode_backlight */
245 
                6
246 
        },
247 
 
248 
        { /* 1: Pb1100 LCDA: Sharp 320x240x16bpp TFT panel, rotated */
249 
                240, /* xres */
250 
                320, /* yres */
251 
                16,  /* bpp  */
252 
 
253 
                "Sharp_320x240_16",
254 
                /* mode_control */
255 
                ( LCD_CONTROL_SBPPF_565
256 
                /*LCD_CONTROL_WP*/
257 
                /*LCD_CONTROL_WD*/
258 
                | LCD_CONTROL_C
259 
                | LCD_CONTROL_SM_0
260 
                /*LCD_CONTROL_DB*/
261 
                /*LCD_CONTROL_CCO*/
262 
                /*LCD_CONTROL_DP*/
263 
                | LCD_DEFAULT_PIX_FORMAT
264 
                /*LCD_CONTROL_MPI*/
265 
                | LCD_CONTROL_PT
266 
                | LCD_CONTROL_PC
267 
                | LCD_CONTROL_BPP_16 ),
268 
 
269 
                /* mode_horztiming */
270 
                ( LCD_HORZTIMING_HN2_N(8)
271 
                | LCD_HORZTIMING_HN1_N(60)
272 
                | LCD_HORZTIMING_HPW_N(12)
273 
                | LCD_HORZTIMING_PPL_N(320) ),
274 
 
275 
                /* mode_verttiming */
276 
                ( LCD_VERTTIMING_VN2_N(5)
277 
                | LCD_VERTTIMING_VN1_N(17)
278 
                | LCD_VERTTIMING_VPW_N(1)
279 
                | LCD_VERTTIMING_LPP_N(240) ),
280 
 
281 
                /* mode_clkcontrol */
282 
                ( 0
283 
                /*LCD_CLKCONTROL_IB*/
284 
                /*LCD_CLKCONTROL_IC*/
285 
                /*LCD_CLKCONTROL_IH*/
286 
                /*LCD_CLKCONTROL_IV*/
287 
                | LCD_CLKCONTROL_PCD_N(1) ),
288 
 
289 
                /* mode_pwmdiv */
290 
                0,
291 
 
292 
                /* mode_pwmhi */
293 
                0,
294 
 
295 
                /* mode_toyclksrc */
296 
                ((1<<7) | (1<<6) | (1<<5)),
297 
 
298 
                /* mode_backlight */
299 
                6
300 
        },
301 
 
302 
        { /* 2: Pb1100 LCDB 640x480x16bpp PrimeView TFT panel */
303 
                640, /* xres */
304 
                480, /* yres */
305 
                16,  /* bpp  */
306 
 
307 
                "Primeview_640x480_16",
308 
 
309 
                /* mode_control */
310 
                0x0004886a,
311 
 
312 
                /* mode_horztiming */
313 
                0x0e4bfe7f,
314 
 
315 
                /* mode_verttiming */
316 
                0x210805df,
317 
 
318 
                /* mode_clkcontrol */
319 
                0x00038001,
320 
 
321 
                /* mode_pwmdiv */
322 
                0,
323 
 
324 
                /* mode_pwmhi */
325 
                0,
326 
 
327 
                /* mode_toyclksrc */
328 
                ((1<<7) | (1<<6) | (0<<5)),
329 
 
330 
                /* mode_backlight */
331 
                7
332 
        },
333 
 
334 
        { /* 3: Pb1100 LCDC 640x480x16bpp TFT panel */
335 
                640, /* xres */
336 
                480, /* yres */
337 
                16,  /* bpp  */
338 
 
339 
                "Generic_640x480_16",
340 
 
341 
                /* mode_control */
342 
#ifdef CONFIG_MIPS_HYD1100
343 
                0x0004c15a,
344 
#else
345 
                0x004806a | LCD_DEFAULT_PIX_FORMAT,
346 
#endif
347 
 
348 
                /* mode_horztiming */
349 
                0x3434d67f,
350 
 
351 
                /* mode_verttiming */
352 
                0x0e0e39df,
353 
 
354 
                /* mode_clkcontrol */
355 
                ( 0
356 
                /*LCD_CLKCONTROL_IB*/
357 
                /*LCD_CLKCONTROL_IC*/
358 
                /*LCD_CLKCONTROL_IH*/
359 
                /*LCD_CLKCONTROL_IV*/
360 
                | LCD_CLKCONTROL_PCD_N(1) ),
361 
 
362 
                /* mode_pwmdiv */
363 
                0,
364 
 
365 
                /* mode_pwmhi */
366 
                0,
367 
 
368 
                /* mode_toyclksrc */
369 
                ((1<<7) | (1<<6) | (0<<5)),
370 
 
371 
                /* mode_backlight */
372 
                7
373 
        },
374 
 
375 
        { // 4: Pb1100 NEON: 640x480x16bpp CRT, HOG, Hsync 30.7 kHz, Vsync 57.7 Hz
376 
                640, /* xres */
377 
                480, /* yres */
378 
                16,  /* bpp */
379 
 
380 
                "NEON_640x480_16",
381 
 
382 
                /* mode_control */
383 
                0x0004886a | LCD_DEFAULT_PIX_FORMAT,
384 
 
385 
                // mode_horztiming
386 
                // 15 pixels front porch
387 
                // 76 pixels back porch
388 
                // 64 pixels sync pulse
389 
                0x1e3bfe7f,
390 
 
391 
                // mode_verttiming
392 
                // 34 lines front porch
393 
                // 9 lines back porch
394 
                // 2 lines sync pulse
395 
                0x210805df,
396 
 
397 
                /* mode_clkcontrol */
398 
                // div to 24 MHz
399 
                0x00020001,
400 
 
401 
                /* mode_pwmdiv */
402 
                0,
403 
 
404 
                /* mode_pwmhi */
405 
                0,
406 
 
407 
                /* mode_toyclksrc */
408 
                // use 48 MHz clock
409 
                ((1<<7) | (1<<6) | (0<<5)),
410 
 
411 
                /* mode_backlight */
412 
                7
413 
        },
414 
 
415 
        { //5: Pb1100 NEON: 800x600x16bpp CRT, HOG, Hsync 45.7 kHz, Vsync 68.7 Hz
416 
                800, /* xres */
417 
                600, /* yres */
418 
                16,  /* bpp */
419 
 
420 
                "NEON_800x600_16",
421 
 
422 
                /* mode_control */
423 
                0x0004886A | LCD_DEFAULT_PIX_FORMAT,
424 
 
425 
                // mode_horztiming
426 
                // 32 pixels front porch
427 
                // 152 pixels back porch
428 
                // 64 pixels sync pulse
429 
                0x1F97FF1F,
430 
 
431 
                // mode_verttiming
432 
                // 37 lines front porch
433 
                // 23 lines back porch
434 
                // 6 lines sync pulse
435 
                0x24161A57,
436 
 
437 
                /* mode_clkcontrol */
438 
                // keep at 47 MHz
439 
                0x00020000,
440 
 
441 
                /* mode_pwmdiv */
442 
                0,
443 
 
444 
                /* mode_pwmhi */
445 
                0,
446 
 
447 
                /* mode_toyclksrc */
448 
                // use 48 MHz clock
449 
                ((1<<7) | (1<<6) | (0<<5)),
450 
 
451 
                /* mode_backlight */
452 
                7
453 
        },
454 
 
455 
        { //6: Pb1100 NEON: 800x600x16bpp CRT, HOG, Hsync 45.7 kHz, Vsync 68.7 Hz
456 
                640, /* xres */
457 
                480, /* yres */
458 
                16,  /* bpp */
459 
 
460 
                "NEON_640x480_16",
461 
 
462 
                /* mode_control */
463 
                0x0004886A | LCD_DEFAULT_PIX_FORMAT,
464 
 
465 
                // mode_horztiming
466 
                // 32 pixels front porch
467 
                // 152 pixels back porch
468 
                // 64 pixels sync pulse
469 
                0x1F97FF1F,
470 
 
471 
                // mode_verttiming
472 
                // 37 lines front porch
473 
                // 23 lines back porch
474 
                // 6 lines sync pulse
475 
                0x24161A57,
476 
 
477 
                /* mode_clkcontrol */
478 
                // keep at 47 MHz
479 
                0x00020000,
480 
 
481 
                /* mode_pwmdiv */
482 
                0,
483 
 
484 
                /* mode_pwmhi */
485 
                0,
486 
 
487 
                /* mode_toyclksrc */
488 
                // use 48 MHz clock
489 
                ((1<<7) | (1<<6) | (0<<5)),
490 
 
491 
                /* mode_backlight */
492 
                7
493 
        },
494 
 
495 
        { //7: Pb1100 NEON: 800x600x16bpp CRT, HOG, Hsync 45.7 kHz, Vsync 68.7 Hz
496 
                800, /* xres */
497 
                600, /* yres */
498 
                16,  /* bpp */
499 
 
500 
                "NEON_800x600_16",
501 
 
502 
 
503 
                /* mode_control */
504 
                0x0004886A,
505 
 
506 
                // mode_horztiming
507 
                // 32 pixels front porch
508 
                // 152 pixels back porch
509 
                // 64 pixels sync pulse
510 
                0x1F97FF1F,
511 
 
512 
                // mode_verttiming
513 
                // 37 lines front porch
514 
                // 23 lines back porch
515 
                // 6 lines sync pulse
516 
                0x24161A57,
517 
 
518 
                /* mode_clkcontrol */
519 
                // keep at 47 MHz
520 
                0x00020000,
521 
 
522 
                /* mode_pwmdiv */
523 
                0,
524 
 
525 
                /* mode_pwmhi */
526 
                0,
527 
 
528 
                /* mode_toyclksrc */
529 
                // use 48 MHz clock
530 
                ((1<<7) | (1<<6) | (0<<5)),
531 
 
532 
                /* mode_backlight */
533 
                7
534 
        },
535 
        { /* 8 */
536 
                320, /* xres */
537 
                240, /* yres */
538 
                16,  /* bpp */
539 
 
540 
                "Hydrogen_3_NEC_panel_320x240",
541 
                /* mode_control */
542 
                LCD_CONTROL_BPP_16 | LCD_CONTROL_PC | LCD_CONTROL_PT | LCD_CONTROL_PO_00 | LCD_CONTROL_SBPPF_565,
543 
                /* mode_horztiming */
544 
                LCD_HORZTIMING_HN2_N(8) | LCD_HORZTIMING_HN1_N(16) | LCD_HORZTIMING_HPW_N(24) | LCD_HORZTIMING_PPL_N(240),
545 
                /* mode_verttiming */
546 
                LCD_VERTTIMING_VN2_N(5) | LCD_VERTTIMING_VN1_N(5) | LCD_VERTTIMING_VPW_N(2) | LCD_VERTTIMING_LPP_N(320),
547 
                /* mode_clkcontrol */
548 
                LCD_CLKCONTROL_PCD_N(1),
549 
                /* mode_pwmdiv */
550 
                0,
551 
                /* mode_pwmhi */
552 
                0,
553 
                /* mode_toyclksrc */
554 
                ((1<<7) | (0<<6) | (1<<5)),
555 
                /* mode_backlight */
556 
                0,
557 
        },
558 
 
559 
 
560 
};
561 
#endif /* _AU1100LCD_H */

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