OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-arm/] [arch-anakin/] [hardware.h] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1276 phoenix
/*
2
 *  linux/include/asm-arm/arch-anakin/hardware.h
3
 *
4
 *  Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
5
 *
6
 * This program is free software; you can redistribute it and/or modify
7
 * it under the terms of the GNU General Public License version 2 as
8
 * published by the Free Software Foundation.
9
 *
10
 *  Changelog:
11
 *   10-Apr-2001 TTC    Created
12
 */
13
 
14
#ifndef __ASM_ARCH_HARDWARE_H
15
#define __ASM_ARCH_HARDWARE_H
16
 
17
/*
18
 * Memory map
19
 */
20
#define SRAM_START              0x00000000
21
#define SRAM_SIZE               0x00100000
22
#define SRAM_BASE               0xdf000000
23
 
24
#define SDRAM_START             0x20000000
25
#define SDRAM_SIZE              0x04000000
26
#define SDRAM_BASE              0xc0000000
27
 
28
#define IO_START                0x40000000
29
#define IO_SIZE                 0x00100000
30
#define IO_BASE                 0xe0000000
31
 
32
#define FLASH_START             0x60000000
33
#define FLASH_SIZE              0x00080000
34
#define FLASH_BASE              0xe8000000
35
 
36
#define VGA_START               0x80000000
37
#define VGA_SIZE                0x0002db40
38
#define VGA_BASE                0xf0000000
39
 
40
/*
41
 * IO map
42
 */
43
#define IO_CONTROLLER           0x00000
44
#define INTERRUPT_CONTROLLER    0x02000
45
#define UART0                   0x04000
46
#define UART1                   0x06000
47
#define UART2                   0x08000
48
#define CODEC                   0x0a000
49
#define UART4                   0x0c000
50
#define UART3                   0x0e000
51
#define DISPLAY_CONTROLLER      0x10000
52
#define DAB                     0x12000
53
#define STATE_CONTROLLER        0x14000
54
#define CAN                     0x23000
55
#define COMPACTFLASH            0x24000
56
 
57
/*
58
 * Use SRAM for D-cache flush
59
 */
60
#define FLUSH_BASE_PHYS         SRAM_START
61
#define FLUSH_BASE              SRAM_BASE
62
#define UNCACHEABLE_ADDR        (SRAM_BASE + 0x10000)
63
 
64
/*
65
 * Use SDRAM for memory
66
 */
67
#define MEM_SIZE                SDRAM_SIZE
68
 
69
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.