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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-arm/] [arch-at91rm9200/] [AT91RM9200_EMAC.h] - Blame information for rev 1765

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1 1276 phoenix 
// ----------------------------------------------------------------------------
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//          ATMEL Microcontroller Software Support  -  ROUSSET  -
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// ----------------------------------------------------------------------------
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//  The software is delivered "AS IS" without warranty or condition of any
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//  kind, either express, implied or statutory. This includes without
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//  limitation any warranty or condition with respect to merchantability or
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//  fitness for any particular purpose, or against the infringements of
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//  intellectual property rights of others.
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// ----------------------------------------------------------------------------
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// File Name           : AT91RM9200.h
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// Object              : AT91RM9200 / EMAC definitions
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// Generated           : AT91 SW Application Group  01/17/2003 (13:41:21)
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//
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// ----------------------------------------------------------------------------
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#ifndef AT91RM9200_EMAC_H
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#define AT91RM9200_EMAC_H
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// *****************************************************************************
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//              SOFTWARE API DEFINITION  FOR Ethernet MAC
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// *****************************************************************************
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#ifndef __ASSEMBLY__
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typedef struct _AT91S_EMAC {
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        AT91_REG         EMAC_CTL;      // Network Control Register
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        AT91_REG         EMAC_CFG;      // Network Configuration Register
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        AT91_REG         EMAC_SR;       // Network Status Register
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        AT91_REG         EMAC_TAR;      // Transmit Address Register
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        AT91_REG         EMAC_TCR;      // Transmit Control Register
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        AT91_REG         EMAC_TSR;      // Transmit Status Register
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        AT91_REG         EMAC_RBQP;     // Receive Buffer Queue Pointer
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        AT91_REG         Reserved0[1];  //
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        AT91_REG         EMAC_RSR;      // Receive Status Register
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        AT91_REG         EMAC_ISR;      // Interrupt Status Register
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        AT91_REG         EMAC_IER;      // Interrupt Enable Register
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        AT91_REG         EMAC_IDR;      // Interrupt Disable Register
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        AT91_REG         EMAC_IMR;      // Interrupt Mask Register
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        AT91_REG         EMAC_MAN;      // PHY Maintenance Register
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        AT91_REG         Reserved1[2];  //
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        AT91_REG         EMAC_FRA;      // Frames Transmitted OK Register
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        AT91_REG         EMAC_SCOL;     // Single Collision Frame Register
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        AT91_REG         EMAC_MCOL;     // Multiple Collision Frame Register
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        AT91_REG         EMAC_OK;       // Frames Received OK Register
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        AT91_REG         EMAC_SEQE;     // Frame Check Sequence Error Register
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        AT91_REG         EMAC_ALE;      // Alignment Error Register
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        AT91_REG         EMAC_DTE;      // Deferred Transmission Frame Register
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        AT91_REG         EMAC_LCOL;     // Late Collision Register
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        AT91_REG         EMAC_ECOL;     // Excessive Collision Register
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        AT91_REG         EMAC_CSE;      // Carrier Sense Error Register
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        AT91_REG         EMAC_TUE;      // Transmit Underrun Error Register
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        AT91_REG         EMAC_CDE;      // Code Error Register
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        AT91_REG         EMAC_ELR;      // Excessive Length Error Register
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        AT91_REG         EMAC_RJB;      // Receive Jabber Register
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        AT91_REG         EMAC_USF;      // Undersize Frame Register
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        AT91_REG         EMAC_SQEE;     // SQE Test Error Register
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        AT91_REG         EMAC_DRFC;     // Discarded RX Frame Register
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        AT91_REG         Reserved2[3];  //
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        AT91_REG         EMAC_HSH;      // Hash Address High[63:32]
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        AT91_REG         EMAC_HSL;      // Hash Address Low[31:0]
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        AT91_REG         EMAC_SA1L;     // Specific Address 1 Low, First 4 bytes
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        AT91_REG         EMAC_SA1H;     // Specific Address 1 High, Last 2 bytes
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        AT91_REG         EMAC_SA2L;     // Specific Address 2 Low, First 4 bytes
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        AT91_REG         EMAC_SA2H;     // Specific Address 2 High, Last 2 bytes
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        AT91_REG         EMAC_SA3L;     // Specific Address 3 Low, First 4 bytes
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        AT91_REG         EMAC_SA3H;     // Specific Address 3 High, Last 2 bytes
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        AT91_REG         EMAC_SA4L;     // Specific Address 4 Low, First 4 bytes
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        AT91_REG         EMAC_SA4H;     // Specific Address 4 High, Last 2 bytesr
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} AT91S_EMAC, *AT91PS_EMAC;
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#endif
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// -------- EMAC_CTL : (EMAC Offset: 0x0)  --------
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#define AT91C_EMAC_LB         ( 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
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#define AT91C_EMAC_LBL        ( 0x1 <<  1) // (EMAC) Loopback local.
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#define AT91C_EMAC_RE         ( 0x1 <<  2) // (EMAC) Receive enable.
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#define AT91C_EMAC_TE         ( 0x1 <<  3) // (EMAC) Transmit enable.
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#define AT91C_EMAC_MPE        ( 0x1 <<  4) // (EMAC) Management port enable.
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#define AT91C_EMAC_CSR        ( 0x1 <<  5) // (EMAC) Clear statistics registers.
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#define AT91C_EMAC_ISR        ( 0x1 <<  6) // (EMAC) Increment statistics registers.
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#define AT91C_EMAC_WES        ( 0x1 <<  7) // (EMAC) Write enable for statistics registers.
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#define AT91C_EMAC_BP         ( 0x1 <<  8) // (EMAC) Back pressure.
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// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------
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#define AT91C_EMAC_SPD        ( 0x1 <<  0) // (EMAC) Speed.
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#define AT91C_EMAC_FD         ( 0x1 <<  1) // (EMAC) Full duplex.
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#define AT91C_EMAC_BR         ( 0x1 <<  2) // (EMAC) Bit rate.
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#define AT91C_EMAC_CAF        ( 0x1 <<  4) // (EMAC) Copy all frames.
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#define AT91C_EMAC_NBC        ( 0x1 <<  5) // (EMAC) No broadcast.
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#define AT91C_EMAC_MTI        ( 0x1 <<  6) // (EMAC) Multicast hash enable
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#define AT91C_EMAC_UNI        ( 0x1 <<  7) // (EMAC) Unicast hash enable.
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#define AT91C_EMAC_BIG        ( 0x1 <<  8) // (EMAC) Receive 1522 bytes.
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#define AT91C_EMAC_EAE        ( 0x1 <<  9) // (EMAC) External address match enable.
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#define AT91C_EMAC_CLK        ( 0x3 << 10) // (EMAC)
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#define         AT91C_EMAC_CLK_HCLK_8               ( 0x0 << 10) // (EMAC) HCLK divided by 8
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#define         AT91C_EMAC_CLK_HCLK_16              ( 0x1 << 10) // (EMAC) HCLK divided by 16
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#define         AT91C_EMAC_CLK_HCLK_32              ( 0x2 << 10) // (EMAC) HCLK divided by 32
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#define         AT91C_EMAC_CLK_HCLK_64              ( 0x3 << 10) // (EMAC) HCLK divided by 64
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#define AT91C_EMAC_RTY        ( 0x1 << 12) // (EMAC)
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#define AT91C_EMAC_RMII       ( 0x1 << 13) // (EMAC)
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// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------
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#define AT91C_EMAC_MDIO       ( 0x1 <<  1) // (EMAC)
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#define AT91C_EMAC_IDLE       ( 0x1 <<  2) // (EMAC)
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// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------
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#define AT91C_EMAC_LEN        ( 0x7FF <<  0) // (EMAC)
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#define AT91C_EMAC_NCRC       ( 0x1 << 15) // (EMAC)
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// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------
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#define AT91C_EMAC_OVR        ( 0x1 <<  0) // (EMAC)
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#define AT91C_EMAC_COL        ( 0x1 <<  1) // (EMAC)
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#define AT91C_EMAC_RLE        ( 0x1 <<  2) // (EMAC)
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#define AT91C_EMAC_TXIDLE     ( 0x1 <<  3) // (EMAC)
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#define AT91C_EMAC_BNQ        ( 0x1 <<  4) // (EMAC)
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#define AT91C_EMAC_COMP       ( 0x1 <<  5) // (EMAC)
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#define AT91C_EMAC_UND        ( 0x1 <<  6) // (EMAC)
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// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
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#define AT91C_EMAC_BNA        ( 0x1 <<  0) // (EMAC)
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#define AT91C_EMAC_REC        ( 0x1 <<  1) // (EMAC)
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// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
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#define AT91C_EMAC_DONE       ( 0x1 <<  0) // (EMAC)
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#define AT91C_EMAC_RCOM       ( 0x1 <<  1) // (EMAC)
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#define AT91C_EMAC_RBNA       ( 0x1 <<  2) // (EMAC)
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#define AT91C_EMAC_TOVR       ( 0x1 <<  3) // (EMAC)
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#define AT91C_EMAC_TUND       ( 0x1 <<  4) // (EMAC)
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#define AT91C_EMAC_RTRY       ( 0x1 <<  5) // (EMAC)
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#define AT91C_EMAC_TBRE       ( 0x1 <<  6) // (EMAC)
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#define AT91C_EMAC_TCOM       ( 0x1 <<  7) // (EMAC)
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#define AT91C_EMAC_TIDLE      ( 0x1 <<  8) // (EMAC)
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#define AT91C_EMAC_LINK       ( 0x1 <<  9) // (EMAC)
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#define AT91C_EMAC_ROVR       ( 0x1 << 10) // (EMAC)
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#define AT91C_EMAC_HRESP      ( 0x1 << 11) // (EMAC)
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// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
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// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
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// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
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// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
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#define AT91C_EMAC_DATA       ( 0xFFFF <<  0) // (EMAC)
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#define AT91C_EMAC_CODE       ( 0x3 << 16) // (EMAC)
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#define         AT91C_EMAC_CODE_802_3 ( 0x2 << 16) // (EMAC) Write Operation
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#define AT91C_EMAC_REGA       ( 0x1F << 18) // (EMAC)
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#define AT91C_EMAC_PHYA       ( 0x1F << 23) // (EMAC)
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#define AT91C_EMAC_RW         ( 0x3 << 28) // (EMAC)
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#define         AT91C_EMAC_RW_R       ( 0x2 << 28) // (EMAC) Read Operation
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#define         AT91C_EMAC_RW_W       ( 0x1 << 28) // (EMAC) Write Operation
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#define AT91C_EMAC_HIGH       ( 0x1 << 30) // (EMAC)
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#define AT91C_EMAC_LOW        ( 0x1 << 31) // (EMAC)
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#endif

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