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phoenix |
#ifndef __MODE_CTRL00_H
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#define __MODE_CTRL00_H
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/*
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* Register definitions for the reset and mode control
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*/
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/*
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* Copyright (C) 2001 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR ))
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#define BOOT_CR_BF_MSK (0x1)
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#define BOOT_CR_BF_OFST (0)
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#define BOOT_CR_HM_MSK (0x2)
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#define BOOT_CR_HM_OFST (1)
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#define BOOT_CR_RE_MSK (0x4)
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#define BOOT_CR_RE_OFST (2)
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#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 ))
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#define RESET_SR_WR_MSK (0x1)
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#define RESET_SR_WR_OFST (0)
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#define RESET_SR_CR_MSK (0x2)
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#define RESET_SR_CR_OFST (1)
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#define RESET_SR_JT_MSK (0x4)
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#define RESET_SR_JT_OFST (2)
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#define RESET_SR_ER_MSK (0x8)
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#define RESET_SR_ER_OFST (3)
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#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 ))
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#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 ))
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#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
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#define SRAM0_SR_SIZE_OFST (12)
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#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 ))
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#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
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#define SRAM1_SR_SIZE_OFST (12)
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#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 ))
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#define DPSRAM0_SR_MODE_MSK (0xF)
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#define DPSRAM0_SR_MODE_OFST (0)
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#define DPSRAM0_SR_GLBL_MSK (0x30)
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#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
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#define DPSRAM0_SR_SIZE_OFST (12)
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#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 ))
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#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
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#define DPSRAM0_LCR_LCKADDR_OFST (4)
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#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 ))
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#define DPSRAM1_SR_MODE_MSK (0xF)
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#define DPSRAM1_SR_MODE_OFST (0)
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#define DPSRAM1_SR_GLBL_MSK (0x30)
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#define DPSRAM1_SR_GLBL_OFST (4)
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#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
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#define DPSRAM1_SR_SIZE_OFST (12)
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#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C ))
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#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
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#define DPSRAM1_LCR_LCKADDR_OFST (4)
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#endif /* __MODE_CTRL00_H */
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