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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-arm/] [arch-l7200/] [sys-clock.h] - Blame information for rev 1774

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1 1276 phoenix
/****************************************************************************/
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/*
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 *  linux/include/asm-arm/arch-l7200/sys-clock.h
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 *
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 *   Registers and  helper functions for the L7200 Link-Up Systems
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 *   System clocks.
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 *
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 *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
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 *
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 *  This file is subject to the terms and conditions of the GNU General Public
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 *  License. See the file COPYING in the main directory of this archive for
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 *  more details.
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 */
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/****************************************************************************/
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#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
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/* IO_START and IO_BASE are defined in hardware.h */
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#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF)  /* Physical address */
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#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
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/* Define the interface to the SYS_CLOCK */
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typedef struct
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{
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     unsigned int ENABLE;
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     unsigned int ESYNC;
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     unsigned int SELECT;
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} sys_clock_interface;
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#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
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//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
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//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
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//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
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/* SYS_CLOCK -> ENABLE */
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#define SYN_EN          1<<0
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#define B18M_EN         1<<1
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#define CLK3M6_EN       1<<2
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#define BUART_EN        1<<3
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#define CLK18MU_EN      1<<4
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#define FIR_EN          1<<5
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#define MIRN_EN         1<<6
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#define UARTM_EN        1<<7
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#define SIBADC_EN       1<<8
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#define ALTD_EN         1<<9
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#define CLCLK_EN        1<<10
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/* SYS_CLOCK -> SELECT */
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#define CLK18M_DIV      1<<0
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#define MIR_SEL         1<<1
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#define SSP_SEL         1<<4
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#define MM_DIV          1<<5
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#define MM_SEL          1<<6
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#define ADC_SEL_2       0<<7
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#define ADC_SEL_4       1<<7
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#define ADC_SEL_8       3<<7
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#define ADC_SEL_16      7<<7
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#define ADC_SEL_32      0x0f<<7
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#define ADC_SEL_64      0x1f<<7
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#define ADC_SEL_128     0x3f<<7
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#define ALTD_SEL        1<<13

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