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1276 |
phoenix |
/*
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* SA-1101.h
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*
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* Copyright (c) Peter Danielsson 1999
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*
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* Definition of constants related to the sa1101
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* support chip for the sa1100
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*
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*/
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/* Be sure that virtual mapping is defined right */
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#ifndef __ASM_ARCH_HARDWARE_H
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#error You must include hardware.h not SA-1101.h
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#endif
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#ifndef SA1101_BASE
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#error You must define SA-1101 physical base address
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#endif
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#ifndef LANGUAGE
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# ifdef __ASSEMBLY__
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# define LANGUAGE Assembly
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# else
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# define LANGUAGE C
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# endif
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#endif
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#ifndef SA1101_p2v
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#define SA1101_p2v(PhAdd) (PhAdd)
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#endif
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#include <asm/arch/bitfield.h>
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#define C 0
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#define Assembly 1
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/*
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* Memory map
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*/
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#define __SHMEM_CONTROL0 0x00000000
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#define __SYSTEM_CONTROL1 0x00000400
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#define __ARBITER 0x00020000
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#define __SYSTEM_CONTROL2 0x00040000
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#define __SYSTEM_CONTROL3 0x00060000
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#define __PARALLEL_PORT 0x00080000
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#define __VIDMEM_CONTROL 0x00100000
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#define __UPDATE_FIFO 0x00120000
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#define __SHMEM_CONTROL1 0x00140000
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#define __INTERRUPT_CONTROL 0x00160000
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#define __USB_CONTROL 0x00180000
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#define __TRACK_INTERFACE 0x001a0000
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#define __MOUSE_INTERFACE 0x001b0000
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#define __KEYPAD_INTERFACE 0x001c0000
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#define __PCMCIA_INTERFACE 0x001e0000
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#define __VGA_CONTROL 0x00200000
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#define __GPIO_INTERFACE 0x00300000
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/*
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* Macro that calculates real address for registers in the SA-1101
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*/
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#define _SA1101( x ) ((x) + SA1101_BASE)
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/*
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* Interface and shared memory controller registers
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*
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* Registers
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* SKCR SA-1101 control register (read/write)
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* SMCR Shared Memory Controller Register
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* SNPR Snoop Register
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*/
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#define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
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#define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
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#define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */
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#if LANGUAGE == C
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#define SKCR (*((volatile Word *) SA1101_p2v (_SKCR)))
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#define SMCR (*((volatile Word *) SA1101_p2v (_SMCR)))
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#define SNPR (*((volatile Word *) SA1101_p2v (_SNPR)))
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#define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */
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#define SKCR_BCLKEn 0x0002 /* Enables BCLK */
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#define SKCR_Sleep 0x0004 /* Sleep Mode */
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#define SKCR_IRefEn 0x0008 /* DAC Iref input enable */
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#define SKCR_VCOON 0x0010 /* VCO bias */
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#define SKCR_ScanTestEn 0x0020 /* Enables scan test */
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#define SKCR_ClockTestEn 0x0040 /* Enables clock test */
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#define SMCR_DCAC Fld(2,0) /* Number of column address bits */
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#define SMCR_DRAC Fld(2,2) /* Number of row address bits */
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#define SMCR_ArbiterBias 0x0008 /* favor video or USB */
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#define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */
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#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \
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(( (x) - 8 ) << FShft (SMCR_DCAC))
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#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\
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(( (x) - 9 ) << FShft (SMCR_DRAC)
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#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
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#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
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#define SNPR_WholeBank (1 << 23) /* Whole bank bit */
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#define SNPR_BankSelect Fld(2,27) /* Bank select */
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#define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */
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#define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \
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( (x) << FShft (SNPR_VFBsize))
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#define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \
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(( (x) + 1 ) << FShft (SNPR_BankSelect ))
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#endif /* LANGUAGE == C */
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/*
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* Video Memory Controller
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*
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* Registers
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* VMCCR Configuration register
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* VMCAR VMC address register
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* VMCDR VMC data register
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*
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*/
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#define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */
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#define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */
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#define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */
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#if LANGUAGE == C
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#define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR)))
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#define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR)))
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#define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR)))
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#define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */
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#define VMCCR_Config 0x0001 /* DRAM size */
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#define VMCCR_RefPeriod Fld(2,3) /* Refresh period */
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#define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */
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#define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/
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#define VMCCR_RefTest (1<<10) /* refresh test */
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#define VMCCR_RefLow Fld(6,11) /* refresh low counter */
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#define VMCCR_RefHigh Fld(7,17) /* refresh high counter */
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#define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */
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#define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */
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#endif LANGUAGE == C
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/* Update FIFO
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*
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* Registers
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* UFCR Update FIFO Control Register
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* UFSR Update FIFO Status Register
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* UFLVLR update FIFO level register
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* UFDR update FIFO data register
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*/
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#define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */
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#define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */
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#define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */
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#define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */
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#if LANGUAGE == C
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#define UFCR (*((volatile Word *) SA1101_p2v (_UFCR)))
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#define UFSR (*((volatile Word *) SA1101_p2v (_UFSR)))
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#define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR)))
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#define UFDR (*((volatile Word *) SA1101_p2v (_UFDR)))
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#define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */
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#define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */
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#endif /* LANGUAGE == C */
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/* System Controller
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*
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* Registers
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* SKPCR Power Control Register
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* SKCDR Clock Divider Register
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* DACDR1 DAC1 Data register
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* DACDR2 DAC2 Data register
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*/
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#define _SKPCR _SA1101(0x00000400)
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#define _SKCDR _SA1101(0x00040000)
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#define _DACDR1 _SA1101(0x00060000)
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#define _DACDR2 _SA1101(0x00060400)
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#if LANGUAGE == C
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#define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR)))
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#define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR)))
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#define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1)))
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#define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2)))
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#define SKPCR_UCLKEn 0x01 /* USB Enable */
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#define SKPCR_PCLKEn 0x02 /* PS/2 Enable */
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#define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */
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#define SKPCR_VCLKEn 0x08 /* Video Controller Enable */
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#define SKPCR_PICLKEn 0x10 /* parallel port Enable */
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#define SKPCR_DCLKEn 0x20 /* DACs Enable */
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#define SKPCR_nKPADEn 0x40 /* Multiplexer */
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#define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */
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#define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */
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#define SKDCR_BCLKEn (1<<9) /* BCLK Divider */
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#define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */
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#define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */
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#define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */
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#define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */
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#define SKDCR_ChargePump (1<<25) /* Charge pump control */
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#define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */
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#define SKDCR_ClkTestEn (1<<27) /* Test clock generator */
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#define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */
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#define DACDR_DACCount Fld(8,0) /* Count value */
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#define DACDR1_DACCount DACDR_DACCount
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#define DACDR2_DACCount DACDR_DACCount
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#endif /* LANGUAGE == C */
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/*
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* Parallel Port Interface
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*
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* Registers
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* IEEE_Config IEEE mode selection and programmable attributes
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* IEEE_Control Controls the states of IEEE port control outputs
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* IEEE_Data Forward transfer data register
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* IEEE_Addr Forward transfer address register
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* IEEE_Status Port IO signal status register
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* IEEE_IntStatus Port interrupts status register
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* IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels
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* IEEE_InitTime Forward timeout counter initial value
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* IEEE_TimerStatus Forward timeout counter current value
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* IEEE_FifoReset Reset forward transfer FIFO
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* IEEE_ReloadValue Counter reload value
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* IEEE_TestControl Control testmode
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* IEEE_TestDataIn Test data register
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* IEEE_TestDataInEn Enable test data
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* IEEE_TestCtrlIn Test control signals
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* IEEE_TestCtrlInEn Enable test control signals
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* IEEE_TestDataStat Current data bus value
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*
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*/
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/*
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* The control registers are defined as offsets from a base address
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*/
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#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
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#define _IEEE_Config _IEEE( 0x0000 )
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#define _IEEE_Control _IEEE( 0x0400 )
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#define _IEEE_Data _IEEE( 0x4000 )
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#define _IEEE_Addr _IEEE( 0x0800 )
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#define _IEEE_Status _IEEE( 0x0c00 )
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#define _IEEE_IntStatus _IEEE( 0x1000 )
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#define _IEEE_FifoLevels _IEEE( 0x1400 )
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#define _IEEE_InitTime _IEEE( 0x1800 )
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#define _IEEE_TimerStatus _IEEE( 0x1c00 )
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#define _IEEE_FifoReset _IEEE( 0x2000 )
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#define _IEEE_ReloadValue _IEEE( 0x3c00 )
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#define _IEEE_TestControl _IEEE( 0x2400 )
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#define _IEEE_TestDataIn _IEEE( 0x2800 )
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#define _IEEE_TestDataInEn _IEEE( 0x2c00 )
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#define _IEEE_TestCtrlIn _IEEE( 0x3000 )
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#define _IEEE_TestCtrlInEn _IEEE( 0x3400 )
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#define _IEEE_TestDataStat _IEEE( 0x3800 )
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#if LANGUAGE == C
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#define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
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#define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
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#define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
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#define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
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#define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
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#define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
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#define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
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#define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
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#define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
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#define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
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#define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
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#define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
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#define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
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#define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
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#define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
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#define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
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#define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
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#define IEEE_Config_M Fld(3,0) /* Mode select */
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#define IEEE_Config_D 0x04 /* FIFO access enable */
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#define IEEE_Config_B 0x08 /* 9-bit word enable */
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#define IEEE_Config_T 0x10 /* Data transfer enable */
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#define IEEE_Config_A 0x20 /* Data transfer direction */
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#define IEEE_Config_E 0x40 /* Timer enable */
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#define IEEE_Control_A 0x08 /* AutoFd output */
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#define IEEE_Control_E 0x04 /* Selectin output */
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#define IEEE_Control_T 0x02 /* Strobe output */
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#define IEEE_Control_I 0x01 /* Port init output */
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#define IEEE_Data_C (1<<31) /* Byte count */
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#define IEEE_Data_Db Fld(9,16) /* Data byte 2 */
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|
|
#define IEEE_Data_Da Fld(9,0) /* Data byte 1 */
|
| 305 |
|
|
#define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */
|
| 306 |
|
|
#define IEEE_Status_A 0x0100 /* nAutoFd port output status */
|
| 307 |
|
|
#define IEEE_Status_E 0x0080 /* nSelectIn port output status */
|
| 308 |
|
|
#define IEEE_Status_T 0x0040 /* nStrobe port output status */
|
| 309 |
|
|
#define IEEE_Status_I 0x0020 /* nInit port output status */
|
| 310 |
|
|
#define IEEE_Status_B 0x0010 /* Busy port inout status */
|
| 311 |
|
|
#define IEEE_Status_S 0x0008 /* Select port input status */
|
| 312 |
|
|
#define IEEE_Status_K 0x0004 /* nAck port input status */
|
| 313 |
|
|
#define IEEE_Status_F 0x0002 /* nFault port input status */
|
| 314 |
|
|
#define IEEE_Status_R 0x0001 /* pError port input status */
|
| 315 |
|
|
|
| 316 |
|
|
#define IEEE_IntStatus_IntReqDat 0x0100
|
| 317 |
|
|
#define IEEE_IntStatus_IntReqEmp 0x0080
|
| 318 |
|
|
#define IEEE_IntStatus_IntReqInt 0x0040
|
| 319 |
|
|
#define IEEE_IntStatus_IntReqRav 0x0020
|
| 320 |
|
|
#define IEEE_IntStatus_IntReqTim 0x0010
|
| 321 |
|
|
#define IEEE_IntStatus_RevAddrComp 0x0008
|
| 322 |
|
|
#define IEEE_IntStatus_RevDataComp 0x0004
|
| 323 |
|
|
#define IEEE_IntStatus_FwdAddrComp 0x0002
|
| 324 |
|
|
#define IEEE_IntStatus_FwdDataComp 0x0001
|
| 325 |
|
|
#define IEEE_FifoLevels_RevFifoLevel 2
|
| 326 |
|
|
#define IEEE_FifoLevels_FwdFifoLevel 1
|
| 327 |
|
|
#define IEEE_InitTime_TimValInit Fld(22,0)
|
| 328 |
|
|
#define IEEE_TimerStatus_TimValStat Fld(22,0)
|
| 329 |
|
|
#define IEEE_ReloadValue_Reload Fld(4,0)
|
| 330 |
|
|
|
| 331 |
|
|
#define IEEE_TestControl_RegClk 0x04
|
| 332 |
|
|
#define IEEE_TestControl_ClockSelect Fld(2,1)
|
| 333 |
|
|
#define IEEE_TestControl_TimerTestModeEn 0x01
|
| 334 |
|
|
#define IEEE_TestCtrlIn_PError 0x10
|
| 335 |
|
|
#define IEEE_TestCtrlIn_nFault 0x08
|
| 336 |
|
|
#define IEEE_TestCtrlIn_nAck 0x04
|
| 337 |
|
|
#define IEEE_TestCtrlIn_PSel 0x02
|
| 338 |
|
|
#define IEEE_TestCtrlIn_Busy 0x01
|
| 339 |
|
|
|
| 340 |
|
|
#endif /* LANGUAGE == C */
|
| 341 |
|
|
|
| 342 |
|
|
/*
|
| 343 |
|
|
* VGA Controller
|
| 344 |
|
|
*
|
| 345 |
|
|
* Registers
|
| 346 |
|
|
* VideoControl Video Control Register
|
| 347 |
|
|
* VgaTiming0 VGA Timing Register 0
|
| 348 |
|
|
* VgaTiming1 VGA Timing Register 1
|
| 349 |
|
|
* VgaTiming2 VGA Timing Register 2
|
| 350 |
|
|
* VgaTiming3 VGA Timing Register 3
|
| 351 |
|
|
* VgaBorder VGA Border Color Register
|
| 352 |
|
|
* VgaDBAR VGADMA Base Address Register
|
| 353 |
|
|
* VgaDCAR VGADMA Channel Current Address Register
|
| 354 |
|
|
* VgaStatus VGA Status Register
|
| 355 |
|
|
* VgaInterruptMask VGA Interrupt Mask Register
|
| 356 |
|
|
* VgaPalette VGA Palette Registers
|
| 357 |
|
|
* DacControl DAC Control Register
|
| 358 |
|
|
* VgaTest VGA Controller Test Register
|
| 359 |
|
|
*/
|
| 360 |
|
|
|
| 361 |
|
|
#define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL )
|
| 362 |
|
|
|
| 363 |
|
|
#define _VideoControl _VGA( 0x0000 )
|
| 364 |
|
|
#define _VgaTiming0 _VGA( 0x0400 )
|
| 365 |
|
|
#define _VgaTiming1 _VGA( 0x0800 )
|
| 366 |
|
|
#define _VgaTiming2 _VGA( 0x0c00 )
|
| 367 |
|
|
#define _VgaTiming3 _VGA( 0x1000 )
|
| 368 |
|
|
#define _VgaBorder _VGA( 0x1400 )
|
| 369 |
|
|
#define _VgaDBAR _VGA( 0x1800 )
|
| 370 |
|
|
#define _VgaDCAR _VGA( 0x1c00 )
|
| 371 |
|
|
#define _VgaStatus _VGA( 0x2000 )
|
| 372 |
|
|
#define _VgaInterruptMask _VGA( 0x2400 )
|
| 373 |
|
|
#define _VgaPalette _VGA( 0x40000 )
|
| 374 |
|
|
#define _DacControl _VGA( 0x3000 )
|
| 375 |
|
|
#define _VgaTest _VGA( 0x2c00 )
|
| 376 |
|
|
|
| 377 |
|
|
#if (LANGUAGE == C)
|
| 378 |
|
|
#define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl)))
|
| 379 |
|
|
#define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
|
| 380 |
|
|
#define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
|
| 381 |
|
|
#define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
|
| 382 |
|
|
#define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
|
| 383 |
|
|
#define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder)))
|
| 384 |
|
|
#define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
|
| 385 |
|
|
#define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
|
| 386 |
|
|
#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus)))
|
| 387 |
|
|
#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
|
| 388 |
|
|
#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette)))
|
| 389 |
|
|
#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))
|
| 390 |
|
|
#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest)))
|
| 391 |
|
|
|
| 392 |
|
|
#define VideoControl_VgaEn 0x00000000
|
| 393 |
|
|
#define VideoControl_BGR 0x00000001
|
| 394 |
|
|
#define VideoControl_VCompVal Fld(2,2)
|
| 395 |
|
|
#define VideoControl_VgaReq Fld(4,4)
|
| 396 |
|
|
#define VideoControl_VBurstL Fld(4,8)
|
| 397 |
|
|
#define VideoControl_VMode (1<<12)
|
| 398 |
|
|
#define VideoControl_PalRead (1<<13)
|
| 399 |
|
|
|
| 400 |
|
|
#define VgaTiming0_PPL Fld(6,2)
|
| 401 |
|
|
#define VgaTiming0_HSW Fld(8,8)
|
| 402 |
|
|
#define VgaTiming0_HFP Fld(8,16)
|
| 403 |
|
|
#define VgaTiming0_HBP Fld(8,24)
|
| 404 |
|
|
|
| 405 |
|
|
#define VgaTiming1_LPS Fld(10,0)
|
| 406 |
|
|
#define VgaTiming1_VSW Fld(6,10)
|
| 407 |
|
|
#define VgaTiming1_VFP Fld(8,16)
|
| 408 |
|
|
#define VgaTiming1_VBP Fld(8,24)
|
| 409 |
|
|
|
| 410 |
|
|
#define VgaTiming2_IVS 0x01
|
| 411 |
|
|
#define VgaTiming2_IHS 0x02
|
| 412 |
|
|
#define VgaTiming2_CVS 0x04
|
| 413 |
|
|
#define VgaTiming2_CHS 0x08
|
| 414 |
|
|
|
| 415 |
|
|
#define VgaTiming3_HBS Fld(8,0)
|
| 416 |
|
|
#define VgaTiming3_HBE Fld(8,8)
|
| 417 |
|
|
#define VgaTiming3_VBS Fld(8,16)
|
| 418 |
|
|
#define VgaTiming3_VBE Fld(8,24)
|
| 419 |
|
|
|
| 420 |
|
|
#define VgaBorder_BCOL Fld(24,0)
|
| 421 |
|
|
|
| 422 |
|
|
#define VgaStatus_VFUF 0x01
|
| 423 |
|
|
#define VgaStatus_VNext 0x02
|
| 424 |
|
|
#define VgaStatus_VComp 0x04
|
| 425 |
|
|
|
| 426 |
|
|
#define VgaInterruptMask_VFUFMask 0x00
|
| 427 |
|
|
#define VgaInterruptMask_VNextMask 0x01
|
| 428 |
|
|
#define VgaInterruptMask_VCompMask 0x02
|
| 429 |
|
|
|
| 430 |
|
|
#define VgaPalette_R Fld(8,0)
|
| 431 |
|
|
#define VgaPalette_G Fld(8,8)
|
| 432 |
|
|
#define VgaPalette_B Fld(8,16)
|
| 433 |
|
|
|
| 434 |
|
|
#define DacControl_DACON 0x0001
|
| 435 |
|
|
#define DacControl_COMPON 0x0002
|
| 436 |
|
|
#define DacControl_PEDON 0x0004
|
| 437 |
|
|
#define DacControl_RTrim Fld(5,4)
|
| 438 |
|
|
#define DacControl_GTrim Fld(5,9)
|
| 439 |
|
|
#define DacControl_BTrim Fld(5,14)
|
| 440 |
|
|
|
| 441 |
|
|
#define VgaTest_TDAC 0x00
|
| 442 |
|
|
#define VgaTest_Datatest Fld(4,1)
|
| 443 |
|
|
#define VgaTest_DACTESTDAC 0x10
|
| 444 |
|
|
#define VgaTest_DACTESTOUT Fld(3,5)
|
| 445 |
|
|
|
| 446 |
|
|
#endif /* LANGUAGE == C */
|
| 447 |
|
|
|
| 448 |
|
|
/*
|
| 449 |
|
|
* USB Host Interface Controller
|
| 450 |
|
|
*
|
| 451 |
|
|
* Registers
|
| 452 |
|
|
* Revision
|
| 453 |
|
|
* Control
|
| 454 |
|
|
* CommandStatus
|
| 455 |
|
|
* InterruptStatus
|
| 456 |
|
|
* InterruptEnable
|
| 457 |
|
|
* HCCA
|
| 458 |
|
|
* PeriodCurrentED
|
| 459 |
|
|
* ControlHeadED
|
| 460 |
|
|
* BulkHeadED
|
| 461 |
|
|
* BulkCurrentED
|
| 462 |
|
|
* DoneHead
|
| 463 |
|
|
* FmInterval
|
| 464 |
|
|
* FmRemaining
|
| 465 |
|
|
* FmNumber
|
| 466 |
|
|
* PeriodicStart
|
| 467 |
|
|
* LSThreshold
|
| 468 |
|
|
* RhDescriptorA
|
| 469 |
|
|
* RhDescriptorB
|
| 470 |
|
|
* RhStatus
|
| 471 |
|
|
* RhPortStatus
|
| 472 |
|
|
* USBStatus
|
| 473 |
|
|
* USBReset
|
| 474 |
|
|
* USTAR
|
| 475 |
|
|
* USWER
|
| 476 |
|
|
* USRFR
|
| 477 |
|
|
* USNFR
|
| 478 |
|
|
* USTCSR
|
| 479 |
|
|
* USSR
|
| 480 |
|
|
*
|
| 481 |
|
|
*/
|
| 482 |
|
|
|
| 483 |
|
|
#define _USB( x ) _SA1101( ( x ) + __USB_CONTROL )
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
#define _Revision _USB( 0x0000 )
|
| 487 |
|
|
#define _Control _USB( 0x0888 )
|
| 488 |
|
|
#define _CommandStatus _USB( 0x0c00 )
|
| 489 |
|
|
#define _InterruptStatus _USB( 0x1000 )
|
| 490 |
|
|
#define _InterruptEnable _USB( 0x1400 )
|
| 491 |
|
|
#define _HCCA _USB( 0x1800 )
|
| 492 |
|
|
#define _PeriodCurrentED _USB( 0x1c00 )
|
| 493 |
|
|
#define _ControlHeadED _USB( 0x2000 )
|
| 494 |
|
|
#define _BulkHeadED _USB( 0x2800 )
|
| 495 |
|
|
#define _BulkCurrentED _USB( 0x2c00 )
|
| 496 |
|
|
#define _DoneHead _USB( 0x3000 )
|
| 497 |
|
|
#define _FmInterval _USB( 0x3400 )
|
| 498 |
|
|
#define _FmRemaining _USB( 0x3800 )
|
| 499 |
|
|
#define _FmNumber _USB( 0x3c00 )
|
| 500 |
|
|
#define _PeriodicStart _USB( 0x4000 )
|
| 501 |
|
|
#define _LSThreshold _USB( 0x4400 )
|
| 502 |
|
|
#define _RhDescriptorA _USB( 0x4800 )
|
| 503 |
|
|
#define _RhDescriptorB _USB( 0x4c00 )
|
| 504 |
|
|
#define _RhStatus _USB( 0x5000 )
|
| 505 |
|
|
#define _RhPortStatus _USB( 0x5400 )
|
| 506 |
|
|
#define _USBStatus _USB( 0x11800 )
|
| 507 |
|
|
#define _USBReset _USB( 0x11c00 )
|
| 508 |
|
|
|
| 509 |
|
|
#define _USTAR _USB( 0x10400 )
|
| 510 |
|
|
#define _USWER _USB( 0x10800 )
|
| 511 |
|
|
#define _USRFR _USB( 0x10c00 )
|
| 512 |
|
|
#define _USNFR _USB( 0x11000 )
|
| 513 |
|
|
#define _USTCSR _USB( 0x11400 )
|
| 514 |
|
|
#define _USSR _USB( 0x11800 )
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
#if (LANGUAGE == C)
|
| 518 |
|
|
|
| 519 |
|
|
#define Revision (*((volatile Word *) SA1101_p2v (_Revision)))
|
| 520 |
|
|
#define Control (*((volatile Word *) SA1101_p2v (_Control)))
|
| 521 |
|
|
#define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus)))
|
| 522 |
|
|
#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
|
| 523 |
|
|
#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
|
| 524 |
|
|
#define HCCA (*((volatile Word *) SA1101_p2v (_HCCA)))
|
| 525 |
|
|
#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
|
| 526 |
|
|
#define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
|
| 527 |
|
|
#define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
|
| 528 |
|
|
#define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
|
| 529 |
|
|
#define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead)))
|
| 530 |
|
|
#define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval)))
|
| 531 |
|
|
#define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining)))
|
| 532 |
|
|
#define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber)))
|
| 533 |
|
|
#define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
|
| 534 |
|
|
#define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold)))
|
| 535 |
|
|
#define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
|
| 536 |
|
|
#define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
|
| 537 |
|
|
#define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus)))
|
| 538 |
|
|
#define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
|
| 539 |
|
|
#define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus)))
|
| 540 |
|
|
#define USBReset (*((volatile Word *) SA1101_p2v (_USBReset)))
|
| 541 |
|
|
#define USTAR (*((volatile Word *) SA1101_p2v (_USTAR)))
|
| 542 |
|
|
#define USWER (*((volatile Word *) SA1101_p2v (_USWER)))
|
| 543 |
|
|
#define USRFR (*((volatile Word *) SA1101_p2v (_USRFR)))
|
| 544 |
|
|
#define USNFR (*((volatile Word *) SA1101_p2v (_USNFR)))
|
| 545 |
|
|
#define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR)))
|
| 546 |
|
|
#define USSR (*((volatile Word *) SA1101_p2v (_USSR)))
|
| 547 |
|
|
|
| 548 |
|
|
|
| 549 |
|
|
#define USBStatus_IrqHciRmtWkp (1<<7)
|
| 550 |
|
|
#define USBStatus_IrqHciBuffAcc (1<<8)
|
| 551 |
|
|
#define USBStatus_nIrqHciM (1<<9)
|
| 552 |
|
|
#define USBStatus_nHciMFClr (1<<10)
|
| 553 |
|
|
|
| 554 |
|
|
#define USBReset_ForceIfReset 0x01
|
| 555 |
|
|
#define USBReset_ForceHcReset 0x02
|
| 556 |
|
|
#define USBReset_ClkGenReset 0x04
|
| 557 |
|
|
|
| 558 |
|
|
#define USTCR_RdBstCntrl Fld(3,0)
|
| 559 |
|
|
#define USTCR_ByteEnable Fld(4,3)
|
| 560 |
|
|
#define USTCR_WriteEn (1<<7)
|
| 561 |
|
|
#define USTCR_FifoCir (1<<8)
|
| 562 |
|
|
#define USTCR_TestXferSel (1<<9)
|
| 563 |
|
|
#define USTCR_FifoCirAtEnd (1<<10)
|
| 564 |
|
|
#define USTCR_nSimScaleDownClk (1<<11)
|
| 565 |
|
|
|
| 566 |
|
|
#define USSR_nAppMDEmpty 0x01
|
| 567 |
|
|
#define USSR_nAppMDFirst 0x02
|
| 568 |
|
|
#define USSR_nAppMDLast 0x04
|
| 569 |
|
|
#define USSR_nAppMDFull 0x08
|
| 570 |
|
|
#define USSR_nAppMAFull 0x10
|
| 571 |
|
|
#define USSR_XferReq 0x20
|
| 572 |
|
|
#define USSR_XferEnd 0x40
|
| 573 |
|
|
|
| 574 |
|
|
#endif /* LANGUAGE == C */
|
| 575 |
|
|
|
| 576 |
|
|
|
| 577 |
|
|
/*
|
| 578 |
|
|
* Interrupt Controller
|
| 579 |
|
|
*
|
| 580 |
|
|
* Registers
|
| 581 |
|
|
* INTTEST0 Test register 0
|
| 582 |
|
|
* INTTEST1 Test register 1
|
| 583 |
|
|
* INTENABLE0 Interrupt Enable register 0
|
| 584 |
|
|
* INTENABLE1 Interrupt Enable register 1
|
| 585 |
|
|
* INTPOL0 Interrupt Polarity selection 0
|
| 586 |
|
|
* INTPOL1 Interrupt Polarity selection 1
|
| 587 |
|
|
* INTTSTSEL Interrupt source selection
|
| 588 |
|
|
* INTSTATCLR0 Interrupt Status 0
|
| 589 |
|
|
* INTSTATCLR1 Interrupt Status 1
|
| 590 |
|
|
* INTSET0 Interrupt Set 0
|
| 591 |
|
|
* INTSET1 Interrupt Set 1
|
| 592 |
|
|
*/
|
| 593 |
|
|
|
| 594 |
|
|
#define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL)
|
| 595 |
|
|
|
| 596 |
|
|
#define _INTTEST0 _INT( 0x1000 )
|
| 597 |
|
|
#define _INTTEST1 _INT( 0x1400 )
|
| 598 |
|
|
#define _INTENABLE0 _INT( 0x2000 )
|
| 599 |
|
|
#define _INTENABLE1 _INT( 0x2400 )
|
| 600 |
|
|
#define _INTPOL0 _INT( 0x3000 )
|
| 601 |
|
|
#define _INTPOL1 _INT( 0x3400 )
|
| 602 |
|
|
#define _INTTSTSEL _INT( 0x5000 )
|
| 603 |
|
|
#define _INTSTATCLR0 _INT( 0x6000 )
|
| 604 |
|
|
#define _INTSTATCLR1 _INT( 0x6400 )
|
| 605 |
|
|
#define _INTSET0 _INT( 0x7000 )
|
| 606 |
|
|
#define _INTSET1 _INT( 0x7400 )
|
| 607 |
|
|
|
| 608 |
|
|
#if ( LANGUAGE == C )
|
| 609 |
|
|
#define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0)))
|
| 610 |
|
|
#define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1)))
|
| 611 |
|
|
#define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
|
| 612 |
|
|
#define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
|
| 613 |
|
|
#define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0)))
|
| 614 |
|
|
#define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1)))
|
| 615 |
|
|
#define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
|
| 616 |
|
|
#define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
|
| 617 |
|
|
#define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
|
| 618 |
|
|
#define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0)))
|
| 619 |
|
|
#define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1)))
|
| 620 |
|
|
|
| 621 |
|
|
#endif /* LANGUAGE == C */
|
| 622 |
|
|
|
| 623 |
|
|
/*
|
| 624 |
|
|
* PS/2 Trackpad and Mouse Interfaces
|
| 625 |
|
|
*
|
| 626 |
|
|
* Registers (prefix kbd applies to trackpad interface, mse to mouse)
|
| 627 |
|
|
* KBDCR Control Register
|
| 628 |
|
|
* KBDSTAT Status Register
|
| 629 |
|
|
* KBDDATA Transmit/Receive Data register
|
| 630 |
|
|
* KBDCLKDIV Clock Division Register
|
| 631 |
|
|
* KBDPRECNT Clock Precount Register
|
| 632 |
|
|
* KBDTEST1 Test register 1
|
| 633 |
|
|
* KBDTEST2 Test register 2
|
| 634 |
|
|
* KBDTEST3 Test register 3
|
| 635 |
|
|
* KBDTEST4 Test register 4
|
| 636 |
|
|
* MSECR
|
| 637 |
|
|
* MSESTAT
|
| 638 |
|
|
* MSEDATA
|
| 639 |
|
|
* MSECLKDIV
|
| 640 |
|
|
* MSEPRECNT
|
| 641 |
|
|
* MSETEST1
|
| 642 |
|
|
* MSETEST2
|
| 643 |
|
|
* MSETEST3
|
| 644 |
|
|
* MSETEST4
|
| 645 |
|
|
*
|
| 646 |
|
|
*/
|
| 647 |
|
|
|
| 648 |
|
|
#define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE )
|
| 649 |
|
|
#define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE )
|
| 650 |
|
|
|
| 651 |
|
|
#define _KBDCR _KBD( 0x0000 )
|
| 652 |
|
|
#define _KBDSTAT _KBD( 0x0400 )
|
| 653 |
|
|
#define _KBDDATA _KBD( 0x0800 )
|
| 654 |
|
|
#define _KBDCLKDIV _KBD( 0x0c00 )
|
| 655 |
|
|
#define _KBDPRECNT _KBD( 0x1000 )
|
| 656 |
|
|
#define _KBDTEST1 _KBD( 0x2000 )
|
| 657 |
|
|
#define _KBDTEST2 _KBD( 0x2400 )
|
| 658 |
|
|
#define _KBDTEST3 _KBD( 0x2800 )
|
| 659 |
|
|
#define _KBDTEST4 _KBD( 0x2c00 )
|
| 660 |
|
|
#define _MSECR _MSE( 0x0000 )
|
| 661 |
|
|
#define _MSESTAT _MSE( 0x0400 )
|
| 662 |
|
|
#define _MSEDATA _MSE( 0x0800 )
|
| 663 |
|
|
#define _MSECLKDIV _MSE( 0x0c00 )
|
| 664 |
|
|
#define _MSEPRECNT _MSE( 0x1000 )
|
| 665 |
|
|
#define _MSETEST1 _MSE( 0x2000 )
|
| 666 |
|
|
#define _MSETEST2 _MSE( 0x2400 )
|
| 667 |
|
|
#define _MSETEST3 _MSE( 0x2800 )
|
| 668 |
|
|
#define _MSETEST4 _MSE( 0x2c00 )
|
| 669 |
|
|
|
| 670 |
|
|
#if ( LANGUAGE == C )
|
| 671 |
|
|
|
| 672 |
|
|
#define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR)))
|
| 673 |
|
|
#define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
|
| 674 |
|
|
#define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA)))
|
| 675 |
|
|
#define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
|
| 676 |
|
|
#define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
|
| 677 |
|
|
#define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
|
| 678 |
|
|
#define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
|
| 679 |
|
|
#define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
|
| 680 |
|
|
#define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
|
| 681 |
|
|
#define MSECR (*((volatile Word *) SA1101_p2v (_MSECR)))
|
| 682 |
|
|
#define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT)))
|
| 683 |
|
|
#define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA)))
|
| 684 |
|
|
#define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
|
| 685 |
|
|
#define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
|
| 686 |
|
|
#define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1)))
|
| 687 |
|
|
#define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2)))
|
| 688 |
|
|
#define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3)))
|
| 689 |
|
|
#define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4)))
|
| 690 |
|
|
|
| 691 |
|
|
|
| 692 |
|
|
#define KBDCR_ENA 0x08
|
| 693 |
|
|
#define KBDCR_FKD 0x02
|
| 694 |
|
|
#define KBDCR_FKC 0x01
|
| 695 |
|
|
|
| 696 |
|
|
#define KBDSTAT_TXE 0x80
|
| 697 |
|
|
#define KBDSTAT_TXB 0x40
|
| 698 |
|
|
#define KBDSTAT_RXF 0x20
|
| 699 |
|
|
#define KBDSTAT_RXB 0x10
|
| 700 |
|
|
#define KBDSTAT_ENA 0x08
|
| 701 |
|
|
#define KBDSTAT_RXP 0x04
|
| 702 |
|
|
#define KBDSTAT_KBD 0x02
|
| 703 |
|
|
#define KBDSTAT_KBC 0x01
|
| 704 |
|
|
|
| 705 |
|
|
#define KBDCLKDIV_DivVal Fld(4,0)
|
| 706 |
|
|
|
| 707 |
|
|
#define MSECR_ENA 0x08
|
| 708 |
|
|
#define MSECR_FKD 0x02
|
| 709 |
|
|
#define MSECR_FKC 0x01
|
| 710 |
|
|
|
| 711 |
|
|
#define MSESTAT_TXE 0x80
|
| 712 |
|
|
#define MSESTAT_TXB 0x40
|
| 713 |
|
|
#define MSESTAT_RXF 0x20
|
| 714 |
|
|
#define MSESTAT_RXB 0x10
|
| 715 |
|
|
#define MSESTAT_ENA 0x08
|
| 716 |
|
|
#define MSESTAT_RXP 0x04
|
| 717 |
|
|
#define MSESTAT_MSD 0x02
|
| 718 |
|
|
#define MSESTAT_MSC 0x01
|
| 719 |
|
|
|
| 720 |
|
|
#define MSECLKDIV_DivVal Fld(4,0)
|
| 721 |
|
|
|
| 722 |
|
|
#define KBDTEST1_CD 0x80
|
| 723 |
|
|
#define KBDTEST1_RC1 0x40
|
| 724 |
|
|
#define KBDTEST1_MC 0x20
|
| 725 |
|
|
#define KBDTEST1_C Fld(2,3)
|
| 726 |
|
|
#define KBDTEST1_T2 0x40
|
| 727 |
|
|
#define KBDTEST1_T1 0x20
|
| 728 |
|
|
#define KBDTEST1_T0 0x10
|
| 729 |
|
|
#define KBDTEST2_TICBnRES 0x08
|
| 730 |
|
|
#define KBDTEST2_RKC 0x04
|
| 731 |
|
|
#define KBDTEST2_RKD 0x02
|
| 732 |
|
|
#define KBDTEST2_SEL 0x01
|
| 733 |
|
|
#define KBDTEST3_ms_16 0x80
|
| 734 |
|
|
#define KBDTEST3_us_64 0x40
|
| 735 |
|
|
#define KBDTEST3_us_16 0x20
|
| 736 |
|
|
#define KBDTEST3_DIV8 0x10
|
| 737 |
|
|
#define KBDTEST3_DIn 0x08
|
| 738 |
|
|
#define KBDTEST3_CIn 0x04
|
| 739 |
|
|
#define KBDTEST3_KD 0x02
|
| 740 |
|
|
#define KBDTEST3_KC 0x01
|
| 741 |
|
|
#define KBDTEST4_BC12 0x80
|
| 742 |
|
|
#define KBDTEST4_BC11 0x40
|
| 743 |
|
|
#define KBDTEST4_TRES 0x20
|
| 744 |
|
|
#define KBDTEST4_CLKOE 0x10
|
| 745 |
|
|
#define KBDTEST4_CRES 0x08
|
| 746 |
|
|
#define KBDTEST4_RXB 0x04
|
| 747 |
|
|
#define KBDTEST4_TXB 0x02
|
| 748 |
|
|
#define KBDTEST4_SRX 0x01
|
| 749 |
|
|
|
| 750 |
|
|
#define MSETEST1_CD 0x80
|
| 751 |
|
|
#define MSETEST1_RC1 0x40
|
| 752 |
|
|
#define MSETEST1_MC 0x20
|
| 753 |
|
|
#define MSETEST1_C Fld(2,3)
|
| 754 |
|
|
#define MSETEST1_T2 0x40
|
| 755 |
|
|
#define MSETEST1_T1 0x20
|
| 756 |
|
|
#define MSETEST1_T0 0x10
|
| 757 |
|
|
#define MSETEST2_TICBnRES 0x08
|
| 758 |
|
|
#define MSETEST2_RKC 0x04
|
| 759 |
|
|
#define MSETEST2_RKD 0x02
|
| 760 |
|
|
#define MSETEST2_SEL 0x01
|
| 761 |
|
|
#define MSETEST3_ms_16 0x80
|
| 762 |
|
|
#define MSETEST3_us_64 0x40
|
| 763 |
|
|
#define MSETEST3_us_16 0x20
|
| 764 |
|
|
#define MSETEST3_DIV8 0x10
|
| 765 |
|
|
#define MSETEST3_DIn 0x08
|
| 766 |
|
|
#define MSETEST3_CIn 0x04
|
| 767 |
|
|
#define MSETEST3_KD 0x02
|
| 768 |
|
|
#define MSETEST3_KC 0x01
|
| 769 |
|
|
#define MSETEST4_BC12 0x80
|
| 770 |
|
|
#define MSETEST4_BC11 0x40
|
| 771 |
|
|
#define MSETEST4_TRES 0x20
|
| 772 |
|
|
#define MSETEST4_CLKOE 0x10
|
| 773 |
|
|
#define MSETEST4_CRES 0x08
|
| 774 |
|
|
#define MSETEST4_RXB 0x04
|
| 775 |
|
|
#define MSETEST4_TXB 0x02
|
| 776 |
|
|
#define MSETEST4_SRX 0x01
|
| 777 |
|
|
|
| 778 |
|
|
#endif /* LANGUAGE == C */
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
/*
|
| 782 |
|
|
* General-Purpose I/O Interface
|
| 783 |
|
|
*
|
| 784 |
|
|
* Registers
|
| 785 |
|
|
* PADWR Port A Data Write Register
|
| 786 |
|
|
* PBDWR Port B Data Write Register
|
| 787 |
|
|
* PADRR Port A Data Read Register
|
| 788 |
|
|
* PBDRR Port B Data Read Register
|
| 789 |
|
|
* PADDR Port A Data Direction Register
|
| 790 |
|
|
* PBDDR Port B Data Direction Register
|
| 791 |
|
|
* PASSR Port A Sleep State Register
|
| 792 |
|
|
* PBSSR Port B Sleep State Register
|
| 793 |
|
|
*
|
| 794 |
|
|
*/
|
| 795 |
|
|
|
| 796 |
|
|
#define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE )
|
| 797 |
|
|
|
| 798 |
|
|
#define _PADWR _PIO( 0x0000 )
|
| 799 |
|
|
#define _PBDWR _PIO( 0x0400 )
|
| 800 |
|
|
#define _PADRR _PIO( 0x0000 )
|
| 801 |
|
|
#define _PBDRR _PIO( 0x0400 )
|
| 802 |
|
|
#define _PADDR _PIO( 0x0800 )
|
| 803 |
|
|
#define _PBDDR _PIO( 0x0c00 )
|
| 804 |
|
|
#define _PASSR _PIO( 0x1000 )
|
| 805 |
|
|
#define _PBSSR _PIO( 0x1400 )
|
| 806 |
|
|
|
| 807 |
|
|
|
| 808 |
|
|
#if ( LANGUAGE == C )
|
| 809 |
|
|
|
| 810 |
|
|
|
| 811 |
|
|
#define PADWR (*((volatile Word *) SA1101_p2v (_PADWR)))
|
| 812 |
|
|
#define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR)))
|
| 813 |
|
|
#define PADRR (*((volatile Word *) SA1101_p2v (_PADRR)))
|
| 814 |
|
|
#define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR)))
|
| 815 |
|
|
#define PADDR (*((volatile Word *) SA1101_p2v (_PADDR)))
|
| 816 |
|
|
#define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR)))
|
| 817 |
|
|
#define PASSR (*((volatile Word *) SA1101_p2v (_PASSR)))
|
| 818 |
|
|
#define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR)))
|
| 819 |
|
|
|
| 820 |
|
|
#endif
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
|
| 824 |
|
|
/*
|
| 825 |
|
|
* Keypad Interface
|
| 826 |
|
|
*
|
| 827 |
|
|
* Registers
|
| 828 |
|
|
* PXDWR
|
| 829 |
|
|
* PXDRR
|
| 830 |
|
|
* PYDWR
|
| 831 |
|
|
* PYDRR
|
| 832 |
|
|
*
|
| 833 |
|
|
*/
|
| 834 |
|
|
|
| 835 |
|
|
#define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE )
|
| 836 |
|
|
|
| 837 |
|
|
#define _PXDWR _KEYPAD( 0x0000 )
|
| 838 |
|
|
#define _PXDRR _KEYPAD( 0x0000 )
|
| 839 |
|
|
#define _PYDWR _KEYPAD( 0x0400 )
|
| 840 |
|
|
#define _PYDRR _KEYPAD( 0x0400 )
|
| 841 |
|
|
|
| 842 |
|
|
#if ( LANGUAGE == C )
|
| 843 |
|
|
|
| 844 |
|
|
|
| 845 |
|
|
#define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR)))
|
| 846 |
|
|
#define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR)))
|
| 847 |
|
|
#define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR)))
|
| 848 |
|
|
#define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR)))
|
| 849 |
|
|
|
| 850 |
|
|
#endif
|
| 851 |
|
|
|
| 852 |
|
|
|
| 853 |
|
|
|
| 854 |
|
|
/*
|
| 855 |
|
|
* PCMCIA Interface
|
| 856 |
|
|
*
|
| 857 |
|
|
* Registers
|
| 858 |
|
|
* PCSR Status Register
|
| 859 |
|
|
* PCCR Control Register
|
| 860 |
|
|
* PCSSR Sleep State Register
|
| 861 |
|
|
*
|
| 862 |
|
|
*/
|
| 863 |
|
|
|
| 864 |
|
|
#define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE )
|
| 865 |
|
|
|
| 866 |
|
|
#define _PCSR _CARD( 0x0000 )
|
| 867 |
|
|
#define _PCCR _CARD( 0x0400 )
|
| 868 |
|
|
#define _PCSSR _CARD( 0x0800 )
|
| 869 |
|
|
|
| 870 |
|
|
#if ( LANGUAGE == C )
|
| 871 |
|
|
#define PCSR (*((volatile Word *) SA1101_p2v (_PCSR)))
|
| 872 |
|
|
#define PCCR (*((volatile Word *) SA1101_p2v (_PCCR)))
|
| 873 |
|
|
#define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR)))
|
| 874 |
|
|
|
| 875 |
|
|
#define PCSR_S0_ready 0x0001
|
| 876 |
|
|
#define PCSR_S1_ready 0x0002
|
| 877 |
|
|
#define PCSR_S0_detected 0x0004
|
| 878 |
|
|
#define PCSR_S1_detected 0x0008
|
| 879 |
|
|
#define PCSR_S0_VS1 0x0010
|
| 880 |
|
|
#define PCSR_S0_VS2 0x0020
|
| 881 |
|
|
#define PCSR_S1_VS1 0x0040
|
| 882 |
|
|
#define PCSR_S1_VS2 0x0080
|
| 883 |
|
|
#define PCSR_S0_WP 0x0100
|
| 884 |
|
|
#define PCSR_S1_WP 0x0200
|
| 885 |
|
|
#define PCSR_S0_BVD1_nSTSCHG 0x0400
|
| 886 |
|
|
#define PCSR_S0_BVD2_nSPKR 0x0800
|
| 887 |
|
|
#define PCSR_S1_BVD1_nSTSCHG 0x1000
|
| 888 |
|
|
#define PCSR_S1_BVD2_nSPKR 0x2000
|
| 889 |
|
|
|
| 890 |
|
|
#define PCCR_S0_VPP0 0x0001
|
| 891 |
|
|
#define PCCR_S0_VPP1 0x0002
|
| 892 |
|
|
#define PCCR_S0_VCC0 0x0004
|
| 893 |
|
|
#define PCCR_S0_VCC1 0x0008
|
| 894 |
|
|
#define PCCR_S1_VPP0 0x0010
|
| 895 |
|
|
#define PCCR_S1_VPP1 0x0020
|
| 896 |
|
|
#define PCCR_S1_VCC0 0x0040
|
| 897 |
|
|
#define PCCR_S1_VCC1 0x0080
|
| 898 |
|
|
#define PCCR_S0_reset 0x0100
|
| 899 |
|
|
#define PCCR_S1_reset 0x0200
|
| 900 |
|
|
#define PCCR_S0_float 0x0400
|
| 901 |
|
|
#define PCCR_S1_float 0x0800
|
| 902 |
|
|
|
| 903 |
|
|
#define PCSSR_S0_VCC0 0x0001
|
| 904 |
|
|
#define PCSSR_S0_VCC1 0x0002
|
| 905 |
|
|
#define PCSSR_S0_VPP0 0x0004
|
| 906 |
|
|
#define PCSSR_S0_VPP1 0x0008
|
| 907 |
|
|
#define PCSSR_S0_control 0x0010
|
| 908 |
|
|
#define PCSSR_S1_VCC0 0x0020
|
| 909 |
|
|
#define PCSSR_S1_VCC1 0x0040
|
| 910 |
|
|
#define PCSSR_S1_VPP0 0x0080
|
| 911 |
|
|
#define PCSSR_S1_VPP1 0x0100
|
| 912 |
|
|
#define PCSSR_S1_control 0x0200
|
| 913 |
|
|
|
| 914 |
|
|
#endif
|
| 915 |
|
|
|
| 916 |
|
|
#undef C
|
| 917 |
|
|
#undef Assembly
|
