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phoenix |
/*
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* linux/include/asm-arm/arch-sa1100/dma.h
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*
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* Generic SA1100 DMA support
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*
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* Copyright (C) 2000 Nicolas Pitre
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*
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H
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#include <linux/config.h>
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#include "hardware.h"
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/*
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* This is the maximum DMA address that can be DMAd to.
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*/
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#define MAX_DMA_ADDRESS 0xffffffff
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/*
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* The regular generic DMA interface is inappropriate for the
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* SA1100 DMA model. None of the SA1100 specific drivers using
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* DMA are portable anyway so it's pointless to try to twist the
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* regular DMA API to accommodate them.
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*/
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#define MAX_DMA_CHANNELS 0
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/*
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* The SA1100 has six internal DMA channels.
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*/
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#define SA1100_DMA_CHANNELS 6
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/*
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* The SA-1111 SAC has two DMA channels.
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*/
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#define SA1111_SAC_DMA_CHANNELS 2
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#define SA1111_SAC_XMT_CHANNEL 0
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#define SA1111_SAC_RCV_CHANNEL 1
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/*
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* The SA-1111 SAC channels will reside in the same index space as
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* the built-in SA-1100 channels, and will take on the next available
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* identifiers after the 1100.
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*/
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#define SA1111_SAC_DMA_BASE SA1100_DMA_CHANNELS
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#ifdef CONFIG_SA1111
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# define MAX_SA1100_DMA_CHANNELS (SA1100_DMA_CHANNELS + SA1111_SAC_DMA_CHANNELS)
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#else
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# define MAX_SA1100_DMA_CHANNELS SA1100_DMA_CHANNELS
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#endif
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/*
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* All possible SA1100 devices a DMA channel can be attached to.
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*/
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typedef enum {
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DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */
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DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */
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DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */
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DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */
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DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */
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DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */
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DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */
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DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */
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DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */
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DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */
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DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */
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DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */
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DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */
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DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */
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DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */
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DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */
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DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */
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DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */
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} dma_device_t;
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typedef void (*dma_callback_t)( void *buf_id, int size );
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/* SA1100 DMA API */
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extern int sa1100_request_dma( dmach_t *channel, const char *device_id,
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dma_device_t device );
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extern int sa1100_dma_set_callback( dmach_t channel, dma_callback_t cb );
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extern int sa1100_dma_set_spin( dmach_t channel, dma_addr_t addr, int size );
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extern int sa1100_dma_queue_buffer( dmach_t channel, void *buf_id,
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dma_addr_t data, int size );
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extern int sa1100_dma_get_current( dmach_t channel, void **buf_id, dma_addr_t *addr );
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extern int sa1100_dma_stop( dmach_t channel );
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extern int sa1100_dma_resume( dmach_t channel );
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extern int sa1100_dma_flush_all( dmach_t channel );
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extern void sa1100_free_dma( dmach_t channel );
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extern int sa1100_dma_sleep( dmach_t channel );
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extern int sa1100_dma_wakeup( dmach_t channel );
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/* Sa1111 DMA interface (all but registration uses the above) */
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extern int sa1111_sac_request_dma( dmach_t *channel, const char *device_id,
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unsigned int direction );
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extern int sa1111_check_dma_bug( dma_addr_t addr );
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#ifdef CONFIG_SA1111
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static inline void
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__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
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{
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unsigned int sz = 256;
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if (node != 0)
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sz = 0;
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size[1] = size[0] - sz;
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size[0] = sz;
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}
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#define arch_adjust_zones(node,size,holes) __arch_adjust_zones(node,size,holes)
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#endif
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#endif /* _ASM_ARCH_DMA_H */
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