OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-arm/] [arch-tbox/] [hardware.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1276 phoenix
/*
2
 * linux/include/asm-arm/arch-tbox/hardware.h
3
 *
4
 * Copyright (C) 1998, 1999, 2000 Philip Blundell
5
 * Copyright (C) 2000 FutureTV Labs Ltd
6
 *
7
 * This file contains the hardware definitions of the Tbox
8
 */
9
 
10
/*
11
 * This program is free software; you can redistribute it and/or
12
 * modify it under the terms of the GNU General Public License
13
 * as published by the Free Software Foundation; either version
14
 * 2 of the License, or (at your option) any later version.
15
 */
16
 
17
#ifndef __ASM_ARCH_HARDWARE_H
18
#define __ASM_ARCH_HARDWARE_H
19
 
20
/*    Logical    Physical
21
 * 0xfff00000   0x00100000      I/O
22
 * 0xfff00000   0x00100000        Expansion CS0
23
 * 0xfff10000   0x00110000        DMA
24
 * 0xfff20000   0x00120000        C-Cube
25
 * 0xfff30000   0x00130000        FPGA 1
26
 * 0xfff40000   0x00140000        UART 2
27
 * 0xfff50000   0x00150000        UART 1
28
 * 0xfff60000   0x00160000        CS8900
29
 * 0xfff70000   0x00170000        INTCONT
30
 * 0xfff80000   0x00180000        RAMDAC
31
 * 0xfff90000   0x00190000        Control 0
32
 * 0xfffa0000   0x001a0000        Control 1
33
 * 0xfffb0000   0x001b0000        Control 2
34
 * 0xfffc0000   0x001c0000        FPGA 2
35
 * 0xfffd0000   0x001d0000        INTRESET
36
 * 0xfffe0000   0x001e0000        C-Cube DMA throttle
37
 * 0xffff0000   0x001f0000        Expansion CS1
38
 * 0xffe00000   0x82000000      cache flush
39
 */
40
 
41
/*
42
 * Mapping areas
43
 */
44
#define IO_BASE                 0xfff00000
45
#define IO_START                0x00100000
46
#define FLUSH_BASE              0xffe00000
47
 
48
#define INTCONT                 0xfff70000
49
 
50
#define FPGA1CONT               0xffff3000
51
 
52
/*
53
 * RAM definitions
54
 */
55
#define RAM_BASE                0x80000000
56
#define FLUSH_BASE_PHYS         0x82000000
57
 
58
#define UNCACHEABLE_ADDR        INTCONT
59
 
60
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.