| 1 |
1276 |
phoenix |
/*
|
| 2 |
|
|
* linux/include/asm-arm/hardware/serial_omaha.h
|
| 3 |
|
|
*
|
| 4 |
|
|
* Internal header file for Omaha serial ports
|
| 5 |
|
|
*
|
| 6 |
|
|
* Copyright (C) 2002 ARM Limited
|
| 7 |
|
|
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
| 8 |
|
|
*
|
| 9 |
|
|
* This program is free software; you can redistribute it and/or modify
|
| 10 |
|
|
* it under the terms of the GNU General Public License as published by
|
| 11 |
|
|
* the Free Software Foundation; either version 2 of the License, or
|
| 12 |
|
|
* (at your option) any later version.
|
| 13 |
|
|
*
|
| 14 |
|
|
* This program is distributed in the hope that it will be useful,
|
| 15 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 16 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 17 |
|
|
* GNU General Public License for more details.
|
| 18 |
|
|
*
|
| 19 |
|
|
* You should have received a copy of the GNU General Public License
|
| 20 |
|
|
* along with this program; if not, write to the Free Software
|
| 21 |
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
| 22 |
|
|
*/
|
| 23 |
|
|
#ifndef ASM_ARM_HARDWARE_SERIAL_OMAHA_H
|
| 24 |
|
|
#define ASM_ARM_HARDWARE_SERIAL_OMAHA_H
|
| 25 |
|
|
|
| 26 |
|
|
#define OMAHA_UART0_BASE 0x15000000 /* Uart 0 base */
|
| 27 |
|
|
#define OMAHA_UART1_BASE 0x15004000 /* Uart 1 base */
|
| 28 |
|
|
|
| 29 |
|
|
/*
|
| 30 |
|
|
* UART Register Offsets.
|
| 31 |
|
|
*/
|
| 32 |
|
|
#define OMAHA_ULCON 0x00 /* Line control */
|
| 33 |
|
|
#define OMAHA_UCON 0x04 /* Control */
|
| 34 |
|
|
#define OMAHA_UFCON 0x08 /* FIFO control */
|
| 35 |
|
|
#define OMAHA_UMCON 0x0C /* Modem control */
|
| 36 |
|
|
#define OMAHA_UTRSTAT 0x10 /* Rx/Tx status */
|
| 37 |
|
|
#define OMAHA_UERSTAT 0x14 /* Rx Error Status */
|
| 38 |
|
|
#define OMAHA_UFSTAT 0x18 /* FIFO status */
|
| 39 |
|
|
#define OMAHA_UMSTAT 0x1C /* Modem status */
|
| 40 |
|
|
#define OMAHA_UTXH 0x20 /* Transmission Hold (byte wide) */
|
| 41 |
|
|
#define OMAHA_URXH 0x24 /* Receive buffer (byte wide) */
|
| 42 |
|
|
#define OMAHA_UBRDIV 0x28 /* Baud rate divisor */
|
| 43 |
|
|
|
| 44 |
|
|
/* UART status flags in OMAHA_UTRSTAT
|
| 45 |
|
|
*/
|
| 46 |
|
|
#define OMAHA_URX_FULL 0x1 /* Receive buffer has valid data */
|
| 47 |
|
|
#define OMAHA_UTX_EMPTY 0x2 /* Transmitter has finished */
|
| 48 |
|
|
|
| 49 |
|
|
/* UART status flags in UFSTAT */
|
| 50 |
|
|
#define OMAHA_TXFF 0x200 /* TX FIFO Full. */
|
| 51 |
|
|
#define OMAHA_RXFF 0x100 /* RX FIFO Full. */
|
| 52 |
|
|
#define OMAHA_TXFF_CNT 0xF0 /* Tx FIFO count */
|
| 53 |
|
|
#define OMAHA_RXFF_CNT 0x0F /* Rx FIFO count */
|
| 54 |
|
|
|
| 55 |
|
|
/* UART status flags in UERSTAT
|
| 56 |
|
|
*/
|
| 57 |
|
|
#define OMAHA_UART_OVERRUN 0x0
|
| 58 |
|
|
#define OMAHA_UART_PARITY 0x1
|
| 59 |
|
|
#define OMAHA_UART_FRAME 0x2
|
| 60 |
|
|
#define OMAHA_UART_BREAK 0x4
|
| 61 |
|
|
|
| 62 |
|
|
#endif
|
