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phoenix |
#ifndef _I386_PGTABLE_3LEVEL_H
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#define _I386_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT 30
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#define PTRS_PER_PGD 4
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/*
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* PMD_SHIFT determines the size of the area a middle-level
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* page table can map
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*/
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#define PMD_SHIFT 21
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#define PTRS_PER_PMD 512
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/*
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* entries per page directory level
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*/
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#define PTRS_PER_PTE 512
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
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static inline int pgd_none(pgd_t pgd) { return 0; }
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static inline int pgd_bad(pgd_t pgd) { return 0; }
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static inline int pgd_present(pgd_t pgd) { return 1; }
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/* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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static inline void set_pte(pte_t *ptep, pte_t pte)
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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#define set_pmd(pmdptr,pmdval) \
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set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
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#define set_pgd(pgdptr,pgdval) \
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set_64bit((unsigned long long *)(pgdptr),pgd_val(pgdval))
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#define set_pte_atomic(pteptr,pteval) \
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set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
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/*
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* Pentium-II erratum A13: in PAE mode we explicitly have to flush
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* the TLB via cr3 if the top-level pgd is changed...
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* We do not let the generic code free and clear pgd entries due to
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* this erratum.
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*/
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static inline void pgd_clear (pgd_t * pgd) { }
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#define pgd_page(pgd) \
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((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(dir, address) ((pmd_t *) pgd_page(*(dir)) + \
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__pmd_offset(address))
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static inline pte_t ptep_get_and_clear(pte_t *ptep)
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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return res;
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}
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static inline int pte_same(pte_t a, pte_t b)
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{
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return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
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}
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#define pte_page(x) (mem_map+(((x).pte_low >> PAGE_SHIFT) | ((x).pte_high << (32 - PAGE_SHIFT))))
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#define pte_none(x) (!(x).pte_low && !(x).pte_high)
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static inline pte_t __mk_pte(unsigned long page_nr, pgprot_t pgprot)
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{
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pte_t pte;
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pte.pte_high = page_nr >> (32 - PAGE_SHIFT);
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pte.pte_low = (page_nr << PAGE_SHIFT) | pgprot_val(pgprot);
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return pte;
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}
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#endif /* _I386_PGTABLE_3LEVEL_H */
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