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1275 |
phoenix |
#ifndef __ASM_SMP_H
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#define __ASM_SMP_H
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/*
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* We need the APIC definitions automatically as part of 'smp.h'
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*/
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#ifndef __ASSEMBLY__
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <linux/ptrace.h>
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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#ifndef __ASSEMBLY__
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#include <asm/fixmap.h>
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#include <asm/bitops.h>
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#include <asm/mpspec.h>
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#ifdef CONFIG_X86_IO_APIC
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#include <asm/io_apic.h>
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#endif
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#include <asm/apic.h>
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#endif
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#endif
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#ifdef CONFIG_SMP
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#ifndef __ASSEMBLY__
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/*
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* Private routines/data
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*/
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extern void smp_alloc_memory(void);
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extern unsigned long phys_cpu_present_map;
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extern unsigned long cpu_online_map;
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extern volatile unsigned long smp_invalidate_needed;
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extern int pic_mode;
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extern int smp_num_siblings;
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extern int cpu_sibling_map[];
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extern void smp_flush_tlb(void);
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extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
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extern void smp_send_reschedule(int cpu);
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extern void smp_invalidate_rcv(void); /* Process an NMI */
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extern void (*mtrr_hook) (void);
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extern void zap_low_mappings (void);
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/*
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* On x86 all CPUs are mapped 1:1 to the APIC space.
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* This simplifies scheduling and IPI sending and
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* compresses data structures.
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*/
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static inline int cpu_logical_map(int cpu)
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{
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return cpu;
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}
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static inline int cpu_number_map(int cpu)
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{
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return cpu;
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}
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/*
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* Some lowlevel functions might want to know about
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* the real APIC ID <-> CPU # mapping.
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*/
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#define MAX_APICID 256
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extern volatile int cpu_to_physical_apicid[NR_CPUS];
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extern volatile int physical_apicid_to_cpu[MAX_APICID];
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extern volatile int cpu_to_logical_apicid[NR_CPUS];
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extern volatile int logical_apicid_to_cpu[MAX_APICID];
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/*
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* General functions that each host system must provide.
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*/
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extern void smp_boot_cpus(void);
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extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
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/*
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* This function is needed by all SMP systems. It must _always_ be valid
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* from the initial startup. We map APIC_BASE very early in page_setup(),
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* so this is correct in the x86 case.
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*/
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#define smp_processor_id() (current->processor)
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static __inline int hard_smp_processor_id(void)
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{
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/* we don't want to mark this access volatile - bad code generation */
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return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID));
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}
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static __inline int logical_smp_processor_id(void)
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{
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/* we don't want to mark this access volatile - bad code generation */
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return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
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}
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#endif /* !__ASSEMBLY__ */
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#define NO_PROC_ID 0xFF /* No processor magic marker */
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/*
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* This magic constant controls our willingness to transfer
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* a process across CPUs. Such a transfer incurs misses on the L1
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* cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
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* gut feeling is this will vary by board in value. For a board
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* with separate L2 cache it probably depends also on the RSS, and
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* for a board with shared L2 cache it ought to decay fast as other
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* processes are run.
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*/
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#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
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#endif
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#endif
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