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1275 |
phoenix |
/*
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* File: mca_asm.h
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*
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) Vijay Chander (vijay@engr.sgi.com)
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* Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
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* Copyright (C) 2000 Hewlett-Packard Co.
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* Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 2002 Intel Corp.
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* Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
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*/
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#ifndef _ASM_IA64_MCA_ASM_H
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#define _ASM_IA64_MCA_ASM_H
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#define PSR_IC 13
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#define PSR_I 14
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#define PSR_DT 17
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#define PSR_RT 27
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#define PSR_MC 35
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#define PSR_IT 36
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#define PSR_BN 44
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/*
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* This macro converts a instruction virtual address to a physical address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Lop off bits 61 thru 63 in the virtual address
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*/
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#define INST_VA_TO_PA(addr) \
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dep addr = 0, addr, 61, 3
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/*
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* This macro converts a data virtual address to a physical address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Lop off bits 61 thru 63 in the virtual address
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*/
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#define DATA_VA_TO_PA(addr) \
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dep addr = 0, addr, 61, 3
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/*
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* This macro converts a data physical address to a virtual address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Put 0x7 in bits 61 thru 63.
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*/
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#define DATA_PA_TO_VA(addr,temp) \
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mov temp = 0x7 ;; \
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dep addr = temp, addr, 61, 3
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/*
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* This macro jumps to the instruction at the given virtual address
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* and starts execution in physical mode with all the address
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* translations turned off.
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* 1. Save the current psr
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* 2. Make sure that all the upper 32 bits are off
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*
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* 3. Clear the interrupt enable and interrupt state collection bits
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* in the psr before updating the ipsr and iip.
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*
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* 4. Turn off the instruction, data and rse translation bits of the psr
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* and store the new value into ipsr
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* Also make sure that the interrupts are disabled.
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* Ensure that we are in little endian mode.
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* [psr.{rt, it, dt, i, be} = 0]
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*
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* 5. Get the physical address corresponding to the virtual address
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* of the next instruction bundle and put it in iip.
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* (Using magic numbers 24 and 40 in the deposint instruction since
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* the IA64_SDK code directly maps to lower 24bits as physical address
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* from a virtual address).
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*
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* 6. Do an rfi to move the values from ipsr to psr and iip to ip.
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*/
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#define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
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mov old_psr = psr; \
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;; \
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dep old_psr = 0, old_psr, 32, 32; \
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\
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mov ar.rsc = 0 ; \
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;; \
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srlz.d; \
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mov temp2 = ar.bspstore; \
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;; \
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DATA_VA_TO_PA(temp2); \
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;; \
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mov temp1 = ar.rnat; \
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;; \
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mov ar.bspstore = temp2; \
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;; \
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mov ar.rnat = temp1; \
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mov temp1 = psr; \
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mov temp2 = psr; \
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;; \
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\
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dep temp2 = 0, temp2, PSR_IC, 2; \
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;; \
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mov psr.l = temp2; \
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;; \
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srlz.d; \
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dep temp1 = 0, temp1, 32, 32; \
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;; \
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dep temp1 = 0, temp1, PSR_IT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_DT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_RT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_I, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_IC, 1; \
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;; \
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dep temp1 = -1, temp1, PSR_MC, 1; \
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;; \
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movl temp2 = start_addr; \
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mov cr.ipsr = temp1; \
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;; \
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INST_VA_TO_PA(temp2); \
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;; \
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mov cr.iip = temp2; \
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mov cr.ifs = r0; \
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DATA_VA_TO_PA(sp); \
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DATA_VA_TO_PA(gp); \
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;; \
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srlz.i; \
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;; \
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nop 1; \
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nop 2; \
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nop 1; \
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nop 2; \
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rfi; \
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;;
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/*
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* This macro jumps to the instruction at the given virtual address
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* and starts execution in virtual mode with all the address
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* translations turned on.
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* 1. Get the old saved psr
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*
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* 2. Clear the interrupt state collection bit in the current psr.
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*
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* 3. Set the instruction translation bit back in the old psr
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* Note we have to do this since we are right now saving only the
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* lower 32-bits of old psr.(Also the old psr has the data and
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* rse translation bits on)
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*
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* 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
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*
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* 5. Reset the current thread pointer (r13).
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*
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* 6. Set iip to the virtual address of the next instruction bundle.
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*
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* 7. Do an rfi to move ipsr to psr and iip to ip.
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*/
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#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
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mov temp2 = psr; \
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;; \
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mov old_psr = temp2; \
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;; \
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dep temp2 = 0, temp2, PSR_IC, 2; \
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;; \
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mov psr.l = temp2; \
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mov ar.rsc = 0; \
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;; \
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srlz.d; \
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mov r13 = ar.k6; \
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;; \
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DATA_PA_TO_VA(r13,temp1); \
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;; \
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mov temp2 = ar.bspstore; \
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;; \
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DATA_PA_TO_VA(temp2,temp1); \
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;; \
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mov temp1 = ar.rnat; \
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;; \
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mov ar.bspstore = temp2; \
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;; \
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mov ar.rnat = temp1; \
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;; \
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mov temp1 = old_psr; \
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;; \
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mov temp2 = 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_IC, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_IT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_DT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_RT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_BN, 1; \
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;; \
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\
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mov cr.ipsr = temp1; \
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movl temp2 = start_addr; \
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;; \
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mov cr.iip = temp2; \
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;; \
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DATA_PA_TO_VA(sp, temp1); \
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DATA_PA_TO_VA(gp, temp2); \
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srlz.i; \
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;; \
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nop 1; \
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nop 2; \
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nop 1; \
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rfi \
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;;
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/*
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* The following offsets capture the order in which the
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* RSE related registers from the old context are
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* saved onto the new stack frame.
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*
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* +-----------------------+
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* |NDIRTY_WORDS |
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* | [BSP - BSPSTORE]|
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* +-----------------------+
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* | RNAT |
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* +-----------------------+
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* | BSPSTORE |
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* +-----------------------+
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* | IFS |
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* +-----------------------+
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* | PFS |
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* +-----------------------+
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* | RSC |
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* +-----------------------+ <-------- Bottom of new stack frame
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*/
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#define rse_rsc_offset 0
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#define rse_pfs_offset (rse_rsc_offset+0x08)
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#define rse_ifs_offset (rse_pfs_offset+0x08)
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#define rse_bspstore_offset (rse_ifs_offset+0x08)
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#define rse_rnat_offset (rse_bspstore_offset+0x08)
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#define rse_ndirty_words_offset (rse_rnat_offset+0x08)
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/*
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* rse_switch_context
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*
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* 1. Save old RSC onto the new stack frame
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* 2. Save PFS onto new stack frame
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* 3. Cover the old frame and start a new frame.
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* 4. Save IFS onto new stack frame
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* 5. Save the old BSPSTORE on the new stack frame
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* 6. Save the old RNAT on the new stack frame
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* 7. Write BSPSTORE with the new backing store pointer
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* 8. Read and save the new BSP to calculate the #dirty registers
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* NOTE: Look at section 6.11 in Intel IA-64 Architecture Software Developer's
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* Manual, Volume 2, System Architecture.
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*/
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#define rse_switch_context(temp,p_stackframe,p_bspstore) \
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;; \
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mov temp=ar.rsc;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.pfs;; \
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st8 [p_stackframe]=temp,8; \
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cover ;; \
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mov temp=cr.ifs;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.bspstore;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.rnat;; \
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st8 [p_stackframe]=temp,8; \
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mov ar.bspstore=p_bspstore;; \
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mov temp=ar.bsp;; \
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sub temp=temp,p_bspstore;; \
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st8 [p_stackframe]=temp,8;;
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/*
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* rse_return_context
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* 1. Allocate a zero-sized frame
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* 2. Store the number of dirty registers RSC.loadrs field
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* 3. Issue a loadrs to insure that any registers from the interrupted
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* context which were saved on the new stack frame have been loaded
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* back into the stacked registers
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* 4. Restore BSPSTORE
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* 5. Restore RNAT
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* 6. Restore PFS
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* 7. Restore IFS
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* 8. Restore RSC
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* 9. Issue an RFI
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*/
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#define rse_return_context(psr_mask_reg,temp,p_stackframe) \
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;; \
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alloc temp=ar.pfs,0,0,0,0; \
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add p_stackframe=rse_ndirty_words_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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shl temp=temp,16;; \
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mov ar.rsc=temp;; \
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loadrs;; \
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add p_stackframe=-rse_ndirty_words_offset+rse_bspstore_offset,p_stackframe;;\
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ld8 temp=[p_stackframe];; \
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mov ar.bspstore=temp;; \
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add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
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ld8 temp=[p_stackframe];; \
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mov ar.rnat=temp;; \
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add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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| 298 |
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mov ar.pfs=temp;; \
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add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
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| 300 |
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ld8 temp=[p_stackframe];; \
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mov cr.ifs=temp;; \
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| 302 |
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add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
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| 303 |
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ld8 temp=[p_stackframe];; \
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| 304 |
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mov ar.rsc=temp ; \
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| 305 |
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mov temp=psr;; \
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| 306 |
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or temp=temp,psr_mask_reg;; \
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| 307 |
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mov cr.ipsr=temp;; \
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mov temp=ip;; \
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| 309 |
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add temp=0x30,temp;; \
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mov cr.iip=temp;; \
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srlz.i;; \
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rfi;;
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| 313 |
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#endif /* _ASM_IA64_MCA_ASM_H */
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