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1275 |
phoenix |
/*
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* Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
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* Mountain View, CA 94043, or:
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*
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* http://www.sgi.com
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*
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*/
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#ifndef _ASM_IA64_SN_IOC4_H
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#define _ASM_IA64_SN_IOC4_H
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/*
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* ioc4.h - IOC4 chip header file
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*/
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/* Notes:
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* The IOC4 chip is a 32-bit PCI device that provides 4 serial ports,
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* an IDE bus interface, a PC keyboard/mouse interface, and a real-time
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* external interrupt interface.
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*
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* It includes an optimized DMA buffer management, and a store-and-forward
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* buffer RAM.
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*
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* All IOC4 registers are 32 bits wide.
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*/
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typedef uint32_t ioc4reg_t;
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/*
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* PCI Configuration Space Register Address Map, use offset from IOC4 PCI
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* configuration base such that this can be used for multiple IOC4s
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*/
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#define IOC4_PCI_ID 0x0 /* ID */
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#define IOC4_VENDOR_ID_NUM 0x10A9
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#define IOC4_DEVICE_ID_NUM 0x100A
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#define IOC4_ADDRSPACE_MASK 0xfff00000ULL
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#define IOC4_PCI_SCR 0x4 /* Status/Command */
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#define IOC4_PCI_REV 0x8 /* Revision */
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#define IOC4_PCI_LAT 0xC /* Latency Timer */
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#define IOC4_PCI_BAR0 0x10 /* IOC4 base address 0 */
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#define IOC4_PCI_SIDV 0x2c /* Subsys ID and vendor */
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#define IOC4_PCI_CAP 0x34 /* Capability pointer */
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#define IOC4_PCI_LATGNTINT 0x3c /* Max_lat, min_gnt, int_pin, int_line */
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/*
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* PCI Memory Space Map
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*/
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#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
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#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
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#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
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#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
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#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
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#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
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#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
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/* Master IDs contained in PCI_ERR_ADDR_MST_ID_MSK */
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#define IOC4_MST_ID_S0_TX 0
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#define IOC4_MST_ID_S0_RX 1
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#define IOC4_MST_ID_S1_TX 2
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#define IOC4_MST_ID_S1_RX 3
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#define IOC4_MST_ID_S2_TX 4
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#define IOC4_MST_ID_S2_RX 5
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#define IOC4_MST_ID_S3_TX 6
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#define IOC4_MST_ID_S3_RX 7
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#define IOC4_MST_ID_ATA 8
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#define IOC4_PCI_ERR_ADDR_H 0x004 /* High Error Address */
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#define IOC4_SIO_IR 0x008 /* SIO Interrupt Register */
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#define IOC4_OTHER_IR 0x00C /* Other Interrupt Register */
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/* These registers are read-only for general kernel code. To modify
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* them use the functions in ioc4.c
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*/
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#define IOC4_SIO_IES_RO 0x010 /* SIO Interrupt Enable Set Reg */
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#define IOC4_OTHER_IES_RO 0x014 /* Other Interrupt Enable Set Reg */
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#define IOC4_SIO_IEC_RO 0x018 /* SIO Interrupt Enable Clear Reg */
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#define IOC4_OTHER_IEC_RO 0x01C /* Other Interrupt Enable Clear Reg */
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#define IOC4_SIO_CR 0x020 /* SIO Control Reg */
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#define IOC4_INT_OUT 0x028 /* INT_OUT Reg (realtime interrupt) */
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#define IOC4_GPCR_S 0x030 /* GenericPIO Cntrl Set Register */
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#define IOC4_GPCR_C 0x034 /* GenericPIO Cntrl Clear Register */
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#define IOC4_GPDR 0x038 /* GenericPIO Data Register */
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#define IOC4_GPPR_0 0x040 /* GenericPIO Pin Registers */
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#define IOC4_GPPR_OFF 0x4
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#define IOC4_GPPR(x) (IOC4_GPPR_0+(x)*IOC4_GPPR_OFF)
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/* ATAPI Registers */
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#define IOC4_ATA_0 0x100 /* Data w/timing */
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#define IOC4_ATA_1 0x104 /* Error/Features w/timing */
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#define IOC4_ATA_2 0x108 /* Sector Count w/timing */
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#define IOC4_ATA_3 0x10C /* Sector Number w/timing */
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#define IOC4_ATA_4 0x110 /* Cyliner Low w/timing */
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#define IOC4_ATA_5 0x114 /* Cylinder High w/timing */
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#define IOC4_ATA_6 0x118 /* Device/Head w/timing */
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#define IOC4_ATA_7 0x11C /* Status/Command w/timing */
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#define IOC4_ATA_0_AUX 0x120 /* Aux Status/Device Cntrl w/timing */
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#define IOC4_ATA_TIMING 0x140 /* Timing value register 0 */
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#define IOC4_ATA_DMA_PTR_L 0x144 /* Low Memory Pointer to DMA List */
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#define IOC4_ATA_DMA_PTR_H 0x148 /* High Memory Pointer to DMA List */
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#define IOC4_ATA_DMA_ADDR_L 0x14C /* Low Memory DMA Address */
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#define IOC4_ATA_DMA_ADDR_H 0x150 /* High Memory DMA Addresss */
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#define IOC4_ATA_BC_DEV 0x154 /* DMA Byte Count at Device */
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#define IOC4_ATA_BC_MEM 0x158 /* DMA Byte Count at Memory */
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#define IOC4_ATA_DMA_CTRL 0x15C /* DMA Control/Status */
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/* Keyboard and Mouse Registers */
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#define IOC4_KM_CSR 0x200 /* Kbd and Mouse Cntrl/Status Reg */
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#define IOC4_K_RD 0x204 /* Kbd Read Data Register */
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#define IOC4_M_RD 0x208 /* Mouse Read Data Register */
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#define IOC4_K_WD 0x20C /* Kbd Write Data Register */
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#define IOC4_M_WD 0x210 /* Mouse Write Data Register */
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/* Serial Port Registers used for DMA mode serial I/O */
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#define IOC4_SBBR01_H 0x300 /* Serial Port Ring Buffers
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Base Reg High for Channels 0 1*/
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#define IOC4_SBBR01_L 0x304 /* Serial Port Ring Buffers
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Base Reg Low for Channels 0 1 */
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#define IOC4_SBBR23_H 0x308 /* Serial Port Ring Buffers
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Base Reg High for Channels 2 3*/
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#define IOC4_SBBR23_L 0x30C /* Serial Port Ring Buffers
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Base Reg Low for Channels 2 3 */
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#define IOC4_SSCR_0 0x310 /* Serial Port 0 Control */
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#define IOC4_STPIR_0 0x314 /* Serial Port 0 TX Produce */
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#define IOC4_STCIR_0 0x318 /* Serial Port 0 TX Consume */
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#define IOC4_SRPIR_0 0x31C /* Serial Port 0 RX Produce */
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#define IOC4_SRCIR_0 0x320 /* Serial Port 0 RX Consume */
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#define IOC4_SRTR_0 0x324 /* Serial Port 0 Receive Timer Reg */
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#define IOC4_SHADOW_0 0x328 /* Serial Port 0 16550 Shadow Reg */
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#define IOC4_SSCR_1 0x32C /* Serial Port 1 Control */
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#define IOC4_STPIR_1 0x330 /* Serial Port 1 TX Produce */
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#define IOC4_STCIR_1 0x334 /* Serial Port 1 TX Consume */
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#define IOC4_SRPIR_1 0x338 /* Serial Port 1 RX Produce */
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#define IOC4_SRCIR_1 0x33C /* Serial Port 1 RX Consume */
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#define IOC4_SRTR_1 0x340 /* Serial Port 1 Receive Timer Reg */
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#define IOC4_SHADOW_1 0x344 /* Serial Port 1 16550 Shadow Reg */
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#define IOC4_SSCR_2 0x348 /* Serial Port 2 Control */
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#define IOC4_STPIR_2 0x34C /* Serial Port 2 TX Produce */
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#define IOC4_STCIR_2 0x350 /* Serial Port 2 TX Consume */
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#define IOC4_SRPIR_2 0x354 /* Serial Port 2 RX Produce */
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#define IOC4_SRCIR_2 0x358 /* Serial Port 2 RX Consume */
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#define IOC4_SRTR_2 0x35C /* Serial Port 2 Receive Timer Reg */
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#define IOC4_SHADOW_2 0x360 /* Serial Port 2 16550 Shadow Reg */
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#define IOC4_SSCR_3 0x364 /* Serial Port 3 Control */
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#define IOC4_STPIR_3 0x368 /* Serial Port 3 TX Produce */
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#define IOC4_STCIR_3 0x36C /* Serial Port 3 TX Consume */
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#define IOC4_SRPIR_3 0x370 /* Serial Port 3 RX Produce */
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#define IOC4_SRCIR_3 0x374 /* Serial Port 3 RX Consume */
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#define IOC4_SRTR_3 0x378 /* Serial Port 3 Receive Timer Reg */
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#define IOC4_SHADOW_3 0x37C /* Serial Port 3 16550 Shadow Reg */
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#define IOC4_UART0_BASE 0x380 /* UART 0 */
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#define IOC4_UART1_BASE 0x388 /* UART 1 */
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#define IOC4_UART2_BASE 0x390 /* UART 2 */
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#define IOC4_UART3_BASE 0x398 /* UART 3 */
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/* Private page address aliases for usermode mapping */
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#define IOC4_INT_OUT_P 0x04000 /* INT_OUT Reg */
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#define IOC4_SSCR_0_P 0x08000 /* Serial Port 0 */
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#define IOC4_STPIR_0_P 0x08004
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#define IOC4_STCIR_0_P 0x08008 /* (read-only) */
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#define IOC4_SRPIR_0_P 0x0800C /* (read-only) */
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#define IOC4_SRCIR_0_P 0x08010
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#define IOC4_SRTR_0_P 0x08014
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#define IOC4_UART_LSMSMCR_0_P 0x08018 /* (read-only) */
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#define IOC4_SSCR_1_P 0x0C000 /* Serial Port 1 */
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#define IOC4_STPIR_1_P 0x0C004
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#define IOC4_STCIR_1_P 0x0C008 /* (read-only) */
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#define IOC4_SRPIR_1_P 0x0C00C /* (read-only) */
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#define IOC4_SRCIR_1_P 0x0C010
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#define IOC4_SRTR_1_P 0x0C014
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#define IOC4_UART_LSMSMCR_1_P 0x0C018 /* (read-only) */
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#define IOC4_SSCR_2_P 0x10000 /* Serial Port 2 */
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#define IOC4_STPIR_2_P 0x10004
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#define IOC4_STCIR_2_P 0x10008 /* (read-only) */
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#define IOC4_SRPIR_2_P 0x1000C /* (read-only) */
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#define IOC4_SRCIR_2_P 0x10010
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#define IOC4_SRTR_2_P 0x10014
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#define IOC4_UART_LSMSMCR_2_P 0x10018 /* (read-only) */
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#define IOC4_SSCR_3_P 0x14000 /* Serial Port 3 */
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#define IOC4_STPIR_3_P 0x14004
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#define IOC4_STCIR_3_P 0x14008 /* (read-only) */
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#define IOC4_SRPIR_3_P 0x1400C /* (read-only) */
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#define IOC4_SRCIR_3_P 0x14010
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#define IOC4_SRTR_3_P 0x14014
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#define IOC4_UART_LSMSMCR_3_P 0x14018 /* (read-only) */
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#define IOC4_ALIAS_PAGE_SIZE 0x4000
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/* Interrupt types */
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typedef enum ioc4_intr_type_e {
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ioc4_sio_intr_type,
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ioc4_other_intr_type,
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ioc4_num_intr_types
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} ioc4_intr_type_t;
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#define ioc4_first_intr_type ioc4_sio_intr_type
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/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
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#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
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#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
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#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
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#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
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#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
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#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
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#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
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#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
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#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
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#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
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#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
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#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
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#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
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#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
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#define IOC4_SIO_IR_S1_INT 0x00004000 /* */
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#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
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#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
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#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
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#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
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#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
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#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
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#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
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#define IOC4_SIO_IR_S2_INT 0x00400000 /* */
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#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
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#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
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#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
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#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
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#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
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|
|
#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
|
| 260 |
|
|
#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
|
| 261 |
|
|
#define IOC4_SIO_IR_S3_INT 0x40000000 /* */
|
| 262 |
|
|
#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
|
| 263 |
|
|
|
| 264 |
|
|
/* Per device interrupt masks */
|
| 265 |
|
|
#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
|
| 266 |
|
|
IOC4_SIO_IR_S0_RX_FULL | \
|
| 267 |
|
|
IOC4_SIO_IR_S0_RX_HIGH | \
|
| 268 |
|
|
IOC4_SIO_IR_S0_RX_TIMER | \
|
| 269 |
|
|
IOC4_SIO_IR_S0_DELTA_DCD | \
|
| 270 |
|
|
IOC4_SIO_IR_S0_DELTA_CTS | \
|
| 271 |
|
|
IOC4_SIO_IR_S0_INT | \
|
| 272 |
|
|
IOC4_SIO_IR_S0_TX_EXPLICIT)
|
| 273 |
|
|
#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
|
| 274 |
|
|
IOC4_SIO_IR_S1_RX_FULL | \
|
| 275 |
|
|
IOC4_SIO_IR_S1_RX_HIGH | \
|
| 276 |
|
|
IOC4_SIO_IR_S1_RX_TIMER | \
|
| 277 |
|
|
IOC4_SIO_IR_S1_DELTA_DCD | \
|
| 278 |
|
|
IOC4_SIO_IR_S1_DELTA_CTS | \
|
| 279 |
|
|
IOC4_SIO_IR_S1_INT | \
|
| 280 |
|
|
IOC4_SIO_IR_S1_TX_EXPLICIT)
|
| 281 |
|
|
#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
|
| 282 |
|
|
IOC4_SIO_IR_S2_RX_FULL | \
|
| 283 |
|
|
IOC4_SIO_IR_S2_RX_HIGH | \
|
| 284 |
|
|
IOC4_SIO_IR_S2_RX_TIMER | \
|
| 285 |
|
|
IOC4_SIO_IR_S2_DELTA_DCD | \
|
| 286 |
|
|
IOC4_SIO_IR_S2_DELTA_CTS | \
|
| 287 |
|
|
IOC4_SIO_IR_S2_INT | \
|
| 288 |
|
|
IOC4_SIO_IR_S2_TX_EXPLICIT)
|
| 289 |
|
|
#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
|
| 290 |
|
|
IOC4_SIO_IR_S3_RX_FULL | \
|
| 291 |
|
|
IOC4_SIO_IR_S3_RX_HIGH | \
|
| 292 |
|
|
IOC4_SIO_IR_S3_RX_TIMER | \
|
| 293 |
|
|
IOC4_SIO_IR_S3_DELTA_DCD | \
|
| 294 |
|
|
IOC4_SIO_IR_S3_DELTA_CTS | \
|
| 295 |
|
|
IOC4_SIO_IR_S3_INT | \
|
| 296 |
|
|
IOC4_SIO_IR_S3_TX_EXPLICIT)
|
| 297 |
|
|
|
| 298 |
|
|
/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
|
| 299 |
|
|
#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
|
| 300 |
|
|
#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
|
| 301 |
|
|
#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
|
| 302 |
|
|
#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
|
| 303 |
|
|
#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
|
| 304 |
|
|
#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
|
| 305 |
|
|
#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Kbd/mouse intr */
|
| 306 |
|
|
#define IOC4_OTHER_IR_ATA_DMAINT 0x00000089 /* ATAPI DMA intr */
|
| 307 |
|
|
#define IOC4_OTHER_IR_RT_INT 0x00800000 /* RT output pulse */
|
| 308 |
|
|
#define IOC4_OTHER_IR_GEN_INT1 0x02000000 /* RT input pulse */
|
| 309 |
|
|
#define IOC4_OTHER_IR_GEN_INT_SHIFT 25
|
| 310 |
|
|
|
| 311 |
|
|
/* Per device interrupt masks */
|
| 312 |
|
|
#define IOC4_OTHER_IR_ATA (IOC4_OTHER_IR_ATA_INT | \
|
| 313 |
|
|
IOC4_OTHER_IR_ATA_MEMERR | \
|
| 314 |
|
|
IOC4_OTHER_IR_ATA_DMAINT)
|
| 315 |
|
|
#define IOC4_OTHER_IR_RT (IOC4_OTHER_IR_RT_INT | IOC4_OTHER_IR_GEN_INT1)
|
| 316 |
|
|
|
| 317 |
|
|
/* Macro to load pending interrupts */
|
| 318 |
|
|
#define IOC4_PENDING_SIO_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
|
| 319 |
|
|
PCI_INW(&((mem)->sio_ies_ro)))
|
| 320 |
|
|
#define IOC4_PENDING_OTHER_INTRS(mem) (PCI_INW(&((mem)->other_ir)) & \
|
| 321 |
|
|
PCI_INW(&((mem)->other_ies_ro)))
|
| 322 |
|
|
|
| 323 |
|
|
/* Bitmasks for IOC4_SIO_CR */
|
| 324 |
|
|
#define IOC4_SIO_SR_CMD_PULSE 0x00000004 /* Byte bus strobe length */
|
| 325 |
|
|
#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0
|
| 326 |
|
|
#define IOC4_SIO_CR_ARB_DIAG 0x00000070 /* Current non-ATA PCI bus
|
| 327 |
|
|
requester (ro) */
|
| 328 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
|
| 329 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
|
| 330 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
|
| 331 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
|
| 332 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
|
| 333 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
|
| 334 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
|
| 335 |
|
|
#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
|
| 336 |
|
|
#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
|
| 337 |
|
|
serial ports (ro) */
|
| 338 |
|
|
#define IOC4_SIO_CR_ATA_DIAG_IDLE 0x00000100 /* 0 -> active request from
|
| 339 |
|
|
ATA port */
|
| 340 |
|
|
#define IOC4_SIO_CR_ATA_DIAG_ACTIVE 0x00000200 /* 1 -> ATA request is winner */
|
| 341 |
|
|
|
| 342 |
|
|
/* Bitmasks for IOC4_INT_OUT */
|
| 343 |
|
|
#define IOC4_INT_OUT_COUNT 0x0000ffff /* Pulse interval timer */
|
| 344 |
|
|
#define IOC4_INT_OUT_MODE 0x00070000 /* Mode mask */
|
| 345 |
|
|
#define IOC4_INT_OUT_MODE_0 0x00000000 /* Set output to 0 */
|
| 346 |
|
|
#define IOC4_INT_OUT_MODE_1 0x00040000 /* Set output to 1 */
|
| 347 |
|
|
#define IOC4_INT_OUT_MODE_1PULSE 0x00050000 /* Send 1 pulse */
|
| 348 |
|
|
#define IOC4_INT_OUT_MODE_PULSES 0x00060000 /* Send 1 pulse every interval */
|
| 349 |
|
|
#define IOC4_INT_OUT_MODE_SQW 0x00070000 /* Toggle output every interval */
|
| 350 |
|
|
#define IOC4_INT_OUT_DIAG 0x40000000 /* Diag mode */
|
| 351 |
|
|
#define IOC4_INT_OUT_INT_OUT 0x80000000 /* Current state of INT_OUT */
|
| 352 |
|
|
|
| 353 |
|
|
/* Time constants for IOC4_INT_OUT */
|
| 354 |
|
|
#define IOC4_INT_OUT_NS_PER_TICK (15 * 520) /* 15 ns PCI clock, multi=520 */
|
| 355 |
|
|
#define IOC4_INT_OUT_TICKS_PER_PULSE 3 /* Outgoing pulse lasts 3
|
| 356 |
|
|
ticks */
|
| 357 |
|
|
#define IOC4_INT_OUT_US_TO_COUNT(x) /* Convert uS to a count value */ \
|
| 358 |
|
|
(((x) * 10 + IOC4_INT_OUT_NS_PER_TICK / 200) * \
|
| 359 |
|
|
100 / IOC4_INT_OUT_NS_PER_TICK - 1)
|
| 360 |
|
|
#define IOC4_INT_OUT_COUNT_TO_US(x) /* Convert count value to uS */ \
|
| 361 |
|
|
(((x) + 1) * IOC4_INT_OUT_NS_PER_TICK / 1000)
|
| 362 |
|
|
#define IOC4_INT_OUT_MIN_TICKS 3 /* Min period is width of
|
| 363 |
|
|
pulse in "ticks" */
|
| 364 |
|
|
#define IOC4_INT_OUT_MAX_TICKS IOC4_INT_OUT_COUNT /* Largest possible count */
|
| 365 |
|
|
|
| 366 |
|
|
/* Bitmasks for IOC4_GPCR */
|
| 367 |
|
|
#define IOC4_GPCR_DIR 0x000000ff /* Tristate pin in or out */
|
| 368 |
|
|
#define IOC4_GPCR_DIR_PIN(x) (1<<(x)) /* Access one of the DIR bits */
|
| 369 |
|
|
#define IOC4_GPCR_EDGE 0x0000ff00 /* Extint edge or level
|
| 370 |
|
|
sensitive */
|
| 371 |
|
|
#define IOC4_GPCR_EDGE_PIN(x) (1<<((x)+7 )) /* Access one of the EDGE bits */
|
| 372 |
|
|
|
| 373 |
|
|
/* Values for IOC4_GPCR */
|
| 374 |
|
|
#define IOC4_GPCR_INT_OUT_EN 0x00100000 /* Enable INT_OUT to pin 0 */
|
| 375 |
|
|
#define IOC4_GPCR_DIR_SER0_XCVR 0x00000010 /* Port 0 Transceiver select
|
| 376 |
|
|
enable */
|
| 377 |
|
|
#define IOC4_GPCR_DIR_SER1_XCVR 0x00000020 /* Port 1 Transceiver select
|
| 378 |
|
|
enable */
|
| 379 |
|
|
#define IOC4_GPCR_DIR_SER2_XCVR 0x00000040 /* Port 2 Transceiver select
|
| 380 |
|
|
enable */
|
| 381 |
|
|
#define IOC4_GPCR_DIR_SER3_XCVR 0x00000080 /* Port 3 Transceiver select
|
| 382 |
|
|
enable */
|
| 383 |
|
|
|
| 384 |
|
|
/* Defs for some of the generic I/O pins */
|
| 385 |
|
|
#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
|
| 386 |
|
|
mode sel */
|
| 387 |
|
|
#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
|
| 388 |
|
|
mode sel */
|
| 389 |
|
|
#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
|
| 390 |
|
|
mode sel */
|
| 391 |
|
|
#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
|
| 392 |
|
|
mode sel */
|
| 393 |
|
|
|
| 394 |
|
|
#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
|
| 395 |
|
|
uart 0 mode select */
|
| 396 |
|
|
#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
|
| 397 |
|
|
uart 1 mode select */
|
| 398 |
|
|
#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
|
| 399 |
|
|
uart 2 mode select */
|
| 400 |
|
|
#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
|
| 401 |
|
|
uart 3 mode select */
|
| 402 |
|
|
|
| 403 |
|
|
/* Bitmasks for IOC4_ATA_TIMING */
|
| 404 |
|
|
#define IOC4_ATA_TIMING_ADR_SETUP 0x00000003 /* Clocks of addr set-up */
|
| 405 |
|
|
#define IOC4_ATA_TIMING_PULSE_WIDTH 0x000001f8 /* Clocks of read or write
|
| 406 |
|
|
pulse width */
|
| 407 |
|
|
#define IOC4_ATA_TIMING_RECOVERY 0x0000fe00 /* Clocks before next read
|
| 408 |
|
|
or write */
|
| 409 |
|
|
#define IOC4_ATA_TIMING_USE_IORDY 0x00010000 /* PIO uses IORDY */
|
| 410 |
|
|
|
| 411 |
|
|
/* Bitmasks for address list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
|
| 412 |
|
|
#define IOC4_ATA_ALE_DMA_ADDRESS 0xfffffffffffffffe
|
| 413 |
|
|
|
| 414 |
|
|
/* Bitmasks for byte count list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
|
| 415 |
|
|
#define IOC4_ATA_BCLE_BYTE_COUNT 0x000000000000fffe
|
| 416 |
|
|
#define IOC4_ATA_BCLE_LIST_END 0x0000000080000000
|
| 417 |
|
|
|
| 418 |
|
|
/* Bitmasks for IOC4_ATA_BC_<DEV|MEM> */
|
| 419 |
|
|
#define IOC4_ATA_BC_BYTE_CNT 0x0001fffe /* Byte count */
|
| 420 |
|
|
|
| 421 |
|
|
/* Bitmasks for IOC4_ATA_DMA_CTRL */
|
| 422 |
|
|
#define IOC4_ATA_DMA_CTRL_STRAT 0x00000001 /* 1 -> start DMA engine */
|
| 423 |
|
|
#define IOC4_ATA_DMA_CTRL_STOP 0x00000002 /* 1 -> stop DMA engine */
|
| 424 |
|
|
#define IOC4_ATA_DMA_CTRL_DIR 0x00000004 /* 1 -> ATA bus data copied
|
| 425 |
|
|
to memory */
|
| 426 |
|
|
#define IOC4_ATA_DMA_CTRL_ACTIVE 0x00000008 /* DMA channel is active */
|
| 427 |
|
|
#define IOC4_ATA_DMA_CTRL_MEM_ERROR 0x00000010 /* DMA engine encountered
|
| 428 |
|
|
a PCI error */
|
| 429 |
|
|
/* Bitmasks for IOC4_KM_CSR */
|
| 430 |
|
|
#define IOC4_KM_CSR_K_WRT_PEND 0x00000001 /* Kbd port xmitting or resetting */
|
| 431 |
|
|
#define IOC4_KM_CSR_M_WRT_PEND 0x00000002 /* Mouse port xmitting or resetting */
|
| 432 |
|
|
#define IOC4_KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */
|
| 433 |
|
|
#define IOC4_KM_CSR_M_LCB 0x00000008 /* Same for mouse */
|
| 434 |
|
|
#define IOC4_KM_CSR_K_DATA 0x00000010 /* State of kbd data line */
|
| 435 |
|
|
#define IOC4_KM_CSR_K_CLK 0x00000020 /* State of kbd clock line */
|
| 436 |
|
|
#define IOC4_KM_CSR_K_PULL_DATA 0x00000040 /* Pull kbd data line low */
|
| 437 |
|
|
#define IOC4_KM_CSR_K_PULL_CLK 0x00000080 /* Pull kbd clock line low */
|
| 438 |
|
|
#define IOC4_KM_CSR_M_DATA 0x00000100 /* State of mouse data line */
|
| 439 |
|
|
#define IOC4_KM_CSR_M_CLK 0x00000200 /* State of mouse clock line */
|
| 440 |
|
|
#define IOC4_KM_CSR_M_PULL_DATA 0x00000400 /* Pull mouse data line low */
|
| 441 |
|
|
#define IOC4_KM_CSR_M_PULL_CLK 0x00000800 /* Pull mouse clock line low */
|
| 442 |
|
|
#define IOC4_KM_CSR_EMM_MODE 0x00001000 /* Emulation mode */
|
| 443 |
|
|
#define IOC4_KM_CSR_SIM_MODE 0x00002000 /* Clock X8 */
|
| 444 |
|
|
#define IOC4_KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */
|
| 445 |
|
|
#define IOC4_KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */
|
| 446 |
|
|
#define IOC4_KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */
|
| 447 |
|
|
#define IOC4_KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */
|
| 448 |
|
|
#define IOC4_KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN =
|
| 449 |
|
|
cause SIO_IR to assert */
|
| 450 |
|
|
#define IOC4_KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN =
|
| 451 |
|
|
cause SIO_IR to assert */
|
| 452 |
|
|
#define IOC4_KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
|
| 453 |
|
|
#define IOC4_KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
|
| 454 |
|
|
#define IOC4_KM_CSR_K_CLAMP_THREE \
|
| 455 |
|
|
0x00400000 /* Pull K_CLK low after rec. three chars */
|
| 456 |
|
|
#define IOC4_KM_CSR_M_CLAMP_THREE \
|
| 457 |
|
|
0x00800000 /* Pull M_CLK low after rec. three char */
|
| 458 |
|
|
|
| 459 |
|
|
/* Bitmasks for IOC4_K_RD and IOC4_M_RD */
|
| 460 |
|
|
#define IOC4_KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
|
| 461 |
|
|
#define IOC4_KM_RD_DATA_2_SHIFT 0
|
| 462 |
|
|
#define IOC4_KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */
|
| 463 |
|
|
#define IOC4_KM_RD_DATA_1_SHIFT 8
|
| 464 |
|
|
#define IOC4_KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */
|
| 465 |
|
|
#define IOC4_KM_RD_DATA_0_SHIFT 16
|
| 466 |
|
|
#define IOC4_KM_RD_FRAME_ERR_2 0x01000000 /* Framing or parity error in byte 2 */
|
| 467 |
|
|
#define IOC4_KM_RD_FRAME_ERR_1 0x02000000 /* Same for byte 1 */
|
| 468 |
|
|
#define IOC4_KM_RD_FRAME_ERR_0 0x04000000 /* Same for byte 0 */
|
| 469 |
|
|
|
| 470 |
|
|
#define IOC4_KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */
|
| 471 |
|
|
#define IOC4_KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */
|
| 472 |
|
|
#define IOC4_KM_RD_VALID_2 0x20000000 /* DATA_2 valid */
|
| 473 |
|
|
#define IOC4_KM_RD_VALID_1 0x40000000 /* DATA_1 valid */
|
| 474 |
|
|
#define IOC4_KM_RD_VALID_0 0x80000000 /* DATA_0 valid */
|
| 475 |
|
|
#define IOC4_KM_RD_VALID_ALL (IOC4_KM_RD_VALID_0 | IOC4_KM_RD_VALID_1 | \
|
| 476 |
|
|
IOC4_KM_RD_VALID_2)
|
| 477 |
|
|
|
| 478 |
|
|
/* Bitmasks for IOC4_K_WD & IOC4_M_WD */
|
| 479 |
|
|
#define IOC4_KM_WD_WRT_DATA 0x000000ff /* Write to keyboard/mouse port */
|
| 480 |
|
|
#define IOC4_KM_WD_WRT_DATA_SHIFT 0
|
| 481 |
|
|
|
| 482 |
|
|
/* Bitmasks for serial RX status byte */
|
| 483 |
|
|
#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
|
| 484 |
|
|
#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
|
| 485 |
|
|
#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
|
| 486 |
|
|
#define IOC4_RXSB_BREAK 0x08 /* Break character */
|
| 487 |
|
|
#define IOC4_RXSB_CTS 0x10 /* State of CTS */
|
| 488 |
|
|
#define IOC4_RXSB_DCD 0x20 /* State of DCD */
|
| 489 |
|
|
#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
|
| 490 |
|
|
#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR & BREAK valid */
|
| 491 |
|
|
|
| 492 |
|
|
/* Bitmasks for serial TX control byte */
|
| 493 |
|
|
#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
|
| 494 |
|
|
#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
|
| 495 |
|
|
#define IOC4_TXCB_VALID 0x40 /* Byte is valid */
|
| 496 |
|
|
#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control register */
|
| 497 |
|
|
#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
|
| 498 |
|
|
|
| 499 |
|
|
/* Bitmasks for IOC4_SBBR_L */
|
| 500 |
|
|
#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
|
| 501 |
|
|
#define IOC4_SBBR_L_BASE 0xfffff000 /* Lower serial ring base addr */
|
| 502 |
|
|
|
| 503 |
|
|
/* Bitmasks for IOC4_SSCR_<3:0> */
|
| 504 |
|
|
#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
|
| 505 |
|
|
#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
|
| 506 |
|
|
#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
|
| 507 |
|
|
#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
|
| 508 |
|
|
#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
|
| 509 |
|
|
#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
|
| 510 |
|
|
#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
|
| 511 |
|
|
#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
|
| 512 |
|
|
#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
|
| 513 |
|
|
#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
|
| 514 |
|
|
#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
|
| 515 |
|
|
|
| 516 |
|
|
/* All producer/comsumer pointers are the same bitfield */
|
| 517 |
|
|
#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
|
| 518 |
|
|
#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
|
| 519 |
|
|
#define IOC4_PROD_CONS_PTR_OFF 3
|
| 520 |
|
|
|
| 521 |
|
|
/* Bitmasks for IOC4_STPIR_<3:0> */
|
| 522 |
|
|
/* Reserved for future register definitions */
|
| 523 |
|
|
|
| 524 |
|
|
/* Bitmasks for IOC4_STCIR_<3:0> */
|
| 525 |
|
|
#define IOC4_STCIR_BYTE_CNT 0x0f000000 /* Bytes in unpacker */
|
| 526 |
|
|
#define IOC4_STCIR_BYTE_CNT_SHIFT 24
|
| 527 |
|
|
|
| 528 |
|
|
/* Bitmasks for IOC4_SRPIR_<3:0> */
|
| 529 |
|
|
#define IOC4_SRPIR_BYTE_CNT 0x0f000000 /* Bytes in packer */
|
| 530 |
|
|
#define IOC4_SRPIR_BYTE_CNT_SHIFT 24
|
| 531 |
|
|
|
| 532 |
|
|
/* Bitmasks for IOC4_SRCIR_<3:0> */
|
| 533 |
|
|
#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
|
| 534 |
|
|
|
| 535 |
|
|
/* Bitmasks for IOC4_SHADOW_<3:0> */
|
| 536 |
|
|
#define IOC4_SHADOW_DR 0x00000001 /* Data ready */
|
| 537 |
|
|
#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
|
| 538 |
|
|
#define IOC4_SHADOW_PE 0x00000004 /* Parity error */
|
| 539 |
|
|
#define IOC4_SHADOW_FE 0x00000008 /* Framing error */
|
| 540 |
|
|
#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
|
| 541 |
|
|
#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
|
| 542 |
|
|
#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
|
| 543 |
|
|
#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
|
| 544 |
|
|
#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
|
| 545 |
|
|
#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
|
| 546 |
|
|
#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
|
| 547 |
|
|
#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
|
| 548 |
|
|
#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
|
| 549 |
|
|
#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
|
| 550 |
|
|
#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
|
| 551 |
|
|
#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
|
| 552 |
|
|
#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
|
| 553 |
|
|
|
| 554 |
|
|
/* Bitmasks for IOC4_SRTR_<3:0> */
|
| 555 |
|
|
#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
|
| 556 |
|
|
#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
|
| 557 |
|
|
#define IOC4_SRTR_CNT_VAL_SHIFT 16
|
| 558 |
|
|
#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
|
| 559 |
|
|
|
| 560 |
|
|
/* Serial port register map used for DMA and PIO serial I/O */
|
| 561 |
|
|
typedef volatile struct ioc4_serialregs {
|
| 562 |
|
|
ioc4reg_t sscr;
|
| 563 |
|
|
ioc4reg_t stpir;
|
| 564 |
|
|
ioc4reg_t stcir;
|
| 565 |
|
|
ioc4reg_t srpir;
|
| 566 |
|
|
ioc4reg_t srcir;
|
| 567 |
|
|
ioc4reg_t srtr;
|
| 568 |
|
|
ioc4reg_t shadow;
|
| 569 |
|
|
} ioc4_sregs_t;
|
| 570 |
|
|
|
| 571 |
|
|
/* IOC4 UART register map */
|
| 572 |
|
|
typedef volatile struct ioc4_uartregs {
|
| 573 |
|
|
char i4u_lcr;
|
| 574 |
|
|
union {
|
| 575 |
|
|
char iir; /* read only */
|
| 576 |
|
|
char fcr; /* write only */
|
| 577 |
|
|
} u3;
|
| 578 |
|
|
union {
|
| 579 |
|
|
char ier; /* DLAB == 0 */
|
| 580 |
|
|
char dlm; /* DLAB == 1 */
|
| 581 |
|
|
} u2;
|
| 582 |
|
|
union {
|
| 583 |
|
|
char rbr; /* read only, DLAB == 0 */
|
| 584 |
|
|
char thr; /* write only, DLAB == 0 */
|
| 585 |
|
|
char dll; /* DLAB == 1 */
|
| 586 |
|
|
} u1;
|
| 587 |
|
|
char i4u_scr;
|
| 588 |
|
|
char i4u_msr;
|
| 589 |
|
|
char i4u_lsr;
|
| 590 |
|
|
char i4u_mcr;
|
| 591 |
|
|
} ioc4_uart_t;
|
| 592 |
|
|
|
| 593 |
|
|
|
| 594 |
|
|
#define i4u_rbr u1.rbr
|
| 595 |
|
|
#define i4u_thr u1.thr
|
| 596 |
|
|
#define i4u_dll u1.dll
|
| 597 |
|
|
#define i4u_ier u2.ier
|
| 598 |
|
|
#define i4u_dlm u2.dlm
|
| 599 |
|
|
#define i4u_iir u3.iir
|
| 600 |
|
|
#define i4u_fcr u3.fcr
|
| 601 |
|
|
|
| 602 |
|
|
/* PCI config space register map */
|
| 603 |
|
|
typedef volatile struct ioc4_configregs {
|
| 604 |
|
|
ioc4reg_t pci_id;
|
| 605 |
|
|
ioc4reg_t pci_scr;
|
| 606 |
|
|
ioc4reg_t pci_rev;
|
| 607 |
|
|
ioc4reg_t pci_lat;
|
| 608 |
|
|
ioc4reg_t pci_bar0;
|
| 609 |
|
|
ioc4reg_t pci_bar1;
|
| 610 |
|
|
ioc4reg_t pci_bar2_not_implemented;
|
| 611 |
|
|
ioc4reg_t pci_cis_ptr_not_implemented;
|
| 612 |
|
|
ioc4reg_t pci_sidv;
|
| 613 |
|
|
ioc4reg_t pci_rom_bar_not_implemented;
|
| 614 |
|
|
ioc4reg_t pci_cap;
|
| 615 |
|
|
ioc4reg_t pci_rsv;
|
| 616 |
|
|
ioc4reg_t pci_latgntint;
|
| 617 |
|
|
|
| 618 |
|
|
char pci_fill1[0x58 - 0x3c - 4];
|
| 619 |
|
|
|
| 620 |
|
|
ioc4reg_t pci_pcix;
|
| 621 |
|
|
ioc4reg_t pci_pcixstatus;
|
| 622 |
|
|
} ioc4_cfg_t;
|
| 623 |
|
|
|
| 624 |
|
|
/* PCI memory space register map addressed using pci_bar0 */
|
| 625 |
|
|
typedef volatile struct ioc4_memregs {
|
| 626 |
|
|
|
| 627 |
|
|
/* Miscellaneous IOC4 registers */
|
| 628 |
|
|
ioc4reg_t pci_err_addr_l;
|
| 629 |
|
|
ioc4reg_t pci_err_addr_h;
|
| 630 |
|
|
ioc4reg_t sio_ir;
|
| 631 |
|
|
ioc4reg_t other_ir;
|
| 632 |
|
|
|
| 633 |
|
|
/* These registers are read-only for general kernel code. To
|
| 634 |
|
|
* modify them use the functions in ioc4.c.
|
| 635 |
|
|
*/
|
| 636 |
|
|
ioc4reg_t sio_ies_ro;
|
| 637 |
|
|
ioc4reg_t other_ies_ro;
|
| 638 |
|
|
ioc4reg_t sio_iec_ro;
|
| 639 |
|
|
ioc4reg_t other_iec_ro;
|
| 640 |
|
|
ioc4reg_t sio_cr;
|
| 641 |
|
|
ioc4reg_t misc_fill1;
|
| 642 |
|
|
ioc4reg_t int_out;
|
| 643 |
|
|
ioc4reg_t misc_fill2;
|
| 644 |
|
|
ioc4reg_t gpcr_s;
|
| 645 |
|
|
ioc4reg_t gpcr_c;
|
| 646 |
|
|
ioc4reg_t gpdr;
|
| 647 |
|
|
ioc4reg_t misc_fill3;
|
| 648 |
|
|
ioc4reg_t gppr_0;
|
| 649 |
|
|
ioc4reg_t gppr_1;
|
| 650 |
|
|
ioc4reg_t gppr_2;
|
| 651 |
|
|
ioc4reg_t gppr_3;
|
| 652 |
|
|
ioc4reg_t gppr_4;
|
| 653 |
|
|
ioc4reg_t gppr_5;
|
| 654 |
|
|
ioc4reg_t gppr_6;
|
| 655 |
|
|
ioc4reg_t gppr_7;
|
| 656 |
|
|
|
| 657 |
|
|
char misc_fill4[0x100 - 0x5C - 4];
|
| 658 |
|
|
|
| 659 |
|
|
/* ATA/ATAP registers */
|
| 660 |
|
|
ioc4reg_t ata_0;
|
| 661 |
|
|
ioc4reg_t ata_1;
|
| 662 |
|
|
ioc4reg_t ata_2;
|
| 663 |
|
|
ioc4reg_t ata_3;
|
| 664 |
|
|
ioc4reg_t ata_4;
|
| 665 |
|
|
ioc4reg_t ata_5;
|
| 666 |
|
|
ioc4reg_t ata_6;
|
| 667 |
|
|
ioc4reg_t ata_7;
|
| 668 |
|
|
ioc4reg_t ata_aux;
|
| 669 |
|
|
|
| 670 |
|
|
char ata_fill1[0x140 - 0x120 - 4];
|
| 671 |
|
|
|
| 672 |
|
|
ioc4reg_t ata_timing;
|
| 673 |
|
|
ioc4reg_t ata_dma_ptr_l;
|
| 674 |
|
|
ioc4reg_t ata_dma_ptr_h;
|
| 675 |
|
|
ioc4reg_t ata_dma_addr_l;
|
| 676 |
|
|
ioc4reg_t ata_dma_addr_h;
|
| 677 |
|
|
ioc4reg_t ata_bc_dev;
|
| 678 |
|
|
ioc4reg_t ata_bc_mem;
|
| 679 |
|
|
ioc4reg_t ata_dma_ctrl;
|
| 680 |
|
|
|
| 681 |
|
|
char ata_fill2[0x200 - 0x15C - 4];
|
| 682 |
|
|
|
| 683 |
|
|
/* Keyboard and mouse registers */
|
| 684 |
|
|
ioc4reg_t km_csr;
|
| 685 |
|
|
ioc4reg_t k_rd;
|
| 686 |
|
|
ioc4reg_t m_rd;
|
| 687 |
|
|
ioc4reg_t k_wd;
|
| 688 |
|
|
ioc4reg_t m_wd;
|
| 689 |
|
|
|
| 690 |
|
|
char km_fill1[0x300 - 0x210 - 4];
|
| 691 |
|
|
|
| 692 |
|
|
/* Serial port registers used for DMA serial I/O */
|
| 693 |
|
|
ioc4reg_t sbbr01_l;
|
| 694 |
|
|
ioc4reg_t sbbr01_h;
|
| 695 |
|
|
ioc4reg_t sbbr23_l;
|
| 696 |
|
|
ioc4reg_t sbbr23_h;
|
| 697 |
|
|
|
| 698 |
|
|
ioc4_sregs_t port_0;
|
| 699 |
|
|
ioc4_sregs_t port_1;
|
| 700 |
|
|
ioc4_sregs_t port_2;
|
| 701 |
|
|
ioc4_sregs_t port_3;
|
| 702 |
|
|
|
| 703 |
|
|
ioc4_uart_t uart_0;
|
| 704 |
|
|
ioc4_uart_t uart_1;
|
| 705 |
|
|
ioc4_uart_t uart_2;
|
| 706 |
|
|
ioc4_uart_t uart_3;
|
| 707 |
|
|
} ioc4_mem_t;
|
| 708 |
|
|
|
| 709 |
|
|
|
| 710 |
|
|
/*
|
| 711 |
|
|
* Bytebus device space
|
| 712 |
|
|
*/
|
| 713 |
|
|
#define IOC4_BYTEBUS_DEV0 0x80000L /* Addressed using pci_bar0 */
|
| 714 |
|
|
#define IOC4_BYTEBUS_DEV1 0xA0000L /* Addressed using pci_bar0 */
|
| 715 |
|
|
#define IOC4_BYTEBUS_DEV2 0xC0000L /* Addressed using pci_bar0 */
|
| 716 |
|
|
#define IOC4_BYTEBUS_DEV3 0xE0000L /* Addressed using pci_bar0 */
|
| 717 |
|
|
|
| 718 |
|
|
/* UART clock speed */
|
| 719 |
|
|
#define IOC4_SER_XIN_CLK 66000000
|
| 720 |
|
|
|
| 721 |
|
|
typedef enum ioc4_subdevs_e {
|
| 722 |
|
|
ioc4_subdev_generic,
|
| 723 |
|
|
ioc4_subdev_kbms,
|
| 724 |
|
|
ioc4_subdev_tty0,
|
| 725 |
|
|
ioc4_subdev_tty1,
|
| 726 |
|
|
ioc4_subdev_tty2,
|
| 727 |
|
|
ioc4_subdev_tty3,
|
| 728 |
|
|
ioc4_subdev_rt,
|
| 729 |
|
|
ioc4_nsubdevs
|
| 730 |
|
|
} ioc4_subdev_t;
|
| 731 |
|
|
|
| 732 |
|
|
/* Subdevice disable bits,
|
| 733 |
|
|
* from the standard INFO_LBL_SUBDEVS
|
| 734 |
|
|
*/
|
| 735 |
|
|
#define IOC4_SDB_TTY0 (1 << ioc4_subdev_tty0)
|
| 736 |
|
|
#define IOC4_SDB_TTY1 (1 << ioc4_subdev_tty1)
|
| 737 |
|
|
#define IOC4_SDB_TTY2 (1 << ioc4_subdev_tty2)
|
| 738 |
|
|
#define IOC4_SDB_TTY3 (1 << ioc4_subdev_tty3)
|
| 739 |
|
|
#define IOC4_SDB_KBMS (1 << ioc4_subdev_kbms)
|
| 740 |
|
|
#define IOC4_SDB_RT (1 << ioc4_subdev_rt)
|
| 741 |
|
|
#define IOC4_SDB_GENERIC (1 << ioc4_subdev_generic)
|
| 742 |
|
|
|
| 743 |
|
|
#define IOC4_ALL_SUBDEVS ((1 << ioc4_nsubdevs) - 1)
|
| 744 |
|
|
|
| 745 |
|
|
#define IOC4_SDB_SERIAL (IOC4_SDB_TTY0 | IOC4_SDB_TTY1 | IOC4_SDB_TTY2 | IOC4_SDB_TTY3)
|
| 746 |
|
|
|
| 747 |
|
|
#define IOC4_STD_SUBDEVS IOC4_ALL_SUBDEVS
|
| 748 |
|
|
|
| 749 |
|
|
#define IOC4_INTA_SUBDEVS (IOC4_SDB_SERIAL | IOC4_SDB_KBMS | IOC4_SDB_RT | IOC4_SDB_GENERIC)
|
| 750 |
|
|
|
| 751 |
|
|
extern int ioc4_subdev_enabled(vertex_hdl_t, ioc4_subdev_t);
|
| 752 |
|
|
extern void ioc4_subdev_enables(vertex_hdl_t, uint64_t);
|
| 753 |
|
|
extern void ioc4_subdev_enable(vertex_hdl_t, ioc4_subdev_t);
|
| 754 |
|
|
extern void ioc4_subdev_disable(vertex_hdl_t, ioc4_subdev_t);
|
| 755 |
|
|
|
| 756 |
|
|
/* Macros to read and write the SIO_IEC and SIO_IES registers (see the
|
| 757 |
|
|
* comments in ioc4.c for details on why this is necessary
|
| 758 |
|
|
*/
|
| 759 |
|
|
#define IOC4_W_IES 0
|
| 760 |
|
|
#define IOC4_W_IEC 1
|
| 761 |
|
|
extern void ioc4_write_ireg(void *, ioc4reg_t, int, ioc4_intr_type_t);
|
| 762 |
|
|
|
| 763 |
|
|
#define IOC4_WRITE_IES(ioc4, val, type) ioc4_write_ireg(ioc4, val, IOC4_W_IES, type)
|
| 764 |
|
|
#define IOC4_WRITE_IEC(ioc4, val, type) ioc4_write_ireg(ioc4, val, IOC4_W_IEC, type)
|
| 765 |
|
|
|
| 766 |
|
|
typedef void
|
| 767 |
|
|
ioc4_intr_func_f (intr_arg_t, ioc4reg_t);
|
| 768 |
|
|
|
| 769 |
|
|
typedef void
|
| 770 |
|
|
ioc4_intr_connect_f (struct pci_dev *conn_vhdl,
|
| 771 |
|
|
ioc4_intr_type_t,
|
| 772 |
|
|
ioc4reg_t,
|
| 773 |
|
|
ioc4_intr_func_f *,
|
| 774 |
|
|
intr_arg_t info,
|
| 775 |
|
|
vertex_hdl_t owner_vhdl,
|
| 776 |
|
|
vertex_hdl_t intr_dev_vhdl,
|
| 777 |
|
|
int (*)(intr_arg_t));
|
| 778 |
|
|
|
| 779 |
|
|
typedef void
|
| 780 |
|
|
ioc4_intr_disconnect_f (vertex_hdl_t conn_vhdl,
|
| 781 |
|
|
ioc4_intr_type_t,
|
| 782 |
|
|
ioc4reg_t,
|
| 783 |
|
|
ioc4_intr_func_f *,
|
| 784 |
|
|
intr_arg_t info,
|
| 785 |
|
|
vertex_hdl_t owner_vhdl);
|
| 786 |
|
|
|
| 787 |
|
|
void ioc4_intr_connect(vertex_hdl_t, ioc4_intr_type_t, ioc4reg_t,
|
| 788 |
|
|
ioc4_intr_func_f *, intr_arg_t, vertex_hdl_t,
|
| 789 |
|
|
vertex_hdl_t);
|
| 790 |
|
|
|
| 791 |
|
|
extern int ioc4_is_console(vertex_hdl_t conn_vhdl);
|
| 792 |
|
|
|
| 793 |
|
|
extern void ioc4_mlreset(ioc4_cfg_t *, ioc4_mem_t *);
|
| 794 |
|
|
|
| 795 |
|
|
|
| 796 |
|
|
extern ioc4_mem_t *ioc4_mem_ptr(void *ioc4_fastinfo);
|
| 797 |
|
|
|
| 798 |
|
|
typedef ioc4_intr_func_f *ioc4_intr_func_t;
|
| 799 |
|
|
|
| 800 |
|
|
#endif /* _ASM_IA64_SN_IOC4_H */
|
