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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-ia64/] [sn/] [ksys/] [l1.h] - Blame information for rev 1774

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1 1276 phoenix
/* $Id: l1.h,v 1.1.1.1 2004-04-15 02:58:08 phoenix Exp $
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 *
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc.  All Rights Reserved.
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 */
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#ifndef _ASM_SN_KSYS_L1_H
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#define _ASM_SN_KSYS_L1_H
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#include <linux/config.h>
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#include <asm/sn/vector.h>
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#include <asm/sn/addrs.h>
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#include <asm/atomic.h>
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#include <asm/sn/sv.h>
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/* L1 Target Addresses */
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/*
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 * L1 commands and responses use source/target addresses that are
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 * 32 bits long.  These are broken up into multiple bitfields that
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 * specify the type of the target controller (could actually be L2
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 * L3, not just L1), the rack and bay of the target, and the task
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 * id (L1 functionality is divided into several independent "tasks"
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 * that can each receive command requests and transmit responses)
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 */
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#define L1_ADDR_TYPE_L1         0x00    /* L1 system controller */
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#define L1_ADDR_TYPE_L2         0x01    /* L2 system controller */
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#define L1_ADDR_TYPE_L3         0x02    /* L3 system controller */
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#define L1_ADDR_TYPE_CBRICK     0x03    /* attached C brick     */
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#define L1_ADDR_TYPE_IOBRICK    0x04    /* attached I/O brick   */
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#define L1_ADDR_TASK_SHFT       0
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#define L1_ADDR_TASK_MASK       0x0000001F
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#define L1_ADDR_TASK_INVALID    0x00    /* invalid task         */
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#define L1_ADDR_TASK_IROUTER    0x01    /* iRouter              */
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#define L1_ADDR_TASK_SYS_MGMT   0x02    /* system management port */
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#define L1_ADDR_TASK_CMD        0x03    /* command interpreter  */
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#define L1_ADDR_TASK_ENV        0x04    /* environmental monitor */
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#define L1_ADDR_TASK_BEDROCK    0x05    /* bedrock              */
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#define L1_ADDR_TASK_GENERAL    0x06    /* general requests     */
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#define L1_ADDR_LOCAL                           \
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    (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) |    \
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    (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \
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    (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT)
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#define L1_ADDR_LOCALIO                                 \
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    (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) |       \
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    (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) |         \
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    (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT)
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#define L1_ADDR_LOCAL_SHFT      L1_ADDR_BAY_SHFT
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/* response argument types */
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#define L1_ARG_INT              0x00    /* 4-byte integer (big-endian)  */
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#define L1_ARG_ASCII            0x01    /* null-terminated ASCII string */
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#define L1_ARG_UNKNOWN          0x80    /* unknown data type.  The low
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                                         * 7 bits will contain the data
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                                         * length.                      */
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/* response codes */
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#define L1_RESP_OK          0   /* no problems encountered      */
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#define L1_RESP_IROUTER (-  1)  /* iRouter error                */
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#define L1_RESP_ARGC    (-100)  /* arg count mismatch           */
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#define L1_RESP_REQC    (-101)  /* bad request code             */
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#define L1_RESP_NAVAIL  (-104)  /* requested data not available */
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#define L1_RESP_ARGVAL  (-105)  /* arg value out of range       */
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#define L1_RESP_INVAL   (-107)  /* requested data invalid       */
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/* L1 general requests */
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/* request codes */
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#define L1_REQ_RDBG             0x0001  /* read debug switches  */
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#define L1_REQ_RRACK            0x0002  /* read brick rack & bay */
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#define L1_REQ_RRBT             0x0003  /* read brick rack, bay & type */
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#define L1_REQ_SER_NUM          0x0004  /* read brick serial number */
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#define L1_REQ_FW_REV           0x0005  /* read L1 firmware revision */
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#define L1_REQ_EEPROM           0x0006  /* read EEPROM info */
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#define L1_REQ_EEPROM_FMT       0x0007  /* get EEPROM data format & size */
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#define L1_REQ_SYS_SERIAL       0x0008  /* read system serial number */
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#define L1_REQ_PARTITION_GET    0x0009  /* read partition id */
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#define L1_REQ_PORTSPEED        0x000a  /* get ioport speed */
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#define L1_REQ_CONS_SUBCH       0x1002  /* select this node's console 
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                                           subchannel */
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#define L1_REQ_CONS_NODE        0x1003  /* volunteer to be the master 
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                                           (console-hosting) node */
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#define L1_REQ_DISP1            0x1004  /* write line 1 of L1 display */
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#define L1_REQ_DISP2            0x1005  /* write line 2 of L1 display */
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#define L1_REQ_PARTITION_SET    0x1006  /* set partition id */
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#define L1_REQ_EVENT_SUBCH      0x1007  /* set the subchannel for system
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                                           controller event transmission */
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#define L1_REQ_RESET            0x2000  /* request a full system reset */
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#define L1_REQ_PCI_UP           0x2001  /* power up pci slot or bus */
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#define L1_REQ_PCI_DOWN         0x2002  /* power down pci slot or bus */
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#define L1_REQ_PCI_RESET        0x2003  /* reset pci bus or slot */
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/* L1 command interpreter requests */
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/* request codes */
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#define L1_REQ_EXEC_CMD         0x0000  /* interpret and execute an ASCII
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                                           command string */
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/* brick type response codes */
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#define L1_BRICKTYPE_PX         0x23            /* # */
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#define L1_BRICKTYPE_PE         0x25            /* % */
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#define L1_BRICKTYPE_N_p0       0x26            /* & */
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#define L1_BRICKTYPE_IP45       0x34            /* 4 */
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#define L1_BRICKTYPE_IP41       0x35            /* 5 */
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#define L1_BRICKTYPE_TWISTER    0x36            /* 6 */ /* IP53 & ROUTER */
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#define L1_BRICKTYPE_IX         0x3d            /* = */
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#define L1_BRICKTYPE_IP34       0x61            /* a */
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#define L1_BRICKTYPE_C          0x63            /* c */
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#define L1_BRICKTYPE_I          0x69            /* i */
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#define L1_BRICKTYPE_N          0x6e            /* n */
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#define L1_BRICKTYPE_OPUS       0x6f            /* o */
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#define L1_BRICKTYPE_P          0x70            /* p */
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#define L1_BRICKTYPE_R          0x72            /* r */
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#define L1_BRICKTYPE_CHI_CG     0x76            /* v */
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#define L1_BRICKTYPE_X          0x78            /* x */
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#define L1_BRICKTYPE_X2         0x79            /* y */
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/* EEPROM codes (for the "read EEPROM" request) */
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/* c brick */
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#define L1_EEP_NODE             0x00    /* node board */
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#define L1_EEP_PIMM0            0x01
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#define L1_EEP_PIMM(x)          (L1_EEP_PIMM0+(x))
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#define L1_EEP_DIMM0            0x03
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#define L1_EEP_DIMM(x)          (L1_EEP_DIMM0+(x))
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/* other brick types */
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#define L1_EEP_POWER            0x00    /* power board */
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#define L1_EEP_LOGIC            0x01    /* logic board */
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/* info area types */
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#define L1_EEP_CHASSIS          1       /* chassis info area */
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#define L1_EEP_BOARD            2       /* board info area */
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#define L1_EEP_IUSE             3       /* internal use area */
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#define L1_EEP_SPD              4       /* serial presence detect record */
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typedef uint32_t l1addr_t;
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#define L1_BUILD_ADDR(addr,at,r,s,t)                                    \
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    (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) |      \
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                             ((l1addr_t)(r)  << L1_ADDR_RACK_SHFT) |    \
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                             ((l1addr_t)(s)  << L1_ADDR_BAY_SHFT) |     \
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                             ((l1addr_t)(t)  << L1_ADDR_TASK_SHFT))
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#define L1_ADDRESS_TO_TASK(addr,trb,tsk)                                \
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    (*(l1addr_t *)(addr) = (l1addr_t)(trb) |                            \
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                             ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT))
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#define L1_DISPLAY_LINE_LENGTH  12      /* L1 display characters/line */
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#ifdef L1_DISP_2LINES
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#define L1_DISPLAY_LINES        2       /* number of L1 display lines */
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#else
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#define L1_DISPLAY_LINES        1       /* number of L1 display lines available
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                                         * to system software */
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#endif
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#define bzero(d, n)     memset((d), 0, (n))
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int     elsc_display_line(nasid_t nasid, char *line, int lnum);
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int     iobrick_rack_bay_type_get( nasid_t nasid, uint *rack,
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                                   uint *bay, uint *brick_type );
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int     iobrick_module_get( nasid_t nasid );
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#endif /* _ASM_SN_KSYS_L1_H */

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