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phoenix |
/* $Id: pcibr.h,v 1.1.1.1 2004-04-15 02:42:53 phoenix Exp $
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_SN_PCI_PCIBR_H
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#define _ASM_SN_PCI_PCIBR_H
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#if defined(__KERNEL__)
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#include <linux/config.h>
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#include <asm/sn/dmamap.h>
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#include <asm/sn/driver.h>
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#include <asm/sn/pio.h>
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#include <asm/sn/pci/pciio.h>
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#include <asm/sn/pci/bridge.h>
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/* =====================================================================
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* symbolic constants used by pcibr's xtalk bus provider
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*/
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#define PCIBR_PIOMAP_BUSY 0x80000000
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#define PCIBR_DMAMAP_BUSY 0x80000000
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#define PCIBR_DMAMAP_SSRAM 0x40000000
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#define PCIBR_INTR_BLOCKED 0x40000000
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#define PCIBR_INTR_BUSY 0x80000000
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#ifndef __ASSEMBLY__
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/* =====================================================================
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* opaque types used by pcibr's xtalk bus provider
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*/
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typedef struct pcibr_piomap_s *pcibr_piomap_t;
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typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
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typedef struct pcibr_intr_s *pcibr_intr_t;
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/* =====================================================================
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* primary entry points: Bridge (pcibr) device driver
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*
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* These functions are normal device driver entry points
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* and are called along with the similar entry points from
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* other device drivers. They are included here as documentation
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* of their existence and purpose.
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*
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* pcibr_init() is called to inform us that there is a pcibr driver
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* configured into the kernel; it is responsible for registering
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* as a crosstalk widget and providing a routine to be called
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* when a widget with the proper part number is observed.
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*
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* pcibr_attach() is called for each vertex in the hardware graph
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* corresponding to a crosstalk widget with the manufacturer
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* code and part number registered by pcibr_init().
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*/
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extern int pcibr_attach(vertex_hdl_t);
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/* =====================================================================
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* bus provider function table
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*
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* Normally, this table is only handed off explicitly
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* during provider initialization, and the PCI generic
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* layer will stash a pointer to it in the vertex; however,
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* exporting it explicitly enables a performance hack in
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* the generic PCI provider where if we know at compile
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* time that the only possible PCI provider is a
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* pcibr, we can go directly to this ops table.
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*/
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extern pciio_provider_t pcibr_provider;
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extern pciio_provider_t pci_pic_provider;
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/* =====================================================================
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* secondary entry points: pcibr PCI bus provider
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*
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* These functions are normally exported explicitly by
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* a direct call from the pcibr initialization routine
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* into the generic crosstalk provider; they are included
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* here to enable a more aggressive performance hack in
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* the generic crosstalk layer, where if we know that the
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* only possible crosstalk provider is pcibr, and we can
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* guarantee that all entry points are properly named, and
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* we can deal with the implicit casting properly, then
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* we can turn many of the generic provider routines into
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* plain brances, or even eliminate them (given sufficient
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* smarts on the part of the compilation system).
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*/
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extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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iopaddr_t pci_addr,
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size_t byte_count,
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size_t byte_count_max,
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unsigned flags);
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extern void pcibr_piomap_free(pcibr_piomap_t piomap);
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extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap,
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iopaddr_t xtalk_addr,
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size_t byte_count);
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extern void pcibr_piomap_done(pcibr_piomap_t piomap);
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extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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iopaddr_t pci_addr,
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size_t byte_count,
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unsigned flags);
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extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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size_t byte_count,
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size_t alignment);
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extern void pcibr_piospace_free(vertex_hdl_t dev,
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pciio_space_t space,
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iopaddr_t pciaddr,
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size_t byte_count);
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extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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size_t byte_count_max,
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unsigned flags);
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extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap);
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extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
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paddr_t paddr,
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size_t byte_count);
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extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap,
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alenlist_t palenlist,
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unsigned flags);
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extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap);
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/*
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* pcibr_get_dmatrans_node() will return the compact node id to which
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* all 32-bit Direct Mapping memory accesses will be directed.
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* (This node id can be different for each PCI bus.)
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*/
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extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl);
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extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev,
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device_desc_t dev_desc,
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paddr_t paddr,
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size_t byte_count,
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unsigned flags);
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extern alenlist_t pcibr_dmatrans_list(vertex_hdl_t dev,
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device_desc_t dev_desc,
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alenlist_t palenlist,
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unsigned flags);
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extern void pcibr_dmamap_drain(pcibr_dmamap_t map);
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extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl,
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paddr_t addr,
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size_t bytes);
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extern void pcibr_dmalist_drain(vertex_hdl_t vhdl,
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alenlist_t list);
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typedef unsigned pcibr_intr_ibit_f(pciio_info_t info,
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pciio_intr_line_t lines);
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extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *);
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extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_intr_line_t lines,
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vertex_hdl_t owner_dev);
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extern void pcibr_intr_free(pcibr_intr_t intr);
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extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t);
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extern void pcibr_intr_disconnect(pcibr_intr_t intr);
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extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr);
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extern void pcibr_provider_startup(vertex_hdl_t pcibr);
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extern void pcibr_provider_shutdown(vertex_hdl_t pcibr);
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extern int pcibr_reset(vertex_hdl_t dev);
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extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev,
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pciio_endian_t device_end,
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pciio_endian_t desired_end);
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extern uint64_t pcibr_config_get(vertex_hdl_t conn,
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unsigned reg,
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unsigned size);
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extern void pcibr_config_set(vertex_hdl_t conn,
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unsigned reg,
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unsigned size,
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uint64_t value);
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extern int pcibr_error_devenable(vertex_hdl_t pconn_vhdl,
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int error_code);
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extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl);
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extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
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int *count_vchan0,
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int *count_vchan1,
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int *count_reserved,
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int *count_pool);
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extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd,
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int dev_1_rrbs, int virt1,
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int dev_2_rrbs, int virt2,
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int dev_3_rrbs, int virt3,
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int dev_4_rrbs, int virt4);
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typedef void
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rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl,
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int *vendor_list);
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typedef rrb_alloc_funct_f *rrb_alloc_funct_t;
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void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
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rrb_alloc_funct_f *func);
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extern int pcibr_device_unregister(vertex_hdl_t);
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extern int pcibr_dma_enabled(vertex_hdl_t);
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/*
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* Bridge-specific flags that can be set via pcibr_device_flags_set
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* and cleared via pcibr_device_flags_clear. Other flags are
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* more generic and are maniuplated through PCI-generic interfaces.
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*
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* Note that all PCI implementation-specific flags (Bridge flags, in
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* this case) are in bits 15-31. The lower 15 bits are reserved
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* for PCI-generic flags.
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*
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* Some of these flags have been "promoted" to the
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* generic layer, so they can be used without having
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* to "know" that the PCI bus is hosted by a Bridge.
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*
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* PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when
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* allocating ATE's. ATE count computation will assume that the
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* address to be mapped will start on a page boundary.
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*/
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#define PCIBR_NO_ATE_ROUNDUP 0x00008000
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#define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */
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#define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */
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#define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */
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#define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */
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#define PCIBR_PRECISE 0x00100000
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#define PCIBR_NOPRECISE 0x00200000
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#define PCIBR_BARRIER 0x00400000
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#define PCIBR_NOBARRIER 0x00800000
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#define PCIBR_VCHAN0 0x01000000
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#define PCIBR_VCHAN1 0x02000000
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#define PCIBR_64BIT 0x04000000
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#define PCIBR_NO64BIT 0x08000000
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#define PCIBR_SWAP 0x10000000
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#define PCIBR_NOSWAP 0x20000000
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#define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */
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#define PCIBR_ACTIVE 0x80000000 /* need a "done" */
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/* Flags that have meaning to pcibr_device_flags_{set,clear} */
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#define PCIBR_DEVICE_FLAGS ( \
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PCIBR_WRITE_GATHER |\
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PCIBR_NOWRITE_GATHER |\
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PCIBR_PREFETCH |\
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PCIBR_NOPREFETCH |\
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PCIBR_PRECISE |\
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PCIBR_NOPRECISE |\
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PCIBR_BARRIER |\
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PCIBR_NOBARRIER \
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)
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/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
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#define PCIBR_DMA_FLAGS ( \
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PCIBR_PREFETCH |\
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PCIBR_NOPREFETCH |\
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PCIBR_PRECISE |\
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PCIBR_NOPRECISE |\
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PCIBR_BARRIER |\
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PCIBR_NOBARRIER |\
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PCIBR_VCHAN0 |\
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PCIBR_VCHAN1 \
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)
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typedef int pcibr_device_flags_t;
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/*
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* Set bits in the Bridge Device(x) register for this device.
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* "flags" are defined above. NOTE: this includes turning
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* things *OFF* as well as turning them *ON* ...
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*/
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extern int pcibr_device_flags_set(vertex_hdl_t dev,
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pcibr_device_flags_t flags);
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/*
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* Allocate Read Response Buffers for use by the specified device.
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* count_vchan0 is the total number of buffers desired for the
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* "normal" channel. count_vchan1 is the total number of buffers
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* desired for the "virtual" channel. Returns 0 on success, or
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* <0 on failure, which occurs when we're unable to allocate any
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* buffers to a channel that desires at least one buffer.
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*/
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extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
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int *count_vchan0,
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int *count_vchan1);
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/*
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* Get the starting PCIbus address out of the given DMA map.
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* This function is supposed to be used by a close friend of PCI bridge
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* since it relies on the fact that the starting address of the map is fixed at
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* the allocation time in the current implementation of PCI bridge.
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*/
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| 325 |
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|
extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
|
| 326 |
|
|
|
| 327 |
|
|
extern xwidget_intr_preset_f pcibr_xintr_preset;
|
| 328 |
|
|
|
| 329 |
|
|
extern void pcibr_hints_fix_rrbs(vertex_hdl_t);
|
| 330 |
|
|
extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t);
|
| 331 |
|
|
extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong);
|
| 332 |
|
|
extern void pcibr_hints_handsoff(vertex_hdl_t);
|
| 333 |
|
|
|
| 334 |
|
|
typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int);
|
| 335 |
|
|
extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *);
|
| 336 |
|
|
|
| 337 |
|
|
extern int pcibr_asic_rev(vertex_hdl_t);
|
| 338 |
|
|
|
| 339 |
|
|
#endif /* __ASSEMBLY__ */
|
| 340 |
|
|
#endif /* #if defined(__KERNEL__) */
|
| 341 |
|
|
/*
|
| 342 |
|
|
* Some useful ioctls into the pcibr driver
|
| 343 |
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|
*/
|
| 344 |
|
|
#define PCIBR 'p'
|
| 345 |
|
|
#define _PCIBR(x) ((PCIBR << 8) | (x))
|
| 346 |
|
|
|
| 347 |
|
|
#define PCIBR_SLOT_STARTUP _PCIBR(1)
|
| 348 |
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#define PCIBR_SLOT_SHUTDOWN _PCIBR(2)
|
| 349 |
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|
#define PCIBR_SLOT_QUERY _PCIBR(3)
|
| 350 |
|
|
|
| 351 |
|
|
/*
|
| 352 |
|
|
* Bit defintions for variable slot_status in struct
|
| 353 |
|
|
* pcibr_soft_slot_s. They are here so that both
|
| 354 |
|
|
* the pcibr driver and the pciconfig command can
|
| 355 |
|
|
* reference them.
|
| 356 |
|
|
*/
|
| 357 |
|
|
#define SLOT_STARTUP_CMPLT 0x01
|
| 358 |
|
|
#define SLOT_STARTUP_INCMPLT 0x02
|
| 359 |
|
|
#define SLOT_SHUTDOWN_CMPLT 0x04
|
| 360 |
|
|
#define SLOT_SHUTDOWN_INCMPLT 0x08
|
| 361 |
|
|
#define SLOT_POWER_UP 0x10
|
| 362 |
|
|
#define SLOT_POWER_DOWN 0x20
|
| 363 |
|
|
#define SLOT_IS_SYS_CRITICAL 0x40
|
| 364 |
|
|
|
| 365 |
|
|
#define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \
|
| 366 |
|
|
SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT)
|
| 367 |
|
|
#define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN)
|
| 368 |
|
|
|
| 369 |
|
|
/*
|
| 370 |
|
|
* Bit definitions for variable resp_f_staus.
|
| 371 |
|
|
* They are here so that both the pcibr driver
|
| 372 |
|
|
* and the pciconfig command can reference them.
|
| 373 |
|
|
*/
|
| 374 |
|
|
#define FUNC_IS_VALID 0x01
|
| 375 |
|
|
#define FUNC_IS_SYS_CRITICAL 0x02
|
| 376 |
|
|
|
| 377 |
|
|
/*
|
| 378 |
|
|
* Structures for requesting PCI bridge information and receiving a response
|
| 379 |
|
|
*/
|
| 380 |
|
|
typedef struct pcibr_slot_req_s *pcibr_slot_req_t;
|
| 381 |
|
|
typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t;
|
| 382 |
|
|
typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t;
|
| 383 |
|
|
typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
|
| 384 |
|
|
typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
|
| 385 |
|
|
|
| 386 |
|
|
#define L1_QSIZE 128 /* our L1 message buffer size */
|
| 387 |
|
|
struct pcibr_slot_req_s {
|
| 388 |
|
|
int req_slot;
|
| 389 |
|
|
union {
|
| 390 |
|
|
pcibr_slot_up_resp_t up;
|
| 391 |
|
|
pcibr_slot_down_resp_t down;
|
| 392 |
|
|
pcibr_slot_info_resp_t query;
|
| 393 |
|
|
void *any;
|
| 394 |
|
|
} req_respp;
|
| 395 |
|
|
int req_size;
|
| 396 |
|
|
};
|
| 397 |
|
|
|
| 398 |
|
|
struct pcibr_slot_up_resp_s {
|
| 399 |
|
|
int resp_sub_errno;
|
| 400 |
|
|
char resp_l1_msg[L1_QSIZE + 1];
|
| 401 |
|
|
};
|
| 402 |
|
|
|
| 403 |
|
|
struct pcibr_slot_down_resp_s {
|
| 404 |
|
|
int resp_sub_errno;
|
| 405 |
|
|
char resp_l1_msg[L1_QSIZE + 1];
|
| 406 |
|
|
};
|
| 407 |
|
|
|
| 408 |
|
|
struct pcibr_slot_info_resp_s {
|
| 409 |
|
|
short resp_bs_bridge_type;
|
| 410 |
|
|
short resp_bs_bridge_mode;
|
| 411 |
|
|
int resp_has_host;
|
| 412 |
|
|
char resp_host_slot;
|
| 413 |
|
|
vertex_hdl_t resp_slot_conn;
|
| 414 |
|
|
char resp_slot_conn_name[MAXDEVNAME];
|
| 415 |
|
|
int resp_slot_status;
|
| 416 |
|
|
int resp_l1_bus_num;
|
| 417 |
|
|
int resp_bss_ninfo;
|
| 418 |
|
|
char resp_bss_devio_bssd_space[16];
|
| 419 |
|
|
iopaddr_t resp_bss_devio_bssd_base;
|
| 420 |
|
|
bridgereg_t resp_bss_device;
|
| 421 |
|
|
int resp_bss_pmu_uctr;
|
| 422 |
|
|
int resp_bss_d32_uctr;
|
| 423 |
|
|
int resp_bss_d64_uctr;
|
| 424 |
|
|
iopaddr_t resp_bss_d64_base;
|
| 425 |
|
|
unsigned resp_bss_d64_flags;
|
| 426 |
|
|
iopaddr_t resp_bss_d32_base;
|
| 427 |
|
|
unsigned resp_bss_d32_flags;
|
| 428 |
|
|
atomic_t resp_bss_ext_ates_active;
|
| 429 |
|
|
volatile unsigned *resp_bss_cmd_pointer;
|
| 430 |
|
|
unsigned resp_bss_cmd_shadow;
|
| 431 |
|
|
int resp_bs_rrb_valid;
|
| 432 |
|
|
int resp_bs_rrb_valid_v1;
|
| 433 |
|
|
int resp_bs_rrb_valid_v2;
|
| 434 |
|
|
int resp_bs_rrb_valid_v3;
|
| 435 |
|
|
int resp_bs_rrb_res;
|
| 436 |
|
|
bridgereg_t resp_b_resp;
|
| 437 |
|
|
bridgereg_t resp_b_int_device;
|
| 438 |
|
|
bridgereg_t resp_b_int_enable;
|
| 439 |
|
|
bridgereg_t resp_b_int_host;
|
| 440 |
|
|
picreg_t resp_p_int_enable;
|
| 441 |
|
|
picreg_t resp_p_int_host;
|
| 442 |
|
|
struct pcibr_slot_func_info_resp_s {
|
| 443 |
|
|
int resp_f_status;
|
| 444 |
|
|
char resp_f_slot_name[MAXDEVNAME];
|
| 445 |
|
|
char resp_f_bus;
|
| 446 |
|
|
char resp_f_slot;
|
| 447 |
|
|
char resp_f_func;
|
| 448 |
|
|
char resp_f_master_name[MAXDEVNAME];
|
| 449 |
|
|
void *resp_f_pops;
|
| 450 |
|
|
error_handler_f *resp_f_efunc;
|
| 451 |
|
|
error_handler_arg_t resp_f_einfo;
|
| 452 |
|
|
int resp_f_vendor;
|
| 453 |
|
|
int resp_f_device;
|
| 454 |
|
|
|
| 455 |
|
|
struct {
|
| 456 |
|
|
char resp_w_space[16];
|
| 457 |
|
|
iopaddr_t resp_w_base;
|
| 458 |
|
|
size_t resp_w_size;
|
| 459 |
|
|
} resp_f_window[6];
|
| 460 |
|
|
|
| 461 |
|
|
unsigned resp_f_rbase;
|
| 462 |
|
|
unsigned resp_f_rsize;
|
| 463 |
|
|
int resp_f_ibit[4];
|
| 464 |
|
|
int resp_f_att_det_error;
|
| 465 |
|
|
|
| 466 |
|
|
} resp_func[8];
|
| 467 |
|
|
};
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
/*
|
| 471 |
|
|
* PCI specific errors, interpreted by pciconfig command
|
| 472 |
|
|
*/
|
| 473 |
|
|
|
| 474 |
|
|
/* EPERM 1 */
|
| 475 |
|
|
#define PCI_SLOT_ALREADY_UP 2 /* slot already up */
|
| 476 |
|
|
#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */
|
| 477 |
|
|
#define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */
|
| 478 |
|
|
/* EIO 5 */
|
| 479 |
|
|
/* ENXIO 6 */
|
| 480 |
|
|
#define PCI_L1_ERR 7 /* L1 console command error */
|
| 481 |
|
|
#define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */
|
| 482 |
|
|
#define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */
|
| 483 |
|
|
#define PCI_NOT_A_SLOT 10 /* slot is invalid */
|
| 484 |
|
|
#define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */
|
| 485 |
|
|
/* ENOMEM 12 */
|
| 486 |
|
|
#define PCI_NO_DRIVER 13 /* no driver for device */
|
| 487 |
|
|
/* EFAULT 14 */
|
| 488 |
|
|
#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */
|
| 489 |
|
|
/* EBUSY 16 */
|
| 490 |
|
|
#define PCI_SLOT_RESET_ERR 17 /* slot reset error */
|
| 491 |
|
|
#define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */
|
| 492 |
|
|
/* ENODEV 19 */
|
| 493 |
|
|
#define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */
|
| 494 |
|
|
#define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */
|
| 495 |
|
|
/* EINVAL 22 */
|
| 496 |
|
|
#define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */
|
| 497 |
|
|
#define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */
|
| 498 |
|
|
#define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */
|
| 499 |
|
|
#define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */
|
| 500 |
|
|
/* EFBIG 27 */
|
| 501 |
|
|
#define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */
|
| 502 |
|
|
#define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */
|
| 503 |
|
|
/* ERANGE 34 */
|
| 504 |
|
|
/* EUNATCH 42 */
|
| 505 |
|
|
|
| 506 |
|
|
#endif /* _ASM_SN_PCI_PCIBR_H */
|
