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phoenix |
/* $Id: pciio_private.h,v 1.1.1.1 2004-04-15 02:42:52 phoenix Exp $
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
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#define _ASM_SN_PCI_PCIIO_PRIVATE_H
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#include <asm/sn/pci/pciio.h>
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#include <asm/sn/pci/pci_defs.h>
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/*
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* pciio_private.h -- private definitions for pciio
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* PCI drivers should NOT include this file.
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*/
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#ident "sys/PCI/pciio_private: $Revision: 1.1.1.1 $"
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/*
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* All PCI providers set up PIO using this information.
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*/
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struct pciio_piomap_s {
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unsigned pp_flags; /* PCIIO_PIOMAP flags */
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vertex_hdl_t pp_dev; /* associated pci card */
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pciio_slot_t pp_slot; /* which slot the card is in */
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pciio_space_t pp_space; /* which address space */
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iopaddr_t pp_pciaddr; /* starting offset of mapping */
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size_t pp_mapsz; /* size of this mapping */
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caddr_t pp_kvaddr; /* kernel virtual address to use */
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};
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/*
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* All PCI providers set up DMA using this information.
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*/
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struct pciio_dmamap_s {
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unsigned pd_flags; /* PCIIO_DMAMAP flags */
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vertex_hdl_t pd_dev; /* associated pci card */
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pciio_slot_t pd_slot; /* which slot the card is in */
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};
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/*
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* All PCI providers set up interrupts using this information.
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*/
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struct pciio_intr_s {
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unsigned pi_flags; /* PCIIO_INTR flags */
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vertex_hdl_t pi_dev; /* associated pci card */
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device_desc_t pi_dev_desc; /* override device descriptor */
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pciio_intr_line_t pi_lines; /* which interrupt line(s) */
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intr_func_t pi_func; /* handler function (when connected) */
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intr_arg_t pi_arg; /* handler parameter (when connected) */
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cpuid_t pi_mustruncpu; /* Where we must run. */
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int pi_irq; /* IRQ assigned */
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int pi_cpu; /* cpu assigned */
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};
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/* PCIIO_INTR (pi_flags) flags */
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#define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */
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#define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */
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/*
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* Some PCI provider implementations keep track of PCI window Base Address
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* Register (BAR) address range assignment via the rmalloc()/rmfree() arena
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* management routines. These implementations use the following data
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* structure for each allocation address space (e.g. memory, I/O, small
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* window, etc.).
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*
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* The ``page size'' encodes the minimum allocation unit and must be a power
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* of 2. The main use of this allocation ``page size'' is to control the
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* number of free address ranges that the mapping allocation software will
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* need to track. Smaller values will allow more efficient use of the address
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* ranges but will result in much larger allocation map structures ... For
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* instance, if we want to manage allocations for a 256MB address range,
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* choosing a 1MB allocation page size will result in up to 1MB being wasted
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* for allocation requests smaller than 1MB. The worst case allocation
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* pattern for the allocation software to track would be a pattern of 1MB
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* allocated, 1MB free. This results in the need to track up to 128 free
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* ranges.
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*/
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struct pciio_win_map_s {
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struct map *wm_map; /* window address map */
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int wm_page_size; /* allocation ``page size'' */
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};
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/*
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* Opaque structure used to keep track of window allocation information.
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*/
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struct pciio_win_alloc_s {
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struct resource *wa_resource; /* window map allocation resource */
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unsigned long wa_base; /* allocation starting page number */
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size_t wa_pages; /* number of pages in allocation */
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};
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/*
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* Each PCI Card has one of these.
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*/
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struct pciio_info_s {
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char *c_fingerprint;
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vertex_hdl_t c_vertex; /* back pointer to vertex */
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pciio_bus_t c_bus; /* which bus the card is in */
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pciio_slot_t c_slot; /* which slot the card is in */
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pciio_function_t c_func; /* which func (on multi-func cards) */
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pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */
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pciio_device_id_t c_device; /* PCI card "device" code */
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vertex_hdl_t c_master; /* PCI bus provider */
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arbitrary_info_t c_mfast; /* cached fastinfo from c_master */
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pciio_provider_t *c_pops; /* cached provider from c_master */
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error_handler_f *c_efunc; /* error handling function */
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error_handler_arg_t c_einfo; /* first parameter for efunc */
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struct pciio_win_info_s { /* state of BASE regs */
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pciio_space_t w_space;
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iopaddr_t w_base;
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size_t w_size;
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int w_devio_index; /* DevIO[] register used to
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access this window */
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struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */
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} c_window[PCI_CFG_BASE_ADDRS + 1];
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#define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */
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#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */
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#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */
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pciio_piospace_t c_piospace; /* additional I/O spaces allocated */
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};
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extern char pciio_info_fingerprint[];
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#endif /* _ASM_SN_PCI_PCIIO_PRIVATE_H */
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