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phoenix |
/*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2001, 2002-2003 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _SHUB_MD_H
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#define _SHUB_MD_H
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/* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced,
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contiguous regions, or "software banks". On SN2, software bank n begins at
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addresses n * 16GB, 0 <= n < 4. Each bank has a 16GB address space. If
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the 4 dimms do not use up this space there will be holes between the
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banks. Even with these holes the whole memory space within a bank is
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not addressable address space. The top 1/32 of each bank is directory
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memory space and is accessible through bist only.
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Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets
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each. A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms
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each. The data is stripped across the 4 memory busses so all dimms within
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a dimm bank must have identical capacity dimms. Memory is increased or
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decreased in sets of 4. Each dimm bank has 2 dimms on each side.
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Physical Dimm Bank layout.
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DTR Card0
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------------
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Dimm Bank 3 | MemYL3 | CS 3
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| MemXL3 |
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|----------|
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Dimm Bank 2 | MemYL2 | CS 2
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| MemXL2 |
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|----------|
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Dimm Bank 1 | MemYL1 | CS 1
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| MemXL1 |
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|----------|
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Dimm Bank 0 | MemYL0 | CS 0
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| MemXL0 |
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------------
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BUS BUS
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XL YL
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------------
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| SHUB |
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| MD |
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------------
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BUS BUS
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XR YR
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------------
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Dimm Bank 0 | MemXR0 | CS 0
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| MemYR0 |
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|----------|
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Dimm Bank 1 | MemXR1 | CS 1
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| MemYR1 |
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|----------|
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Dimm Bank 2 | MemXR2 | CS 2
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| MemYR2 |
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|----------|
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Dimm Bank 3 | MemXR3 | CS 3
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| MemYR3 |
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------------
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DTR Card1
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The dimms can be 1 or 2 sided dimms. The size and bankness is defined
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separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register.
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Normally software bank 0 would map directly to physical dimm bank 0. The
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software banks can map to the different physical dimm banks via the
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DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot.
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All the PROM's data structures (promlog variables, klconfig, etc.)
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track memory by the physical dimm bank number. The kernel usually
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tracks memory by the software bank number.
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*/
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/* Preprocessor macros */
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#define MD_MEM_BANKS 4
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#define MD_PHYS_BANKS_PER_DIMM 2 /* dimms may be 2 sided. */
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#define MD_NUM_PHYS_BANKS (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM)
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#define MD_DIMMS_IN_SLOT 4 /* 4 dimms in each dimm bank. aka slot */
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/* Address bits 35,34 control dimm bank access. */
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#define MD_BANK_SHFT 34
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#define MD_BANK_MASK (UINT64_CAST 0x3 << MD_BANK_SHFT )
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#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
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#define MD_BANK_SIZE (UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */
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#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
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/*Address bit 12 selects side of dimm if 2bnk dimms present. */
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#define MD_PHYS_BANK_SEL_SHFT 12
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#define MD_PHYS_BANK_SEL_MASK (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT)
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/* Address bit 7 determines if data resides on X or Y memory system.
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* If addr Bit 7 is set the data resides on Y memory system and
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* the corresponing directory entry reside on the X.
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*/
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#define MD_X_OR_Y_SEL_SHFT 7
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#define MD_X_OR_Y_SEL_MASK (1 << MD_X_OR_Y_SEL_SHFT)
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/* Address bit 8 determines which directory entry of the pair the address
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* corresponds to. If addr Bit 8 is set DirB corresponds to the memory address.
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*/
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#define MD_DIRA_OR_DIRB_SEL_SHFT 8
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#define MD_DIRA_OR_DIRB_SEL_MASK (1 << MD_DIRA_OR_DIRB_SEL_SHFT)
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/* Address bit 11 determines if corresponding directory entry resides
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* on Left or Right memory bus. If addr Bit 11 is set the corresponding
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* directory entry resides on Right memory bus.
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*/
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#define MD_L_OR_R_SEL_SHFT 11
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#define MD_L_OR_R_SEL_MASK (1 << MD_L_OR_R_SEL_SHFT)
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/* DRAM sizes. */
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#define MD_SZ_64_Mb 0x0
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#define MD_SZ_128_Mb 0x1
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#define MD_SZ_256_Mb 0x2
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#define MD_SZ_512_Mb 0x3
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#define MD_SZ_1024_Mb 0x4
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#define MD_SZ_2048_Mb 0x5
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#define MD_SZ_UNUSED 0x7
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#define MD_DIMM_SIZE_BYTES(_size, _2bk) ( \
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( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\
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#define MD_DIMM_SIZE_MBYTES(_size, _2bk) ( \
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( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk))) \
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/* The top 1/32 of each bank is directory memory, and not accessible
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* via normal reads and writes */
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#define MD_DIMM_USER_SIZE(_size) ((_size) * 31 / 32)
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/* Minimum size of a populated bank is 64M (62M usable) */
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#define MIN_BANK_SIZE MD_DIMM_USER_SIZE((64 * 0x100000))
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#define MIN_BANK_STRING "62"
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/*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */
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#define MD_DIMM_100_CL2_0 0x0
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#define MD_DIMM_133_CL2_0 0x1
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#define MD_DIMM_133_CL2_5 0x2
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#define MD_DIMM_160_CL2_0 0x3
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#define MD_DIMM_160_CL2_5 0x4
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#define MD_DIMM_160_CL3_0 0x5
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#define MD_DIMM_200_CL2_0 0x6
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#define MD_DIMM_200_CL2_5 0x7
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#define MD_DIMM_200_CL3_0 0x8
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/* DIMM_CFG fields */
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#define MD_DIMM_SHFT(_dimm) ((_dimm) << 3)
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#define MD_DIMM_SIZE_MASK(_dimm) \
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(SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << \
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(MD_DIMM_SHFT(_dimm)))
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#define MD_DIMM_2BK_MASK(_dimm) \
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(SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << \
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MD_DIMM_SHFT(_dimm))
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#define MD_DIMM_REV_MASK(_dimm) \
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(SH_JNR_DIMM_CFG_DIMM0_REV_MASK << \
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MD_DIMM_SHFT(_dimm))
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#define MD_DIMM_CS_MASK(_dimm) \
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(SH_JNR_DIMM_CFG_DIMM0_CS_MASK << \
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MD_DIMM_SHFT(_dimm))
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#define MD_DIMM_SIZE(_dimm, _cfg) \
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(((_cfg) & MD_DIMM_SIZE_MASK(_dimm)) \
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>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT))
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#define MD_DIMM_TWO_SIDED(_dimm,_cfg) \
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( ((_cfg) & MD_DIMM_2BK_MASK(_dimm)) \
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>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT))
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#define MD_DIMM_REVERSED(_dimm,_cfg) \
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(((_cfg) & MD_DIMM_REV_MASK(_dimm)) \
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>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT))
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#define MD_DIMM_CS(_dimm,_cfg) \
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(((_cfg) & MD_DIMM_CS_MASK(_dimm)) \
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>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT))
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/* Macros to set MMRs that must be set identically to others. */
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#define MD_SET_DIMM_CFG(_n, _value) { \
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REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value); \
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REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value); \
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REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);}
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#define MD_SET_DQCT_CFG(_n, _value) { \
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REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value); \
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REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); }
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#define MD_SET_CFG(_n, _value) { \
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REMOTE_HUB_S(_n, SH_X_CFG,_value); \
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REMOTE_HUB_S(_n, SH_Y_CFG,_value);}
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#define MD_SET_REFRESH_CONTROL(_n, _value) { \
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REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value); \
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REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);}
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#define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) { \
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REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value); \
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REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);}
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#define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) { \
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REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\
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REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);}
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/*
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* There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the
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* LB. The data in the left and right DQ MMRs and the LB must match.
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*/
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#define MD_SET_PRESENT_VEC(_n, _vec, _value) { \
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REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
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_value); \
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REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
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_value); \
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REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);}
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/*
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* There are 16 Privilege Vector MMRs, 8 in each primary DQ. The data
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* in the corresponding left and right DQ MMRs must match. Each MMR
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* pair is used for a single partition.
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*/
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#define MD_SET_PRI_VEC(_n, _vec, _value) { \
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REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
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_value); \
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REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
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_value);}
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/*
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* There are 16 Local/Remote MMRs, 8 in each primary DQ. The data in
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* the corresponding left and right DQ MMRs must match. Each MMR pair
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* is used for a single partition.
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*/
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#define MD_SET_LOC_VEC(_n, _vec, _value) { \
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REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
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_value); \
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REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
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_value);}
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/* Memory BIST CMDS */
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#define MD_DIMM_INIT_MODE_SET 0x0
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#define MD_DIMM_INIT_REFRESH 0x1
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#define MD_DIMM_INIT_PRECHARGE 0x2
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#define MD_DIMM_INIT_BURST_TERM 0x6
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#define MD_DIMM_INIT_NOP 0x7
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#define MD_DIMM_BIST_READ 0x10
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#define MD_FILL_DIR 0x20
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#define MD_FILL_DATA 0x30
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#define MD_FILL_DIR_ACCESS 0X40
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#define MD_READ_DIR_PAIR 0x50
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#define MD_READ_DIR_TAG 0x60
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/* SH_MMRBIST_CTL macros */
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#define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
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SH_MMRBIST_CTL_FAIL_MASK)
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#define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
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SH_MMRBIST_CTL_IN_PROGRESS_MASK)
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#define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
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SH_MMRBIST_CTL_MEM_IDLE_MASK)
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/* SH_MMRBIST_ERR macros */
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#define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) & \
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SH_MMRBIST_ERR_DETECTED_MASK)
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#endif /* _SHUB_MD_H */
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