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phoenix |
/*
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* Lowlevel hardware stuff for the MIPS based Cobalt microservers.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997 Cobalt Microserver
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* Copyright (C) 1997 Ralf Baechle
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* Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
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*
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*/
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#ifndef __ASM_MIPS_COBALT_H
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#define __ASM_MIPS_COBALT_H
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/*
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* COBALT interrupt enable bits
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*/
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#define COBALT_IE_PCI (1 << 0)
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#define COBALT_IE_FLOPPY (1 << 1)
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#define COBALT_IE_KEYBOARD (1 << 2)
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#define COBALT_IE_SERIAL1 (1 << 3)
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#define COBALT_IE_SERIAL2 (1 << 4)
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#define COBALT_IE_PARALLEL (1 << 5)
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#define COBALT_IE_GPIO (1 << 6)
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#define COBALT_IE_RTC (1 << 7)
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/*
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* PCI defines
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*/
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#define COBALT_IE_ETHERNET (1 << 7)
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#define COBALT_IE_SCSI (1 << 7)
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/*
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* COBALT Interrupt Level definitions.
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* These should match the request IRQ id's.
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*/
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#define COBALT_TIMER_IRQ 0
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#define COBALT_KEYBOARD_IRQ 1
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#define COBALT_QUBE_SLOT_IRQ 9
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#define COBALT_ETH0_IRQ 4
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#define COBALT_ETH1_IRQ 13
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#define COBALT_SCC_IRQ 4
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#define COBALT_SERIAL2_IRQ 4
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#define COBALT_PARALLEL_IRQ 5
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#define COBALT_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */
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#define COBALT_SCSI_IRQ 7
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#define COBALT_SERIAL_IRQ 7
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#define COBALT_RAQ_SCSI_IRQ 4
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/*
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* PCI configuration space manifest constants. These are wired into
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* the board layout according to the PCI spec to enable the software
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* to probe the hardware configuration space in a well defined manner.
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*
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* The PCI_DEVSHFT() macro transforms these values into numbers
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* suitable for passing as the dev parameter to the various
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* pcibios_read/write_config routines.
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*/
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#define COBALT_PCICONF_CPU 0x06
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#define COBALT_PCICONF_ETH0 0x07
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#define COBALT_PCICONF_RAQSCSI 0x08
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#define COBALT_PCICONF_VIA 0x09
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#define COBALT_PCICONF_PCISLOT 0x0A
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#define COBALT_PCICONF_ETH1 0x0C
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/*
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* The Cobalt board id information. The boards have an ID number wired
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* into the VIA that is available in the high nibble of register 94.
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* This register is available in the VIA configuration space through the
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* interface routines qube_pcibios_read/write_config. See cobalt/pci.c
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*/
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#define VIA_COBALT_BRD_ID_REG 0x94
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#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4)
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#define COBALT_BRD_ID_QUBE1 0x3
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#define COBALT_BRD_ID_RAQ1 0x4
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#define COBALT_BRD_ID_QUBE2 0x5
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#define COBALT_BRD_ID_RAQ2 0x6
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/*
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* Galileo chipset access macros for the Cobalt. The base address for
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* the GT64111 chip is 0x14000000
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*/
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#define GT64111_BASE 0x04000000
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#define GALILEO_REG(ofs) (GT64111_BASE + (ofs))
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#define GALILEO_INL(port) (inl(GALILEO_REG(port)))
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#define GALILEO_OUTL(val, port) outl(val, GALILEO_REG(port))
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#define GALILEO_T0EXP 0x0100
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#define GALILEO_ENTC0 0x01
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#define GALILEO_SELTC0 0x02
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#endif /* __ASM_MIPS_COBALT_H */
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