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phoenix |
/*
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*
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* BRIEF MODULE DESCRIPTION
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* ITE 8172 Interrupt Numbering
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _MIPS_ITEINT_H
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#define _MIPS_ITEINT_H
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/*
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* Here's the "strategy":
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* We number the LPC serial irqs from 0 to 15,
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* the local bus irqs from 16 to 31,
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* the pci dev register interrupts from 32 to 47,
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* and the non-maskable ints from 48 to 53.
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*/
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#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
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#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
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#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
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#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
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#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
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#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
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#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
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#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
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#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
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#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
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#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
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#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
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#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
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#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
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#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
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#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
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#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
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#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
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#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
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#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
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#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
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#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
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#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
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#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
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#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
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#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
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#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
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#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
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#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
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#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
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/* 12 - 15 reserved */
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/*
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* Note here that the pci dev registers includes bits for more than
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* just the pci devices.
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*/
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#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
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#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
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#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
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#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
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#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
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#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
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#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
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#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
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#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
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#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
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#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
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#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
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#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
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#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
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#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
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#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
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#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
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#define IT8172_NMI_IRQ_BASE 48
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#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
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#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
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#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
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#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
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#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
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#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
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#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ)
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/* Finally, let's move over here the mips cpu timer interrupt.
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*/
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#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
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/*
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* IT8172 Interrupt Controller Registers
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*/
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struct it8172_intc_regs {
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volatile unsigned short lb_req; /* offset 0 */
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volatile unsigned short lb_mask;
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volatile unsigned short lb_trigger;
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volatile unsigned short lb_level;
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unsigned char pad0[8];
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volatile unsigned short lpc_req; /* offset 0x10 */
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volatile unsigned short lpc_mask;
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volatile unsigned short lpc_trigger;
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volatile unsigned short lpc_level;
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unsigned char pad1[8];
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volatile unsigned short pci_req; /* offset 0x20 */
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volatile unsigned short pci_mask;
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volatile unsigned short pci_trigger;
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volatile unsigned short pci_level;
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unsigned char pad2[8];
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volatile unsigned short nmi_req; /* offset 0x30 */
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volatile unsigned short nmi_mask;
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volatile unsigned short nmi_trigger;
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volatile unsigned short nmi_level;
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unsigned char pad3[6];
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volatile unsigned short nmi_redir; /* offset 0x3E */
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unsigned char pad4[0xBE];
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volatile unsigned short intstatus; /* offset 0xFE */
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};
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#endif /* _MIPS_ITEINT_H */
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