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1276 |
phoenix |
/*
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* Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
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*/
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#ifndef _ASM_JAZZDMA_H
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#define _ASM_JAZZDMA_H
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/*
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* Prototypes and macros
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*/
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extern void vdma_init(void);
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extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
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extern int vdma_free(unsigned long laddr);
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extern int vdma_remap(unsigned long laddr, unsigned long paddr,
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unsigned long size);
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extern unsigned long vdma_phys2log(unsigned long paddr);
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extern unsigned long vdma_log2phys(unsigned long laddr);
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extern void vdma_stats(void); /* for debugging only */
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extern void vdma_enable(int channel);
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extern void vdma_disable(int channel);
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extern void vdma_set_mode(int channel, int mode);
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extern void vdma_set_addr(int channel, long addr);
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extern void vdma_set_count(int channel, int count);
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extern int vdma_get_residue(int channel);
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extern int vdma_get_enable(int channel);
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/*
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* some definitions used by the driver functions
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*/
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#define VDMA_PAGESIZE 4096
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#define VDMA_PGTBL_ENTRIES 4096
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#define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
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#define VDMA_PAGE_EMPTY 0xff000000
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/*
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* Macros to get page no. and offset of a given address
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* Note that VDMA_PAGE() works for physical addresses only
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*/
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#define VDMA_PAGE(a) ((unsigned int)(a) >> 12)
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#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1))
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/*
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* error code returned by vdma_alloc()
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* (See also arch/mips/kernel/jazzdma.c)
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*/
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#define VDMA_ERROR 0xffffffff
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/*
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* VDMA pagetable entry description
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*/
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typedef volatile struct VDMA_PGTBL_ENTRY {
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unsigned int frame; /* physical frame no. */
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unsigned int owner; /* owner of this entry (0=free) */
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} VDMA_PGTBL_ENTRY;
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/*
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* DMA channel control registers
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* in the R4030 MCT_ADR chip
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*/
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#define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */
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/* 0xE0000100,120,140... */
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#define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */
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/* 0xE0000108,128,148... */
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#define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */
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/* 0xE0000110,130,150... */
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#define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */
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/* 0xE0000118,138,158... */
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/* channel enable register bits */
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#define R4030_CHNL_ENABLE (1<<0)
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#define R4030_CHNL_WRITE (1<<1)
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#define R4030_TC_INTR (1<<8)
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#define R4030_MEM_INTR (1<<9)
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#define R4030_ADDR_INTR (1<<10)
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/*
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* Channel mode register bits
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*/
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#define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */
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#define R4030_MODE_ATIME_80 (1)
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#define R4030_MODE_ATIME_120 (2)
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#define R4030_MODE_ATIME_160 (3)
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#define R4030_MODE_ATIME_200 (4)
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#define R4030_MODE_ATIME_240 (5)
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#define R4030_MODE_ATIME_280 (6)
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#define R4030_MODE_ATIME_320 (7)
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#define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */
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#define R4030_MODE_WIDTH_16 (2<<3)
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#define R4030_MODE_WIDTH_32 (3<<3)
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#define R4030_MODE_INTR_EN (1<<5)
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#define R4030_MODE_BURST (1<<6) /* Rev. 2 only */
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#define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */
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#endif /* _ASM_JAZZDMA_H */
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