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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips/] [mips-boards/] [generic.h] - Blame information for rev 1774

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/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Defines of the MIPS boards specific address-MAP, registers, etc.
 */
#ifndef __ASM_MIPS_BOARDS_GENERIC_H
#define __ASM_MIPS_BOARDS_GENERIC_H
 
#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/mips-boards/bonito64.h>
 
/*
 * Display register base.
 */
#ifdef CONFIG_MIPS_SEAD
#define ASCII_DISPLAY_POS_BASE     (KSEG1ADDR(0x1f0005c0))
#else
#define ASCII_DISPLAY_WORD_BASE    (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE     (KSEG1ADDR(0x1f000418))
#endif
 
 
/*
 * Yamon Prom print address.
 */
#define YAMON_PROM_PRINT_ADDR      (KSEG1ADDR(0x1fc00504))
 
 
/*
 * Reset register.
 */
#ifdef CONFIG_MIPS_SEAD
#define SOFTRES_REG       (KSEG1ADDR(0x1e800050))
#define GORESET           0x4d
#else
#define SOFTRES_REG       (KSEG1ADDR(0x1f000500))
#define GORESET           0x42
#endif
 
/*
 * Revision register.
 */
#define MIPS_REVISION_REG                  (KSEG1ADDR(0x1fc00010))
#define MIPS_REVISION_CORID_QED_RM5261     0
#define MIPS_REVISION_CORID_CORE_LV        1
#define MIPS_REVISION_CORID_BONITO64       2
#define MIPS_REVISION_CORID_CORE_20K       3
#define MIPS_REVISION_CORID_CORE_FPGA      4
#define MIPS_REVISION_CORID_CORE_MSC       5
 
#define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f)
 
extern unsigned int mips_revision_corid;
 
#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */

Line No.	Rev	Author	Line
1	1276	phoenix	`/*`
2			`* Carsten Langgaard, carstenl@mips.com`
3			`* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.`
4			`*`
5			`* This program is free software; you can distribute it and/or modify it`
6			`* under the terms of the GNU General Public License (Version 2) as`
7			`* published by the Free Software Foundation.`
8			`*`
9			`* This program is distributed in the hope it will be useful, but WITHOUT`
10			`* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
11			`* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`* for more details.`
13			`*`
14			`* You should have received a copy of the GNU General Public License along`
15			`* with this program; if not, write to the Free Software Foundation, Inc.,`
16			`* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.`
17			`*`
18			`* Defines of the MIPS boards specific address-MAP, registers, etc.`
19			`*/`
20			`#ifndef __ASM_MIPS_BOARDS_GENERIC_H`
21			`#define __ASM_MIPS_BOARDS_GENERIC_H`
22
23			`#include <linux/config.h>`
24			`#include <asm/addrspace.h>`
25			`#include <asm/byteorder.h>`
26			`#include <asm/mips-boards/bonito64.h>`
27
28			`/*`
29			`* Display register base.`
30			`*/`
31			`#ifdef CONFIG_MIPS_SEAD`
32			`#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))`
33			`#else`
34			`#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))`
35			`#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))`
36			`#endif`
37
38
39			`/*`
40			`* Yamon Prom print address.`
41			`*/`
42			`#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))`
43
44
45			`/*`
46			`* Reset register.`
47			`*/`
48			`#ifdef CONFIG_MIPS_SEAD`
49			`#define SOFTRES_REG (KSEG1ADDR(0x1e800050))`
50			`#define GORESET 0x4d`
51			`#else`
52			`#define SOFTRES_REG (KSEG1ADDR(0x1f000500))`
53			`#define GORESET 0x42`
54			`#endif`
55
56			`/*`
57			`* Revision register.`
58			`*/`
59			`#define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))`
60			`#define MIPS_REVISION_CORID_QED_RM5261 0`
61			`#define MIPS_REVISION_CORID_CORE_LV 1`
62			`#define MIPS_REVISION_CORID_BONITO64 2`
63			`#define MIPS_REVISION_CORID_CORE_20K 3`
64			`#define MIPS_REVISION_CORID_CORE_FPGA 4`
65			`#define MIPS_REVISION_CORID_CORE_MSC 5`
66
67			`#define MIPS_REVISION_CORID ((((volatile u32 )(MIPS_REVISION_REG)) >> 10) & 0x3f)`
68
69			`extern unsigned int mips_revision_corid;`
70
71			`#endif /* __ASM_MIPS_BOARDS_GENERIC_H */`

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips/] [mips-boards/] [generic.h] - Blame information for rev 1774