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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips/] [mips-boards/] [malta.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 1276 phoenix
/*
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 * Carsten Langgaard, carstenl@mips.com
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 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
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 *
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 *  This program is free software; you can distribute it and/or modify it
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 *  under the terms of the GNU General Public License (Version 2) as
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 *  published by the Free Software Foundation.
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 *
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 *  This program is distributed in the hope it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 *  for more details.
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 *
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 *  You should have received a copy of the GNU General Public License along
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 *  with this program; if not, write to the Free Software Foundation, Inc.,
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 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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 *
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 * Defines of the Malta board specific address-MAP, registers, etc.
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 */
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#ifndef __ASM_MIPS_BOARDS_MALTA_H
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#define __ASM_MIPS_BOARDS_MALTA_H
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#include <asm/addrspace.h>
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#include <asm/io.h>
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/*
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 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
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 * Bonito system controllers.
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 */
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#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
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#define MALTA_BONITO_PORT_BASE  (KSEG1ADDR(0x1fd00000))
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#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
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static inline unsigned long get_gt_port_base(unsigned long reg)
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{
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        unsigned long addr;
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        addr = GT_READ(reg);
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        return KSEG1ADDR((addr & 0xffff) << 21);
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}
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static inline unsigned long get_msc_port_base(unsigned long reg)
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{
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        unsigned long addr;
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        MSC_READ(reg, addr);
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        return KSEG1ADDR(addr);
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}
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/*
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 * Malta RTC-device indirect register access.
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 */
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#define MALTA_RTC_ADR_REG       0x70
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#define MALTA_RTC_DAT_REG       0x71
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/*
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 * Malta SMSC FDC37M817 Super I/O Controller register.
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 */
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#define SMSC_CONFIG_REG         0x3f0
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#define SMSC_DATA_REG           0x3f1
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#define SMSC_CONFIG_DEVNUM      0x7
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#define SMSC_CONFIG_ACTIVATE    0x30
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#define SMSC_CONFIG_ENTER       0x55
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#define SMSC_CONFIG_EXIT        0xaa
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#define SMSC_CONFIG_DEVNUM_FLOPPY     0
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#define SMSC_CONFIG_ACTIVATE_ENABLE   1
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#define SMSC_WRITE(x,a)     outb(x,a)
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#define MALTA_JMPRS_REG         (KSEG1ADDR(0x1f000210))
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#endif /* __ASM_MIPS_BOARDS_MALTA_H */

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