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phoenix |
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Register definitions for Intel PIIX4 South Bridge Device.
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*/
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#ifndef __ASM_MIPS_BOARDS_PIIX4_H
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#define __ASM_MIPS_BOARDS_PIIX4_H
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/************************************************************************
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* IO register offsets
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************************************************************************/
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#define PIIX4_ICTLR1_ICW1 0x20
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#define PIIX4_ICTLR1_ICW2 0x21
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#define PIIX4_ICTLR1_ICW3 0x21
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#define PIIX4_ICTLR1_ICW4 0x21
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#define PIIX4_ICTLR2_ICW1 0xa0
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#define PIIX4_ICTLR2_ICW2 0xa1
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#define PIIX4_ICTLR2_ICW3 0xa1
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#define PIIX4_ICTLR2_ICW4 0xa1
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#define PIIX4_ICTLR1_OCW1 0x21
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#define PIIX4_ICTLR1_OCW2 0x20
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#define PIIX4_ICTLR1_OCW3 0x20
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#define PIIX4_ICTLR1_OCW4 0x20
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#define PIIX4_ICTLR2_OCW1 0xa1
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#define PIIX4_ICTLR2_OCW2 0xa0
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#define PIIX4_ICTLR2_OCW3 0xa0
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#define PIIX4_ICTLR2_OCW4 0xa0
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/************************************************************************
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* Register encodings.
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************************************************************************/
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#define PIIX4_OCW2_NSEOI (0x1 << 5)
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#define PIIX4_OCW2_SEOI (0x3 << 5)
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#define PIIX4_OCW2_RNSEOI (0x5 << 5)
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#define PIIX4_OCW2_RAEOIS (0x4 << 5)
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#define PIIX4_OCW2_RAEOIC (0x0 << 5)
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#define PIIX4_OCW2_RSEOI (0x7 << 5)
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#define PIIX4_OCW2_SP (0x6 << 5)
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#define PIIX4_OCW2_NOP (0x2 << 5)
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#define PIIX4_OCW2_SEL (0x0 << 3)
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#define PIIX4_OCW2_ILS_0 0
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#define PIIX4_OCW2_ILS_1 1
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#define PIIX4_OCW2_ILS_2 2
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#define PIIX4_OCW2_ILS_3 3
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#define PIIX4_OCW2_ILS_4 4
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#define PIIX4_OCW2_ILS_5 5
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#define PIIX4_OCW2_ILS_6 6
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#define PIIX4_OCW2_ILS_7 7
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#define PIIX4_OCW2_ILS_8 0
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#define PIIX4_OCW2_ILS_9 1
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#define PIIX4_OCW2_ILS_10 2
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#define PIIX4_OCW2_ILS_11 3
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#define PIIX4_OCW2_ILS_12 4
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#define PIIX4_OCW2_ILS_13 5
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#define PIIX4_OCW2_ILS_14 6
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#define PIIX4_OCW2_ILS_15 7
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#define PIIX4_OCW3_SEL (0x1 << 3)
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#define PIIX4_OCW3_IRR 0x2
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#define PIIX4_OCW3_ISR 0x3
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#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
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