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1276 |
phoenix |
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SERIAL_H
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#define _ASM_SERIAL_H
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#include <linux/config.h>
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#include <asm/jazz.h>
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/*
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* This assumes you have a 1.8432 MHz clock for your UART.
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*
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* It'd be nice if someone built a serial card with a 24.576 MHz
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* clock, since the 16550A is capable of handling a top speed of 1.5
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* megabits/second; but this requires the faster clock.
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*/
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#define BASE_BAUD ( 1843200 / 16 )
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#ifndef CONFIG_OLIVETTI_M700
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/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
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exactly which ones ... XXX */
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#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
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#else
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/* but the M700 isn't such a strange beast */
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#define JAZZ_BASE_BAUD BASE_BAUD
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#endif
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/* Standard COM flags (except for COM4, because of the 8514 problem) */
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
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#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
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#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
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#endif
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define FOURPORT_FLAGS ASYNC_FOURPORT
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#define ACCENT_FLAGS 0
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#define BOCA_FLAGS 0
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#define HUB6_FLAGS 0
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#define RS_TABLE_SIZE 64
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#else
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#define RS_TABLE_SIZE
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#endif
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/*
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* The following define the access methods for the HUB6 card. All
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* access is through two ports for all 24 possible chips. The card is
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* selected through the high 2 bits, the port on that card with the
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* "middle" 3 bits, and the register on that port with the bottom
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* 3 bits.
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*
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* While the access port and interrupt is configurable, the default
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* port locations are 0x302 for the port control register, and 0x303
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* for the data read/write register. Normally, the interrupt is at irq3
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* but can be anything from 3 to 7 inclusive. Note that using 3 will
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* require disabling com2.
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*/
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#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
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#ifdef CONFIG_MIPS_JAZZ
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#define _JAZZ_SERIAL_INIT(int, base) \
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{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
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.io_type = SERIAL_IO_MEM }
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#define JAZZ_SERIAL_PORT_DEFNS \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
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#else
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#define JAZZ_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_ATLAS
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#include <asm/mips-boards/atlas.h>
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#include <asm/mips-boards/atlasint.h>
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#define ATLAS_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, ATLAS_BASE_BAUD, ATLAS_UART_REGS_BASE, ATLASINT_UART, STD_COM_FLAGS }, /* ttyS0 */
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#else
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#define ATLAS_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_SEAD
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#include <asm/mips-boards/sead.h>
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#include <asm/mips-boards/seadint.h>
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#define SEAD_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, SEAD_BASE_BAUD, SEAD_UART0_REGS_BASE, SEADINT_UART0, STD_COM_FLAGS }, /* ttyS0 */
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#else
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#define SEAD_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_COBALT
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#include <asm/cobalt/cobalt.h>
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#define COBALT_BASE_BAUD (18432000 / 16)
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#define COBALT_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
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#else
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#define COBALT_SERIAL_PORT_DEFNS
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#endif
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/*
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* Both Galileo boards have the same UART mappings.
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*/
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#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
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#include <asm/gt64120/gt64120.h>
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#include <asm/galileo-boards/ev96100int.h>
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#define EV96100_SERIAL_PORT_DEFNS \
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{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }, \
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{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM },
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#else
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#define EV96100_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_ITE8172
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#include <asm/it8712.h>
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#define ITE_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
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.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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{ .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
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.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 0 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
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.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 1 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
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.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
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#else
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#define ITE_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_IVR
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#define IVR_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
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.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 1 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
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.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
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#else
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#define IVR_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_AU1X00_UART
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#include <asm/au1000.h>
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, .irq = AU1000_UART0_INT, \
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.flags = STD_COM_FLAGS, .type = 1 }, \
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{ .baud_base = 0, .port = UART1_ADDR, .irq = AU1000_UART1_INT, \
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.flags = STD_COM_FLAGS, .type = 1 }, \
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{ .baud_base = 0, .port = UART2_ADDR, .irq = AU1000_UART2_INT, \
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.flags = STD_COM_FLAGS, .type = 1 }, \
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{ .baud_base = 0, .port = UART3_ADDR, .irq = AU1000_UART3_INT, \
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.flags = STD_COM_FLAGS, .type = 1 },
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#else
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#define AU1000_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_TOSHIBA_JMR3927
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#include <asm/jmr3927/jmr3927.h>
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#define TXX927_SERIAL_PORT_DEFNS \
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{ .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
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.flags = UART0_FLAGS, .type = 1 }, \
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{ .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
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.flags = UART1_FLAGS, .type = 1 },
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#else
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#define TXX927_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
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#define STD_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
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{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
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{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
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{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define EXTRA_SERIAL_PORT_DEFNS \
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{ 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
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{ 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
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{ 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
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{ 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
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{ 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
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{ 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
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{ 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
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{ 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
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{ 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
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{ 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
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{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
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{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
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{ 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
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{ 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
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{ 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
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{ 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
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{ 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
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{ 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
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{ 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
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{ 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
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{ 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
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{ 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
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{ 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
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{ 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
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{ 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
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{ 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
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{ 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
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{ 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
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#else /* CONFIG_SERIAL_MANY_PORTS */
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#define EXTRA_SERIAL_PORT_DEFNS
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#endif /* CONFIG_SERIAL_MANY_PORTS */
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| 229 |
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#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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#define STD_SERIAL_PORT_DEFNS
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#define EXTRA_SERIAL_PORT_DEFNS
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#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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| 234 |
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/* You can have up to four HUB6's in the system, but I've only
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* included two cards here for a total of twelve ports.
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*/
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| 237 |
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#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
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#define HUB6_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
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#else
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| 252 |
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#define HUB6_SERIAL_PORT_DFNS
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#endif
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| 254 |
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| 255 |
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#ifdef CONFIG_MCA
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| 256 |
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#define MCA_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, 0x3220, 3, STD_COM_FLAGS }, \
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{ 0, BASE_BAUD, 0x3228, 3, STD_COM_FLAGS }, \
|
| 259 |
|
|
{ 0, BASE_BAUD, 0x4220, 3, STD_COM_FLAGS }, \
|
| 260 |
|
|
{ 0, BASE_BAUD, 0x4228, 3, STD_COM_FLAGS }, \
|
| 261 |
|
|
{ 0, BASE_BAUD, 0x5220, 3, STD_COM_FLAGS }, \
|
| 262 |
|
|
{ 0, BASE_BAUD, 0x5228, 3, STD_COM_FLAGS },
|
| 263 |
|
|
#else
|
| 264 |
|
|
#define MCA_SERIAL_PORT_DFNS
|
| 265 |
|
|
#endif
|
| 266 |
|
|
|
| 267 |
|
|
#ifdef CONFIG_MOMENCO_OCELOT
|
| 268 |
|
|
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
| 269 |
|
|
#define OCELOT_BASE_BAUD ( 20000000 / 16 )
|
| 270 |
|
|
|
| 271 |
|
|
#define OCELOT_SERIAL1_IRQ 4
|
| 272 |
|
|
#define OCELOT_SERIAL1_BASE 0xe0001020
|
| 273 |
|
|
|
| 274 |
|
|
#define _OCELOT_SERIAL_INIT(int, base) \
|
| 275 |
|
|
{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
|
| 276 |
|
|
.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
|
| 277 |
|
|
.io_type = SERIAL_IO_MEM }
|
| 278 |
|
|
#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
|
| 279 |
|
|
_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
|
| 280 |
|
|
#else
|
| 281 |
|
|
#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
|
| 282 |
|
|
#endif
|
| 283 |
|
|
|
| 284 |
|
|
#ifdef CONFIG_MOMENCO_OCELOT_G
|
| 285 |
|
|
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
| 286 |
|
|
#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
|
| 287 |
|
|
|
| 288 |
|
|
#define OCELOT_G_SERIAL1_IRQ 4
|
| 289 |
|
|
#if 0
|
| 290 |
|
|
#define OCELOT_G_SERIAL1_BASE 0xe0001020
|
| 291 |
|
|
#else
|
| 292 |
|
|
#define OCELOT_G_SERIAL1_BASE 0xfd000020
|
| 293 |
|
|
#endif
|
| 294 |
|
|
|
| 295 |
|
|
#define _OCELOT_G_SERIAL_INIT(int, base) \
|
| 296 |
|
|
{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
|
| 297 |
|
|
.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
|
| 298 |
|
|
.io_type = SERIAL_IO_MEM }
|
| 299 |
|
|
#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
| 300 |
|
|
_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
|
| 301 |
|
|
#else
|
| 302 |
|
|
#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
|
| 303 |
|
|
#endif
|
| 304 |
|
|
|
| 305 |
|
|
#ifdef CONFIG_MOMENCO_OCELOT_C
|
| 306 |
|
|
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
| 307 |
|
|
#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
|
| 308 |
|
|
|
| 309 |
|
|
#define OCELOT_C_SERIAL1_IRQ 80
|
| 310 |
|
|
#define OCELOT_C_SERIAL1_BASE 0xfd000020
|
| 311 |
|
|
|
| 312 |
|
|
#define OCELOT_C_SERIAL2_IRQ 81
|
| 313 |
|
|
#define OCELOT_C_SERIAL2_BASE 0xfd000000
|
| 314 |
|
|
|
| 315 |
|
|
#define _OCELOT_C_SERIAL_INIT(int, base) \
|
| 316 |
|
|
{ baud_base: OCELOT_C_BASE_BAUD, irq: int, flags: STD_COM_FLAGS,\
|
| 317 |
|
|
iomem_base: (u8 *) base, iomem_reg_shift: 2, \
|
| 318 |
|
|
io_type: SERIAL_IO_MEM }
|
| 319 |
|
|
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
| 320 |
|
|
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
|
| 321 |
|
|
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
|
| 322 |
|
|
#else
|
| 323 |
|
|
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
|
| 324 |
|
|
#endif
|
| 325 |
|
|
|
| 326 |
|
|
#ifdef CONFIG_MOMENCO_JAGUAR_ATX
|
| 327 |
|
|
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
| 328 |
|
|
#define JAGUAR_ATX_BASE_BAUD ( 20000000 / 16 )
|
| 329 |
|
|
|
| 330 |
|
|
#define JAGUAR_ATX_SERIAL1_IRQ 7
|
| 331 |
|
|
#define JAGUAR_ATX_SERIAL1_BASE 0xfffffffffd000020
|
| 332 |
|
|
|
| 333 |
|
|
#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
|
| 334 |
|
|
{ baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
|
| 335 |
|
|
flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
|
| 336 |
|
|
iomem_base: (u8 *) base, iomem_reg_shift: 2, \
|
| 337 |
|
|
io_type: SERIAL_IO_MEM }
|
| 338 |
|
|
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
|
| 339 |
|
|
_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
|
| 340 |
|
|
#else
|
| 341 |
|
|
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
|
| 342 |
|
|
#endif
|
| 343 |
|
|
|
| 344 |
|
|
#ifdef CONFIG_TITAN_SERIAL
|
| 345 |
|
|
/* 16552 20 MHz crystal */
|
| 346 |
|
|
#define TITAN_SERIAL_BASE_BAUD ( 20000000 / 16 )
|
| 347 |
|
|
#define TITAN_SERIAL_IRQ XXX
|
| 348 |
|
|
#define TITAN_SERIAL_BASE 0xffffffff
|
| 349 |
|
|
|
| 350 |
|
|
#define _TITAN_SERIAL_INIT(int, base) \
|
| 351 |
|
|
{ baud_base: TITAN_SERIAL_BASE_BAUD, irq: int, \
|
| 352 |
|
|
flags: STD_COM_FLAGS, iomem_base: (u8 *) base, \
|
| 353 |
|
|
iomem_reg_shift: 2, io_type: SERIAL_IO_MEM \
|
| 354 |
|
|
}
|
| 355 |
|
|
|
| 356 |
|
|
#define TITAN_SERIAL_PORT_DEFNS \
|
| 357 |
|
|
_TITAN_SERIAL_INIT(TITAN_SERIAL_IRQ, TITAN_SERIAL_BASE)
|
| 358 |
|
|
#else
|
| 359 |
|
|
#define TITAN_SERIAL_PORT_DEFNS
|
| 360 |
|
|
#endif
|
| 361 |
|
|
|
| 362 |
|
|
#ifdef CONFIG_SGI_IP27
|
| 363 |
|
|
|
| 364 |
|
|
/*
|
| 365 |
|
|
* Note about serial ports and consoles:
|
| 366 |
|
|
* For console output, everyone uses the IOC3 UARTA (offset 0x178)
|
| 367 |
|
|
* connected to the master node (look in ip27_setup_console() and
|
| 368 |
|
|
* ip27prom_console_write()).
|
| 369 |
|
|
*
|
| 370 |
|
|
* For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
|
| 371 |
|
|
* addresses on a partitioned machine. Since we currently use the ioc3
|
| 372 |
|
|
* serial ports, we use dynamic serial port discovery that the serial.c
|
| 373 |
|
|
* driver uses for pci/pnp ports (there is an entry for the SGI ioc3
|
| 374 |
|
|
* boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
|
| 375 |
|
|
* than UARTB's, although UARTA on o200s has traditionally been known as
|
| 376 |
|
|
* port 0. So, we just use one serial port from each ioc3 (since the
|
| 377 |
|
|
* serial driver adds addresses to get to higher ports).
|
| 378 |
|
|
*
|
| 379 |
|
|
* The first one to do a register_console becomes the preferred console
|
| 380 |
|
|
* (if there is no kernel command line console= directive). /dev/console
|
| 381 |
|
|
* (ie 5, 1) is then "aliased" into the device number returned by the
|
| 382 |
|
|
* "device" routine referred to in this console structure
|
| 383 |
|
|
* (ip27prom_console_dev).
|
| 384 |
|
|
*
|
| 385 |
|
|
* Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working
|
| 386 |
|
|
* around ioc3 oddities in this respect.
|
| 387 |
|
|
*
|
| 388 |
|
|
* The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
|
| 389 |
|
|
* (IOC3_BAUD = (22000000 / (3*16)))
|
| 390 |
|
|
*
|
| 391 |
|
|
* At the moment this is only a skeleton definition as we register all serials
|
| 392 |
|
|
* at runtime.
|
| 393 |
|
|
*/
|
| 394 |
|
|
|
| 395 |
|
|
#define IP27_SERIAL_PORT_DEFNS
|
| 396 |
|
|
#else
|
| 397 |
|
|
#define IP27_SERIAL_PORT_DEFNS
|
| 398 |
|
|
#endif /* CONFIG_SGI_IP27 */
|
| 399 |
|
|
|
| 400 |
|
|
#ifdef CONFIG_DDB5477
|
| 401 |
|
|
#include <asm/ddb5xxx/ddb5477.h>
|
| 402 |
|
|
#define DDB5477_SERIAL_PORT_DEFNS \
|
| 403 |
|
|
{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
|
| 404 |
|
|
.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
|
| 405 |
|
|
.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
|
| 406 |
|
|
{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
|
| 407 |
|
|
.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
|
| 408 |
|
|
.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
|
| 409 |
|
|
#else
|
| 410 |
|
|
#define DDB5477_SERIAL_PORT_DEFNS
|
| 411 |
|
|
#endif
|
| 412 |
|
|
|
| 413 |
|
|
#define SERIAL_PORT_DFNS \
|
| 414 |
|
|
ATLAS_SERIAL_PORT_DEFNS \
|
| 415 |
|
|
AU1000_SERIAL_PORT_DEFNS \
|
| 416 |
|
|
COBALT_SERIAL_PORT_DEFNS \
|
| 417 |
|
|
DDB5477_SERIAL_PORT_DEFNS \
|
| 418 |
|
|
EV96100_SERIAL_PORT_DEFNS \
|
| 419 |
|
|
EXTRA_SERIAL_PORT_DEFNS \
|
| 420 |
|
|
HUB6_SERIAL_PORT_DFNS \
|
| 421 |
|
|
ITE_SERIAL_PORT_DEFNS \
|
| 422 |
|
|
IVR_SERIAL_PORT_DEFNS \
|
| 423 |
|
|
JAZZ_SERIAL_PORT_DEFNS \
|
| 424 |
|
|
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
|
| 425 |
|
|
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
| 426 |
|
|
MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
| 427 |
|
|
MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
|
| 428 |
|
|
SEAD_SERIAL_PORT_DEFNS \
|
| 429 |
|
|
STD_SERIAL_PORT_DEFNS \
|
| 430 |
|
|
TITAN_SERIAL_PORT_DEFNS \
|
| 431 |
|
|
TXX927_SERIAL_PORT_DEFNS
|
| 432 |
|
|
|
| 433 |
|
|
#endif /* _ASM_SERIAL_H */
|
