| 1 |
1276 |
phoenix |
/*
|
| 2 |
|
|
* Copyright 2003 PMC-Sierra
|
| 3 |
|
|
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
|
| 4 |
|
|
*
|
| 5 |
|
|
* Board specific definititions for the PMC-Sierra Yosemite
|
| 6 |
|
|
*
|
| 7 |
|
|
* This program is free software; you can redistribute it and/or modify it
|
| 8 |
|
|
* under the terms of the GNU General Public License as published by the
|
| 9 |
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
| 10 |
|
|
* option) any later version.
|
| 11 |
|
|
*/
|
| 12 |
|
|
|
| 13 |
|
|
#ifndef __TITAN_DEP_H__
|
| 14 |
|
|
#define __TITAN_DEP_H__
|
| 15 |
|
|
|
| 16 |
|
|
#include <asm/addrspace.h> /* for KSEG1ADDR() */
|
| 17 |
|
|
#include <asm/byteorder.h> /* for cpu_to_le32() */
|
| 18 |
|
|
|
| 19 |
|
|
/* Turn on serial */
|
| 20 |
|
|
#define CONFIG_TITAN_SERIAL
|
| 21 |
|
|
|
| 22 |
|
|
/* PCI */
|
| 23 |
|
|
#define TITAN_PCI_BASE 0xbb000000
|
| 24 |
|
|
|
| 25 |
|
|
#define TITAN_WRITE(ofs, data) \
|
| 26 |
|
|
*(volatile u32 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le32(data)
|
| 27 |
|
|
#define TITAN_READ(ofs, data) \
|
| 28 |
|
|
*(data) = le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
|
| 29 |
|
|
#define TITAN_READ_DATA(ofs) \
|
| 30 |
|
|
le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
|
| 31 |
|
|
|
| 32 |
|
|
#define TITAN_WRITE_16(ofs, data) \
|
| 33 |
|
|
*(volatile u16 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le16(data)
|
| 34 |
|
|
#define TITAN_READ_16(ofs, data) \
|
| 35 |
|
|
*(data) = le16_to_cpu(*(volatile u16 *)(TITAN_PCI_BASE+(ofs)))
|
| 36 |
|
|
|
| 37 |
|
|
#define TITAN_WRITE_8(ofs, data) \
|
| 38 |
|
|
*(volatile u8 *)(TITAN_PCI_BASE+(ofs)) = data
|
| 39 |
|
|
#define TITAN_READ_8(ofs, data) \
|
| 40 |
|
|
*(data) = *(volatile u8 *)(TITAN_PCI_BASE+(ofs))
|
| 41 |
|
|
|
| 42 |
|
|
/*
|
| 43 |
|
|
* PCI specific defines
|
| 44 |
|
|
*/
|
| 45 |
|
|
#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
|
| 46 |
|
|
#define TITAN_PCI_0_CONFIG_DATA 0x784
|
| 47 |
|
|
|
| 48 |
|
|
/*
|
| 49 |
|
|
* HT specific defines
|
| 50 |
|
|
*/
|
| 51 |
|
|
#define RM9000x2_HTLINK_REG 0xbb000644
|
| 52 |
|
|
#define RM9000x2_BASE_ADDR 0xbb000000
|
| 53 |
|
|
#define RM9000x2_OCD_HTCFGA 0x06f8
|
| 54 |
|
|
#define RM9000x2_OCD_HTCFGD 0x06fc
|
| 55 |
|
|
|
| 56 |
|
|
/*
|
| 57 |
|
|
* Hypertransport specific macros
|
| 58 |
|
|
*/
|
| 59 |
|
|
#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
|
| 60 |
|
|
#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
|
| 61 |
|
|
#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
|
| 62 |
|
|
|
| 63 |
|
|
#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
|
| 64 |
|
|
#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
|
| 65 |
|
|
#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
|
| 66 |
|
|
|
| 67 |
|
|
#endif
|
| 68 |
|
|
|
