OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips/] [vr41xx/] [tb0226.h] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1276 phoenix
/*
2
 * FILE NAME
3
 *      include/asm-mips/vr41xx/tb0226.h
4
 *
5
 * BRIEF MODULE DESCRIPTION
6
 *      Include file for TANBAC TB0226.
7
 *
8
 * Copyright 2002,2003 Yoichi Yuasa
9
 *                yuasa@hh.iij4u.or.jp
10
 *
11
 *  This program is free software; you can redistribute it and/or modify it
12
 *  under the terms of the GNU General Public License as published by the
13
 *  Free Software Foundation; either version 2 of the License, or (at your
14
 *  option) any later version.
15
 */
16
#ifndef __TANBAC_TB0226_H
17
#define __TANBAC_TB0226_H
18
 
19
#include <asm/addrspace.h>
20
#include <asm/vr41xx/vr41xx.h>
21
 
22
/*
23
 * Board specific address mapping
24
 */
25
#define VR41XX_PCI_MEM1_BASE            0x10000000
26
#define VR41XX_PCI_MEM1_SIZE            0x04000000
27
#define VR41XX_PCI_MEM1_MASK            0x7c000000
28
 
29
#define VR41XX_PCI_MEM2_BASE            0x14000000
30
#define VR41XX_PCI_MEM2_SIZE            0x02000000
31
#define VR41XX_PCI_MEM2_MASK            0x7e000000
32
 
33
#define VR41XX_PCI_IO_BASE              0x16000000
34
#define VR41XX_PCI_IO_SIZE              0x02000000
35
#define VR41XX_PCI_IO_MASK              0x7e000000
36
 
37
#define VR41XX_PCI_IO_START             0x01000000
38
#define VR41XX_PCI_IO_END               0x01ffffff
39
 
40
#define VR41XX_PCI_MEM_START            0x12000000
41
#define VR41XX_PCI_MEM_END              0x15ffffff
42
 
43
#define IO_PORT_BASE                    KSEG1ADDR(VR41XX_PCI_IO_BASE)
44
#define IO_PORT_RESOURCE_START          0
45
#define IO_PORT_RESOURCE_END            VR41XX_PCI_IO_SIZE
46
#define IO_MEM1_RESOURCE_START          VR41XX_PCI_MEM1_BASE
47
#define IO_MEM1_RESOURCE_END            (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE)
48
#define IO_MEM2_RESOURCE_START          VR41XX_PCI_MEM2_BASE
49
#define IO_MEM2_RESOURCE_END            (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE)
50
 
51
/*
52
 * General-Purpose I/O Pin Number
53
 */
54
#define GD82559_1_PIN                   2
55
#define GD82559_2_PIN                   3
56
#define UPD720100_INTA_PIN              4
57
#define UPD720100_INTB_PIN              8
58
#define UPD720100_INTC_PIN              13
59
 
60
/*
61
 * Interrupt Number
62
 */
63
#define GD82559_1_IRQ                   GIU_IRQ(GD82559_1_PIN)
64
#define GD82559_2_IRQ                   GIU_IRQ(GD82559_2_PIN)
65
#define UPD720100_INTA_IRQ              GIU_IRQ(UPD720100_INTA_PIN)
66
#define UPD720100_INTB_IRQ              GIU_IRQ(UPD720100_INTB_PIN)
67
#define UPD720100_INTC_IRQ              GIU_IRQ(UPD720100_INTC_PIN)
68
 
69
#endif /* __TANBAC_TB0226_H */

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.