OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips64/] [ds1286.h] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1275 phoenix
/*
2
 * This file is subject to the terms and conditions of the GNU General Public
3
 * License.  See the file "COPYING" in the main directory of this archive
4
 * for more details.
5
 *
6
 * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
7
 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
8
 * derived from Data Sheet, Copyright Motorola 1984 (!).
9
 * It was written to be part of the Linux operating system.
10
 *
11
 * Copyright (C) 1998, 1999 Ralf Baechle
12
 */
13
#ifndef _ASM_DS1286_h
14
#define _ASM_DS1286_h
15
 
16
#include <asm/mc146818rtc.h>
17
 
18
/**********************************************************************
19
 * register summary
20
 **********************************************************************/
21
#define RTC_HUNDREDTH_SECOND    0
22
#define RTC_SECONDS             1
23
#define RTC_MINUTES             2
24
#define RTC_MINUTES_ALARM       3
25
#define RTC_HOURS               4
26
#define RTC_HOURS_ALARM         5
27
#define RTC_DAY                 6
28
#define RTC_DAY_ALARM           7
29
#define RTC_DATE                8
30
#define RTC_MONTH               9
31
#define RTC_YEAR                10
32
#define RTC_CMD                 11
33
#define RTC_WHSEC               12
34
#define RTC_WSEC                13
35
#define RTC_UNUSED              14
36
 
37
/* RTC_*_alarm is always true if 2 MSBs are set */
38
# define RTC_ALARM_DONT_CARE    0xC0
39
 
40
 
41
/*
42
 * Bits in the month register
43
 */
44
#define RTC_EOSC                0x80
45
#define RTC_ESQW                0x40
46
 
47
/*
48
 * Bits in the Command register
49
 */
50
#define RTC_TDF                 0x01
51
#define RTC_WAF                 0x02
52
#define RTC_TDM                 0x04
53
#define RTC_WAM                 0x08
54
#define RTC_PU_LVL              0x10
55
#define RTC_IBH_LO              0x20
56
#define RTC_IPSW                0x40
57
#define RTC_TE                  0x80
58
 
59
/*
60
 * Conversion between binary and BCD.
61
 */
62
#ifndef BCD_TO_BIN
63
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
64
#endif
65
 
66
#ifndef BIN_TO_BCD
67
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
68
#endif
69
 
70
#endif /* _ASM_DS1286_h */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.