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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-mips64/] [pci/] [bridge.h] - Blame information for rev 1765

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1 1275 phoenix
/*
2
 * This file is subject to the terms and conditions of the GNU General Public
3
 * License.  See the file "COPYING" in the main directory of this archive
4
 * for more details.
5
 *
6
 * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
7
 * revision 1.76.
8
 *
9
 * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
10
 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
11
 */
12
#ifndef _ASM_PCI_BRIDGE_H
13
#define _ASM_PCI_BRIDGE_H
14
 
15
#include <linux/types.h>
16
#include <asm/xtalk/xwidget.h>          /* generic widget header */
17
 
18
/* I/O page size */
19
 
20
#define IOPFNSHIFT              12      /* 4K per mapped page */
21
 
22
#define IOPGSIZE                (1 << IOPFNSHIFT)
23
#define IOPG(x)                 ((x) >> IOPFNSHIFT)
24
#define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
25
 
26
/* Bridge RAM sizes */
27
 
28
#define BRIDGE_ATE_RAM_SIZE     0x00000400      /* 1kB ATE RAM */
29
 
30
#define BRIDGE_CONFIG_BASE      0x20000
31
#define BRIDGE_CONFIG1_BASE     0x28000
32
#define BRIDGE_CONFIG_END       0x30000
33
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
34
 
35
#define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
36
#define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
37
#define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
38
#define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
39
 
40
/* ========================================================================
41
 *    Bridge address map
42
 */
43
 
44
#ifndef __ASSEMBLY__
45
 
46
/*
47
 * All accesses to bridge hardware registers must be done
48
 * using 32-bit loads and stores.
49
 */
50
typedef u32     bridgereg_t;
51
 
52
typedef u64     bridge_ate_t;
53
 
54
/* pointers to bridge ATEs
55
 * are always "pointer to volatile"
56
 */
57
typedef volatile bridge_ate_t  *bridge_ate_p;
58
 
59
/*
60
 * It is generally preferred that hardware registers on the bridge
61
 * are located from C code via this structure.
62
 *
63
 * Generated from Bridge spec dated 04oct95
64
 */
65
 
66
typedef volatile struct bridge_s {
67
        /* Local Registers                             0x000000-0x00FFFF */
68
 
69
        /* standard widget configuration               0x000000-0x000057 */
70
        widget_cfg_t        b_widget;                   /* 0x000000 */
71
 
72
        /* helper fieldnames for accessing bridge widget */
73
 
74
#define b_wid_id                        b_widget.w_id
75
#define b_wid_stat                      b_widget.w_status
76
#define b_wid_err_upper                 b_widget.w_err_upper_addr
77
#define b_wid_err_lower                 b_widget.w_err_lower_addr
78
#define b_wid_control                   b_widget.w_control
79
#define b_wid_req_timeout               b_widget.w_req_timeout
80
#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
81
#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
82
#define b_wid_err_cmdword               b_widget.w_err_cmd_word
83
#define b_wid_llp                       b_widget.w_llp_cfg
84
#define b_wid_tflush                    b_widget.w_tflush
85
 
86
        /* bridge-specific widget configuration 0x000058-0x00007F */
87
        bridgereg_t         _pad_000058;
88
        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
89
        bridgereg_t         _pad_000060;
90
        bridgereg_t         b_wid_resp_upper;           /* 0x000064 */
91
        bridgereg_t         _pad_000068;
92
        bridgereg_t         b_wid_resp_lower;           /* 0x00006C */
93
        bridgereg_t         _pad_000070;
94
        bridgereg_t         b_wid_tst_pin_ctrl;         /* 0x000074 */
95
        bridgereg_t     _pad_000078[2];
96
 
97
        /* PMU & Map 0x000080-0x00008F */
98
        bridgereg_t     _pad_000080;
99
        bridgereg_t     b_dir_map;                      /* 0x000084 */
100
        bridgereg_t     _pad_000088[2];
101
 
102
        /* SSRAM 0x000090-0x00009F */
103
        bridgereg_t     _pad_000090;
104
        bridgereg_t     b_ram_perr;                     /* 0x000094 */
105
        bridgereg_t     _pad_000098[2];
106
 
107
        /* Arbitration 0x0000A0-0x0000AF */
108
        bridgereg_t     _pad_0000A0;
109
        bridgereg_t     b_arb;                          /* 0x0000A4 */
110
        bridgereg_t     _pad_0000A8[2];
111
 
112
        /* Number In A Can 0x0000B0-0x0000BF */
113
        bridgereg_t     _pad_0000B0;
114
        bridgereg_t     b_nic;                          /* 0x0000B4 */
115
        bridgereg_t     _pad_0000B8[2];
116
 
117
        /* PCI/GIO 0x0000C0-0x0000FF */
118
        bridgereg_t     _pad_0000C0;
119
        bridgereg_t     b_bus_timeout;                  /* 0x0000C4 */
120
#define b_pci_bus_timeout b_bus_timeout
121
 
122
        bridgereg_t     _pad_0000C8;
123
        bridgereg_t     b_pci_cfg;                      /* 0x0000CC */
124
        bridgereg_t     _pad_0000D0;
125
        bridgereg_t     b_pci_err_upper;                /* 0x0000D4 */
126
        bridgereg_t     _pad_0000D8;
127
        bridgereg_t     b_pci_err_lower;                /* 0x0000DC */
128
        bridgereg_t     _pad_0000E0[8];
129
#define b_gio_err_lower b_pci_err_lower
130
#define b_gio_err_upper b_pci_err_upper
131
 
132
        /* Interrupt 0x000100-0x0001FF */
133
        bridgereg_t     _pad_000100;
134
        bridgereg_t     b_int_status;                   /* 0x000104 */
135
        bridgereg_t     _pad_000108;
136
        bridgereg_t     b_int_enable;                   /* 0x00010C */
137
        bridgereg_t     _pad_000110;
138
        bridgereg_t     b_int_rst_stat;                 /* 0x000114 */
139
        bridgereg_t     _pad_000118;
140
        bridgereg_t     b_int_mode;                     /* 0x00011C */
141
        bridgereg_t     _pad_000120;
142
        bridgereg_t     b_int_device;                   /* 0x000124 */
143
        bridgereg_t     _pad_000128;
144
        bridgereg_t     b_int_host_err;                 /* 0x00012C */
145
 
146
        struct {
147
                bridgereg_t     __pad;                  /* 0x0001{30,,,68} */
148
                bridgereg_t     addr;                   /* 0x0001{34,,,6C} */
149
        } b_int_addr[8];                                /* 0x000130 */
150
 
151
        bridgereg_t     _pad_000170[36];
152
 
153
        /* Device 0x000200-0x0003FF */
154
        struct {
155
                bridgereg_t     __pad;                  /* 0x0002{00,,,38} */
156
                bridgereg_t     reg;                    /* 0x0002{04,,,3C} */
157
        } b_device[8];                                  /* 0x000200 */
158
 
159
        struct {
160
                bridgereg_t     __pad;                  /* 0x0002{40,,,78} */
161
                bridgereg_t     reg;                    /* 0x0002{44,,,7C} */
162
        } b_wr_req_buf[8];                              /* 0x000240 */
163
 
164
        struct {
165
                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
166
                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
167
        } b_rrb_map[2];                                 /* 0x000280 */
168
#define b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
169
#define b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
170
 
171
        bridgereg_t     _pad_000290;
172
        bridgereg_t     b_resp_status;                  /* 0x000294 */
173
        bridgereg_t     _pad_000298;
174
        bridgereg_t     b_resp_clear;                   /* 0x00029C */
175
 
176
        bridgereg_t     _pad_0002A0[24];
177
 
178
        char            _pad_000300[0x10000 - 0x000300];
179
 
180
        /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
181
        union {
182
                bridge_ate_t    wr;                     /* write-only */
183
                struct {
184
                        bridgereg_t     _p_pad;
185
                        bridgereg_t     rd;             /* read-only */
186
                }                       hi;
187
        }                           b_int_ate_ram[128];
188
 
189
        char    _pad_010400[0x11000 - 0x010400];
190
 
191
        /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
192
        struct {
193
                bridgereg_t     _p_pad;
194
                bridgereg_t     rd;             /* read-only */
195
        } b_int_ate_ram_lo[128];
196
 
197
        char    _pad_011400[0x20000 - 0x011400];
198
 
199
        /* PCI Device Configuration Spaces 0x020000-0x027FFF */
200
        union {                         /* make all access sizes available. */
201
                u8      c[0x1000 / 1];
202
                u16     s[0x1000 / 2];
203
                u32     l[0x1000 / 4];
204
                u64     d[0x1000 / 8];
205
                union {
206
                        u8      c[0x100 / 1];
207
                        u16     s[0x100 / 2];
208
                        u32     l[0x100 / 4];
209
                        u64     d[0x100 / 8];
210
                } f[8];
211
        } b_type0_cfg_dev[8];                                   /* 0x020000 */
212
 
213
    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
214
        union {                         /* make all access sizes available. */
215
                u8      c[0x1000 / 1];
216
                u16     s[0x1000 / 2];
217
                u32     l[0x1000 / 4];
218
                u64     d[0x1000 / 8];
219
        } b_type1_cfg;                                  /* 0x028000-0x029000 */
220
 
221
        char    _pad_029000[0x007000];                  /* 0x029000-0x030000 */
222
 
223
        /* PCI Interrupt Acknowledge Cycle 0x030000 */
224
        union {
225
                u8      c[8 / 1];
226
                u16     s[8 / 2];
227
                u32     l[8 / 4];
228
                u64     d[8 / 8];
229
        } b_pci_iack;                                           /* 0x030000 */
230
 
231
        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
232
 
233
        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
234
        bridge_ate_t    b_ext_ate_ram[0x10000];
235
 
236
        /* Reserved 0x100000-0x1FFFFF */
237
        char    _pad_100000[0x200000-0x100000];
238
 
239
        /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
240
        union {                         /* make all access sizes available. */
241
                u8      c[0x100000 / 1];
242
                u16     s[0x100000 / 2];
243
                u32     l[0x100000 / 4];
244
                u64     d[0x100000 / 8];
245
        } b_devio_raw[10];                              /* 0x200000 */
246
 
247
        /* b_devio macro is a bit strange; it reflects the
248
         * fact that the Bridge ASIC provides 2M for the
249
         * first two DevIO windows and 1M for the other six.
250
         */
251
#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
252
 
253
        /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
254
        union {         /* make all access sizes available. */
255
                u8      c[0x400000 / 1];        /* read-only */
256
                u16     s[0x400000 / 2];        /* read-write */
257
                u32     l[0x400000 / 4];        /* read-only */
258
                u64     d[0x400000 / 8];        /* read-only */
259
        } b_external_flash;                     /* 0xC00000 */
260
} bridge_t;
261
 
262
/*
263
 * Field formats for Error Command Word and Auxillary Error Command Word
264
 * of bridge.
265
 */
266
typedef struct bridge_err_cmdword_s {
267
        union {
268
                u32             cmd_word;
269
                struct {
270
                        u32     didn:4,         /* Destination ID */
271
                                sidn:4,         /* Source ID      */
272
                                pactyp:4,       /* Packet type    */
273
                                tnum:5,         /* Trans Number   */
274
                                coh:1,          /* Coh Transacti  */
275
                                ds:2,           /* Data size      */
276
                                gbr:1,          /* GBR enable     */
277
                                vbpm:1,         /* VBPM message   */
278
                                error:1,        /* Error occurred  */
279
                                barr:1,         /* Barrier op     */
280
                                rsvd:8;
281
                } berr_st;
282
        } berr_un;
283
} bridge_err_cmdword_t;
284
 
285
#define berr_field      berr_un.berr_st
286
#endif /* !__ASSEMBLY__ */
287
 
288
/*
289
 * The values of these macros can and should be crosschecked
290
 * regularly against the offsets of the like-named fields
291
 * within the "bridge_t" structure above.
292
 */
293
 
294
/* Byte offset macros for Bridge internal registers */
295
 
296
#define BRIDGE_WID_ID           WIDGET_ID
297
#define BRIDGE_WID_STAT         WIDGET_STATUS
298
#define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
299
#define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
300
#define BRIDGE_WID_CONTROL      WIDGET_CONTROL
301
#define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
302
#define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
303
#define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
304
#define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
305
#define BRIDGE_WID_LLP          WIDGET_LLP_CFG
306
#define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
307
 
308
#define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
309
#define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
310
#define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
311
#define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
312
 
313
#define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
314
 
315
#define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
316
 
317
#define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
318
 
319
#define BRIDGE_NIC              0x0000B4        /* Number In A Can */
320
 
321
#define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
322
#define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
323
#define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
324
#define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
325
#define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
326
 
327
#define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
328
#define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
329
#define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
330
#define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
331
#define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
332
#define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
333
 
334
#define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
335
#define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
336
#define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
337
 
338
#define BRIDGE_DEVICE0          0x000204        /* Device 0 */
339
#define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
340
#define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
341
 
342
#define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
343
#define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
344
#define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
345
 
346
#define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
347
#define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
348
 
349
#define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
350
#define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
351
 
352
/* Byte offset macros for Bridge I/O space */
353
 
354
#define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
355
 
356
#define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
357
#define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
358
#define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
359
#define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
360
                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
361
#define BRIDGE_TYPE0_CFG_DEVF(s,f)      (BRIDGE_TYPE0_CFG_DEV0+\
362
                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
363
                                         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
364
 
365
#define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
366
 
367
#define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
368
#define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
369
 
370
/* Byte offset macros for Bridge device IO spaces */
371
 
372
#define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
373
#define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
374
#define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
375
#define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
376
#define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
377
 
378
#define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
379
#define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
380
 
381
#define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
382
 
383
#define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
384
 
385
/* ========================================================================
386
 *    Bridge register bit field definitions
387
 */
388
 
389
/* Widget part number of bridge */
390
#define BRIDGE_WIDGET_PART_NUM          0xc002
391
 
392
/* Manufacturer of bridge */
393
#define BRIDGE_WIDGET_MFGR_NUM          0x036
394
 
395
/* Revision numbers for known Bridge revisions */
396
#define BRIDGE_REV_A                    0x1
397
#define BRIDGE_REV_B                    0x2
398
#define BRIDGE_REV_C                    0x3
399
#define BRIDGE_REV_D                    0x4
400
 
401
/* Bridge widget status register bits definition */
402
 
403
#define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
404
#define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
405
#define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
406
#define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
407
#define BRIDGE_STAT_PENDING             (0x1F << 0)
408
 
409
/* Bridge widget control register bits definition */
410
#define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)
411
#define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
412
#define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
413
#define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
414
#define BRIDGE_CTRL_RST(n)              ((n) << 24)
415
#define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
416
#define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
417
#define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
418
#define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
419
#define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
420
#define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
421
#define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
422
#define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
423
#define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
424
#define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
425
#define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
426
#define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
427
#define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
428
#define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
429
#define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
430
#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
431
#define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
432
#define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
433
#define BRIDGE_CTRL_SYS_END             (0x1 << 9)
434
#define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
435
#define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
436
#define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
437
#define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
438
 
439
/* Bridge Response buffer Error Upper Register bit fields definition */
440
#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
441
#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
442
#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
443
#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
444
#define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
445
 
446
#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
447
                        (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
448
                                BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
449
 
450
#define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
451
                        (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
452
                                 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
453
 
454
/* Bridge direct mapping register bits definition */
455
#define BRIDGE_DIRMAP_W_ID_SHFT         20
456
#define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
457
#define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
458
#define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
459
#define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
460
#define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
461
 
462
/* Bridge Arbitration register bits definition */
463
#define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
464
#define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
465
#define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
466
#define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
467
#define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
468
#define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
469
#define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
470
#define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
471
#define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
472
#define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
473
#define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
474
 
475
/* Bridge Bus time-out register bits definition */
476
#define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
477
#define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
478
#define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
479
#define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
480
#define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
481
 
482
/* Bridge interrupt status register bits definition */
483
#define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)
484
#define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)
485
#define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
486
#define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
487
#define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
488
#define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
489
#define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
490
#define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
491
#define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
492
#define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
493
#define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
494
#define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
495
#define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
496
#define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
497
#define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
498
#define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
499
#define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
500
#define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
501
#define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
502
#define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
503
#define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
504
#define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
505
#define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
506
#define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
507
#define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
508
#define BRIDGE_ISR_INT_MSK              (0xff << 0)
509
#define BRIDGE_ISR_INT(x)               (0x1 << (x))
510
 
511
#define BRIDGE_ISR_LINK_ERROR           \
512
                (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
513
                 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
514
                 BRIDGE_ISR_LLP_TCTY)
515
 
516
#define BRIDGE_ISR_PCIBUS_PIOERR        \
517
                (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
518
 
519
#define BRIDGE_ISR_PCIBUS_ERROR         \
520
                (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
521
                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
522
                 BRIDGE_ISR_PCI_PARITY)
523
 
524
#define BRIDGE_ISR_XTALK_ERROR          \
525
                (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
526
                 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
527
                 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
528
                 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
529
                 BRIDGE_ISR_UNEXP_RESP)
530
 
531
#define BRIDGE_ISR_ERRORS               \
532
                (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
533
                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
534
                 BRIDGE_ISR_PMU_ESIZE_FAULT)
535
 
536
/*
537
 * List of Errors which are fatal and kill the sytem
538
 */
539
#define BRIDGE_ISR_ERROR_FATAL          \
540
                ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
541
                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
542
 
543
#define BRIDGE_ISR_ERROR_DUMP           \
544
                (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
545
                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
546
 
547
/* Bridge interrupt enable register bits definition */
548
#define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
549
#define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
550
#define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
551
#define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
552
#define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
553
#define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
554
#define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
555
#define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
556
#define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
557
#define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
558
#define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
559
#define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
560
#define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
561
#define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
562
#define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
563
#define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
564
#define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
565
#define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
566
#define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
567
#define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
568
#define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
569
#define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
570
#define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
571
#define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
572
#define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
573
#define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
574
 
575
/* Bridge interrupt reset register bits definition */
576
#define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
577
#define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
578
#define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
579
#define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
580
#define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
581
#define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
582
#define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
583
#define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
584
#define BRIDGE_IRR_ALL_CLR              0x7f
585
 
586
#define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
587
                                         BRIDGE_ISR_XREQ_FIFO_OFLOW)
588
#define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
589
                                         BRIDGE_ISR_RESP_XTLK_ERR | \
590
                                         BRIDGE_ISR_XREAD_REQ_TIMEOUT)
591
#define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
592
                                         BRIDGE_ISR_BAD_XREQ_PKT | \
593
                                         BRIDGE_ISR_REQ_XTLK_ERR | \
594
                                         BRIDGE_ISR_INVLD_ADDR)
595
#define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
596
                                         BRIDGE_ISR_LLP_REC_CBERR | \
597
                                         BRIDGE_ISR_LLP_RCTY | \
598
                                         BRIDGE_ISR_LLP_TX_RETRY | \
599
                                         BRIDGE_ISR_LLP_TCTY)
600
#define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
601
                                         BRIDGE_ISR_PMU_ESIZE_FAULT)
602
#define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
603
                                         BRIDGE_ISR_PCI_PARITY | \
604
                                         BRIDGE_ISR_PCI_SERR | \
605
                                         BRIDGE_ISR_PCI_PERR | \
606
                                         BRIDGE_ISR_PCI_MST_TIMEOUT | \
607
                                         BRIDGE_ISR_PCI_RETRY_CNT)
608
 
609
#define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
610
                                         BRIDGE_ISR_GIO_MST_TIMEOUT)
611
 
612
/* Bridge INT_DEV register bits definition */
613
#define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
614
#define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
615
#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
616
 
617
/* Bridge interrupt(x) register bits definition */
618
#define BRIDGE_INT_ADDR_HOST            0x0003FF00
619
#define BRIDGE_INT_ADDR_FLD             0x000000FF
620
 
621
#define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
622
#define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
623
#define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
624
 
625
#define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
626
 
627
/*
628
 * The NASID should be shifted by this amount and stored into the
629
 * interrupt(x) register.
630
 */
631
#define BRIDGE_INT_ADDR_NASID_SHFT      8
632
 
633
/*
634
 * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
635
 * memory.
636
 */
637
#define BRIDGE_INT_ADDR_DEST_IO         (1 << 17)
638
#define BRIDGE_INT_ADDR_DEST_MEM        0
639
#define BRIDGE_INT_ADDR_MASK            (1 << 17)
640
 
641
/* Bridge device(x) register bits definition */
642
#define BRIDGE_DEV_ERR_LOCK_EN          0x10000000
643
#define BRIDGE_DEV_PAGE_CHK_DIS         0x08000000
644
#define BRIDGE_DEV_FORCE_PCI_PAR        0x04000000
645
#define BRIDGE_DEV_VIRTUAL_EN           0x02000000
646
#define BRIDGE_DEV_PMU_WRGA_EN          0x01000000
647
#define BRIDGE_DEV_DIR_WRGA_EN          0x00800000
648
#define BRIDGE_DEV_DEV_SIZE             0x00400000
649
#define BRIDGE_DEV_RT                   0x00200000
650
#define BRIDGE_DEV_SWAP_PMU             0x00100000
651
#define BRIDGE_DEV_SWAP_DIR             0x00080000
652
#define BRIDGE_DEV_PREF                 0x00040000
653
#define BRIDGE_DEV_PRECISE              0x00020000
654
#define BRIDGE_DEV_COH                  0x00010000
655
#define BRIDGE_DEV_BARRIER              0x00008000
656
#define BRIDGE_DEV_GBR                  0x00004000
657
#define BRIDGE_DEV_DEV_SWAP             0x00002000
658
#define BRIDGE_DEV_DEV_IO_MEM           0x00001000
659
#define BRIDGE_DEV_OFF_MASK             0x00000fff
660
#define BRIDGE_DEV_OFF_ADDR_SHFT        20
661
 
662
#define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
663
                                         BRIDGE_DEV_SWAP_PMU)
664
#define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
665
                                         BRIDGE_DEV_SWAP_DIR            | \
666
                                         BRIDGE_DEV_PREF                | \
667
                                         BRIDGE_DEV_PRECISE             | \
668
                                         BRIDGE_DEV_COH                 | \
669
                                         BRIDGE_DEV_BARRIER)
670
#define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
671
                                         BRIDGE_DEV_SWAP_DIR            | \
672
                                         BRIDGE_DEV_COH                 | \
673
                                         BRIDGE_DEV_BARRIER)
674
 
675
/* Bridge Error Upper register bit field definition */
676
#define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
677
#define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
678
#define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
679
#define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
680
#define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
681
#define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
682
 
683
/* Bridge interrupt mode register bits definition */
684
#define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
685
 
686
/* this should be written to the xbow's link_control(x) register */
687
#define BRIDGE_CREDIT   3
688
 
689
/* RRB assignment register */
690
#define BRIDGE_RRB_EN   0x8     /* after shifting down */
691
#define BRIDGE_RRB_DEV  0x7     /* after shifting down */
692
#define BRIDGE_RRB_VDEV 0x4     /* after shifting down */
693
#define BRIDGE_RRB_PDEV 0x3     /* after shifting down */
694
 
695
/* RRB status register */
696
#define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
697
#define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
698
 
699
/* RRB clear register */
700
#define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
701
 
702
/* xbox system controller declarations */
703
#define XBOX_BRIDGE_WID         8
704
#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
705
#define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
706
#define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
707
 
708
/* ========================================================================
709
 */
710
/*
711
 * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
712
 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
713
 */
714
/* XTALK addresses that map into Bridge Bus addr space */
715
#define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
716
#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
717
#define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
718
#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
719
#define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
720
#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
721
 
722
/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
723
#define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
724
#define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
725
#define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
726
#define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
727
 
728
/* XTALK addresses that map into PCI addresses */
729
#define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
730
#define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
731
#define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
732
#define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
733
#define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
734
#define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
735
 
736
/*
737
 * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
738
 */
739
/* Bridge Bus DMA addresses */
740
#define BRIDGE_LOCAL_BASE               0
741
#define BRIDGE_DMA_MAPPED_BASE          0x40000000
742
#define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
743
#define BRIDGE_DMA_DIRECT_BASE          0x80000000
744
#define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
745
 
746
#define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
747
 
748
/* PCI addresses of regions decoded by Bridge for DMA */
749
#define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
750
#define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
751
 
752
#define IS_PCI32_LOCAL(x)       ((ulong_t)(x) < PCI32_MAPPED_BASE)
753
#define IS_PCI32_MAPPED(x)      ((ulong_t)(x) < PCI32_DIRECT_BASE && \
754
                                        (ulong_t)(x) >= PCI32_MAPPED_BASE)
755
#define IS_PCI32_DIRECT(x)      ((ulong_t)(x) >= PCI32_MAPPED_BASE)
756
#define IS_PCI64(x)             ((ulong_t)(x) >= PCI64_BASE)
757
 
758
/*
759
 * The GIO address space.
760
 */
761
/* Xtalk to GIO PIO */
762
#define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
763
#define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
764
 
765
#define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
766
 
767
/* GIO addresses of regions decoded by Bridge for DMA */
768
#define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
769
#define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
770
 
771
#define IS_GIO_LOCAL(x)         ((ulong_t)(x) < GIO_MAPPED_BASE)
772
#define IS_GIO_MAPPED(x)        ((ulong_t)(x) < GIO_DIRECT_BASE && \
773
                                        (ulong_t)(x) >= GIO_MAPPED_BASE)
774
#define IS_GIO_DIRECT(x)        ((ulong_t)(x) >= GIO_MAPPED_BASE)
775
 
776
/* PCI to xtalk mapping */
777
 
778
/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
779
 * which xtalk address is accessed
780
 */
781
#define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
782
#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
783
        ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
784
                ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
785
 
786
/* 64-bit address attribute masks */
787
#define PCI64_ATTR_TARG_MASK    0xf000000000000000
788
#define PCI64_ATTR_TARG_SHFT    60
789
#define PCI64_ATTR_PREF         0x0800000000000000
790
#define PCI64_ATTR_PREC         0x0400000000000000
791
#define PCI64_ATTR_VIRTUAL      0x0200000000000000
792
#define PCI64_ATTR_BAR          0x0100000000000000
793
#define PCI64_ATTR_RMF_MASK     0x00ff000000000000
794
#define PCI64_ATTR_RMF_SHFT     48
795
 
796
#ifndef __ASSEMBLY__
797
/* Address translation entry for mapped pci32 accesses */
798
typedef union ate_u {
799
        u64     ent;
800
        struct ate_s {
801
                u64     rmf:16;
802
                u64     addr:36;
803
                u64     targ:4;
804
                u64     reserved:3;
805
                u64     barrier:1;
806
                u64     prefetch:1;
807
                u64     precise:1;
808
                u64     coherent:1;
809
                u64     valid:1;
810
        } field;
811
} ate_t;
812
#endif /* !__ASSEMBLY__ */
813
 
814
#define ATE_V           0x01
815
#define ATE_CO          0x02
816
#define ATE_PREC        0x04
817
#define ATE_PREF        0x08
818
#define ATE_BAR         0x10
819
 
820
#define ATE_PFNSHIFT            12
821
#define ATE_TIDSHIFT            8
822
#define ATE_RMFSHIFT            48
823
 
824
#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
825
                                ((xid)<<ATE_TIDSHIFT) | \
826
                                (attr)
827
 
828
#define BRIDGE_INTERNAL_ATES    128
829
 
830
/*
831
 * Linux pci bus mappings to sn physical id's
832
 */
833
extern unsigned char bus_to_wid[];      /* widget id for linux pci bus */
834
extern unsigned char bus_to_nid[];      /* nasid for linux pci bus */
835
extern unsigned char num_bridges;       /* number of bridges in the system */
836
 
837
#endif /* _ASM_PCI_BRIDGE_H */

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