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1275 |
phoenix |
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Inline assembly cache operations.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_R4KCACHE_H
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#define __ASM_R4KCACHE_H
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Invalidate_I, addr);
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_D, addr);
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_SD, addr);
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}
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static inline void flush_icache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_I, addr);
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}
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static inline void flush_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_D, addr);
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}
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static inline void invalidate_scache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_SD, addr);
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}
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static inline void flush_scache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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:
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: "i" (Hit_Invalidate_I), "r" (addr));
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}
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/*
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* R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
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* cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penaltiy isn't overly hard.
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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:
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: "i" (Hit_Writeback_Inv_D), "r" (addr));
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}
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/*
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* This one is RM7000-specific
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*/
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static inline void invalidate_tcache_page(unsigned long addr)
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{
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cache_op(Page_Invalidate_T, addr);
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}
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
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" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
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" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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: \
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: "r" (base), \
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"i" (op));
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static inline void blast_dcache16(void)
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{
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unsigned long start = KSEG0;
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unsigned long end = start + current_cpu_data.dcache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_dcache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_dcache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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| 180 |
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static inline void blast_icache16(void)
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{
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unsigned long start = KSEG0;
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| 183 |
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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| 185 |
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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| 187 |
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unsigned long ws, addr;
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| 188 |
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| 189 |
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for (ws = 0; ws < ws_end; ws += ws_inc)
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| 190 |
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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| 192 |
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}
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| 193 |
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| 194 |
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static inline void blast_icache16_page(unsigned long page)
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| 195 |
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{
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| 196 |
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unsigned long start = page;
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| 197 |
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unsigned long end = start + PAGE_SIZE;
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| 198 |
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| 199 |
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do {
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| 200 |
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cache16_unroll32(start,Hit_Invalidate_I);
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| 201 |
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start += 0x200;
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| 202 |
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} while (start < end);
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| 203 |
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}
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| 204 |
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| 205 |
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static inline void blast_icache16_page_indexed(unsigned long page)
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| 206 |
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{
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| 207 |
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unsigned long start = page;
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| 208 |
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unsigned long end = start + PAGE_SIZE;
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| 209 |
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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| 210 |
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unsigned long ws_end = current_cpu_data.icache.ways <<
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| 211 |
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current_cpu_data.icache.waybit;
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| 212 |
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unsigned long ws, addr;
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| 213 |
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| 214 |
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for (ws = 0; ws < ws_end; ws += ws_inc)
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| 215 |
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for (addr = start; addr < end; addr += 0x200)
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| 216 |
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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| 217 |
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}
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| 218 |
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| 219 |
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static inline void blast_scache16(void)
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| 220 |
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{
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| 221 |
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unsigned long start = KSEG0;
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| 222 |
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unsigned long end = start + current_cpu_data.scache.waysize;
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| 223 |
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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| 224 |
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unsigned long ws_end = current_cpu_data.scache.ways <<
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| 225 |
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current_cpu_data.scache.waybit;
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| 226 |
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unsigned long ws, addr;
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| 227 |
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| 228 |
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for (ws = 0; ws < ws_end; ws += ws_inc)
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| 229 |
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for (addr = start; addr < end; addr += 0x200)
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| 230 |
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
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| 231 |
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}
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| 232 |
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| 233 |
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static inline void blast_scache16_page(unsigned long page)
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| 234 |
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{
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| 235 |
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unsigned long start = page;
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| 236 |
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unsigned long end = page + PAGE_SIZE;
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| 237 |
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| 238 |
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do {
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| 239 |
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cache16_unroll32(start,Hit_Writeback_Inv_SD);
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| 240 |
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start += 0x200;
|
| 241 |
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} while (start < end);
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| 242 |
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}
|
| 243 |
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| 244 |
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static inline void blast_scache16_page_indexed(unsigned long page)
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| 245 |
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{
|
| 246 |
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unsigned long start = page;
|
| 247 |
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unsigned long end = start + PAGE_SIZE;
|
| 248 |
|
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 249 |
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unsigned long ws_end = current_cpu_data.scache.ways <<
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| 250 |
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current_cpu_data.scache.waybit;
|
| 251 |
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unsigned long ws, addr;
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| 252 |
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| 253 |
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for (ws = 0; ws < ws_end; ws += ws_inc)
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| 254 |
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for (addr = start; addr < end; addr += 0x200)
|
| 255 |
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 256 |
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}
|
| 257 |
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| 258 |
|
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#define cache32_unroll32(base,op) \
|
| 259 |
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__asm__ __volatile__( \
|
| 260 |
|
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" .set noreorder \n" \
|
| 261 |
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" .set mips3 \n" \
|
| 262 |
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" cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
|
| 263 |
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" cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \
|
| 264 |
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" cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \
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| 265 |
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" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \
|
| 266 |
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" cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \
|
| 267 |
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" cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \
|
| 268 |
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" cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \
|
| 269 |
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" cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \
|
| 270 |
|
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" cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \
|
| 271 |
|
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" cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \
|
| 272 |
|
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" cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \
|
| 273 |
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" cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \
|
| 274 |
|
|
" cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \
|
| 275 |
|
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" cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
|
| 276 |
|
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" cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
|
| 277 |
|
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" cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
|
| 278 |
|
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" .set mips0 \n" \
|
| 279 |
|
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" .set reorder \n" \
|
| 280 |
|
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: \
|
| 281 |
|
|
: "r" (base), \
|
| 282 |
|
|
"i" (op));
|
| 283 |
|
|
|
| 284 |
|
|
static inline void blast_dcache32(void)
|
| 285 |
|
|
{
|
| 286 |
|
|
unsigned long start = KSEG0;
|
| 287 |
|
|
unsigned long end = start + current_cpu_data.dcache.waysize;
|
| 288 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
| 289 |
|
|
unsigned long ws_end = current_cpu_data.dcache.ways <<
|
| 290 |
|
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current_cpu_data.dcache.waybit;
|
| 291 |
|
|
unsigned long ws, addr;
|
| 292 |
|
|
|
| 293 |
|
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for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 294 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 295 |
|
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
| 296 |
|
|
}
|
| 297 |
|
|
|
| 298 |
|
|
static inline void blast_dcache32_page(unsigned long page)
|
| 299 |
|
|
{
|
| 300 |
|
|
unsigned long start = page;
|
| 301 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 302 |
|
|
|
| 303 |
|
|
do {
|
| 304 |
|
|
cache32_unroll32(start,Hit_Writeback_Inv_D);
|
| 305 |
|
|
start += 0x400;
|
| 306 |
|
|
} while (start < end);
|
| 307 |
|
|
}
|
| 308 |
|
|
|
| 309 |
|
|
static inline void blast_dcache32_page_indexed(unsigned long page)
|
| 310 |
|
|
{
|
| 311 |
|
|
unsigned long start = page;
|
| 312 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 313 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
| 314 |
|
|
unsigned long ws_end = current_cpu_data.dcache.ways <<
|
| 315 |
|
|
current_cpu_data.dcache.waybit;
|
| 316 |
|
|
unsigned long ws, addr;
|
| 317 |
|
|
|
| 318 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 319 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 320 |
|
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
| 321 |
|
|
}
|
| 322 |
|
|
|
| 323 |
|
|
static inline void blast_icache32(void)
|
| 324 |
|
|
{
|
| 325 |
|
|
unsigned long start = KSEG0;
|
| 326 |
|
|
unsigned long end = start + current_cpu_data.icache.waysize;
|
| 327 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
| 328 |
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
| 329 |
|
|
current_cpu_data.icache.waybit;
|
| 330 |
|
|
unsigned long ws, addr;
|
| 331 |
|
|
|
| 332 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 333 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 334 |
|
|
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
| 335 |
|
|
}
|
| 336 |
|
|
|
| 337 |
|
|
static inline void blast_icache32_page(unsigned long page)
|
| 338 |
|
|
{
|
| 339 |
|
|
unsigned long start = page;
|
| 340 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 341 |
|
|
|
| 342 |
|
|
do {
|
| 343 |
|
|
cache32_unroll32(start,Hit_Invalidate_I);
|
| 344 |
|
|
start += 0x400;
|
| 345 |
|
|
} while (start < end);
|
| 346 |
|
|
}
|
| 347 |
|
|
|
| 348 |
|
|
static inline void blast_icache32_page_indexed(unsigned long page)
|
| 349 |
|
|
{
|
| 350 |
|
|
unsigned long start = page;
|
| 351 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 352 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
| 353 |
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
| 354 |
|
|
current_cpu_data.icache.waybit;
|
| 355 |
|
|
unsigned long ws, addr;
|
| 356 |
|
|
|
| 357 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 358 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 359 |
|
|
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
| 360 |
|
|
}
|
| 361 |
|
|
|
| 362 |
|
|
static inline void blast_scache32(void)
|
| 363 |
|
|
{
|
| 364 |
|
|
unsigned long start = KSEG0;
|
| 365 |
|
|
unsigned long end = start + current_cpu_data.scache.waysize;
|
| 366 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 367 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 368 |
|
|
current_cpu_data.scache.waybit;
|
| 369 |
|
|
unsigned long ws, addr;
|
| 370 |
|
|
|
| 371 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 372 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 373 |
|
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 374 |
|
|
}
|
| 375 |
|
|
|
| 376 |
|
|
static inline void blast_scache32_page(unsigned long page)
|
| 377 |
|
|
{
|
| 378 |
|
|
unsigned long start = page;
|
| 379 |
|
|
unsigned long end = page + PAGE_SIZE;
|
| 380 |
|
|
|
| 381 |
|
|
do {
|
| 382 |
|
|
cache32_unroll32(start,Hit_Writeback_Inv_SD);
|
| 383 |
|
|
start += 0x400;
|
| 384 |
|
|
} while (start < end);
|
| 385 |
|
|
}
|
| 386 |
|
|
|
| 387 |
|
|
static inline void blast_scache32_page_indexed(unsigned long page)
|
| 388 |
|
|
{
|
| 389 |
|
|
unsigned long start = page;
|
| 390 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 391 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 392 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 393 |
|
|
current_cpu_data.scache.waybit;
|
| 394 |
|
|
unsigned long ws, addr;
|
| 395 |
|
|
|
| 396 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 397 |
|
|
for (addr = start; addr < end; addr += 0x400)
|
| 398 |
|
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 399 |
|
|
}
|
| 400 |
|
|
|
| 401 |
|
|
#define cache64_unroll32(base,op) \
|
| 402 |
|
|
__asm__ __volatile__( \
|
| 403 |
|
|
" .set noreorder \n" \
|
| 404 |
|
|
" .set mips3 \n" \
|
| 405 |
|
|
" cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
|
| 406 |
|
|
" cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \
|
| 407 |
|
|
" cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \
|
| 408 |
|
|
" cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \
|
| 409 |
|
|
" cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \
|
| 410 |
|
|
" cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \
|
| 411 |
|
|
" cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \
|
| 412 |
|
|
" cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \
|
| 413 |
|
|
" cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \
|
| 414 |
|
|
" cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \
|
| 415 |
|
|
" cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \
|
| 416 |
|
|
" cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \
|
| 417 |
|
|
" cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \
|
| 418 |
|
|
" cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
|
| 419 |
|
|
" cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
|
| 420 |
|
|
" cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
|
| 421 |
|
|
" .set mips0 \n" \
|
| 422 |
|
|
" .set reorder \n" \
|
| 423 |
|
|
: \
|
| 424 |
|
|
: "r" (base), \
|
| 425 |
|
|
"i" (op));
|
| 426 |
|
|
|
| 427 |
|
|
static inline void blast_icache64(void)
|
| 428 |
|
|
{
|
| 429 |
|
|
unsigned long start = KSEG0;
|
| 430 |
|
|
unsigned long end = start + current_cpu_data.icache.waysize;
|
| 431 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
| 432 |
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
| 433 |
|
|
current_cpu_data.icache.waybit;
|
| 434 |
|
|
unsigned long ws, addr;
|
| 435 |
|
|
|
| 436 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 437 |
|
|
for (addr = start; addr < end; addr += 0x800)
|
| 438 |
|
|
cache64_unroll32(addr|ws,Index_Invalidate_I);
|
| 439 |
|
|
}
|
| 440 |
|
|
|
| 441 |
|
|
static inline void blast_icache64_page(unsigned long page)
|
| 442 |
|
|
{
|
| 443 |
|
|
unsigned long start = page;
|
| 444 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 445 |
|
|
|
| 446 |
|
|
do {
|
| 447 |
|
|
cache64_unroll32(start,Hit_Invalidate_I);
|
| 448 |
|
|
start += 0x800;
|
| 449 |
|
|
} while (start < end);
|
| 450 |
|
|
}
|
| 451 |
|
|
|
| 452 |
|
|
static inline void blast_icache64_page_indexed(unsigned long page)
|
| 453 |
|
|
{
|
| 454 |
|
|
unsigned long start = page;
|
| 455 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 456 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
| 457 |
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
| 458 |
|
|
current_cpu_data.icache.waybit;
|
| 459 |
|
|
unsigned long ws, addr;
|
| 460 |
|
|
|
| 461 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 462 |
|
|
for (addr = start; addr < end; addr += 0x800)
|
| 463 |
|
|
cache64_unroll32(addr|ws,Index_Invalidate_I);
|
| 464 |
|
|
}
|
| 465 |
|
|
|
| 466 |
|
|
static inline void blast_scache64(void)
|
| 467 |
|
|
{
|
| 468 |
|
|
unsigned long start = KSEG0;
|
| 469 |
|
|
unsigned long end = start + current_cpu_data.scache.waysize;
|
| 470 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 471 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 472 |
|
|
current_cpu_data.scache.waybit;
|
| 473 |
|
|
unsigned long ws, addr;
|
| 474 |
|
|
|
| 475 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 476 |
|
|
for (addr = start; addr < end; addr += 0x800)
|
| 477 |
|
|
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 478 |
|
|
}
|
| 479 |
|
|
|
| 480 |
|
|
static inline void blast_scache64_page(unsigned long page)
|
| 481 |
|
|
{
|
| 482 |
|
|
unsigned long start = page;
|
| 483 |
|
|
unsigned long end = page + PAGE_SIZE;
|
| 484 |
|
|
|
| 485 |
|
|
do {
|
| 486 |
|
|
cache64_unroll32(start,Hit_Writeback_Inv_SD);
|
| 487 |
|
|
start += 0x800;
|
| 488 |
|
|
} while (start < end);
|
| 489 |
|
|
}
|
| 490 |
|
|
|
| 491 |
|
|
static inline void blast_scache64_page_indexed(unsigned long page)
|
| 492 |
|
|
{
|
| 493 |
|
|
unsigned long start = page;
|
| 494 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 495 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 496 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 497 |
|
|
current_cpu_data.scache.waybit;
|
| 498 |
|
|
unsigned long ws, addr;
|
| 499 |
|
|
|
| 500 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 501 |
|
|
for (addr = start; addr < end; addr += 0x800)
|
| 502 |
|
|
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 503 |
|
|
}
|
| 504 |
|
|
|
| 505 |
|
|
#define cache128_unroll32(base,op) \
|
| 506 |
|
|
__asm__ __volatile__( \
|
| 507 |
|
|
" .set noreorder \n" \
|
| 508 |
|
|
" .set mips3 \n" \
|
| 509 |
|
|
" cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
|
| 510 |
|
|
" cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \
|
| 511 |
|
|
" cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \
|
| 512 |
|
|
" cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \
|
| 513 |
|
|
" cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \
|
| 514 |
|
|
" cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \
|
| 515 |
|
|
" cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \
|
| 516 |
|
|
" cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \
|
| 517 |
|
|
" cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \
|
| 518 |
|
|
" cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \
|
| 519 |
|
|
" cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \
|
| 520 |
|
|
" cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \
|
| 521 |
|
|
" cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \
|
| 522 |
|
|
" cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
|
| 523 |
|
|
" cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
|
| 524 |
|
|
" cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
|
| 525 |
|
|
" .set mips0 \n" \
|
| 526 |
|
|
" .set reorder \n" \
|
| 527 |
|
|
: \
|
| 528 |
|
|
: "r" (base), \
|
| 529 |
|
|
"i" (op));
|
| 530 |
|
|
|
| 531 |
|
|
static inline void blast_scache128(void)
|
| 532 |
|
|
{
|
| 533 |
|
|
unsigned long start = KSEG0;
|
| 534 |
|
|
unsigned long end = start + current_cpu_data.scache.waysize;
|
| 535 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 536 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 537 |
|
|
current_cpu_data.scache.waybit;
|
| 538 |
|
|
unsigned long ws, addr;
|
| 539 |
|
|
|
| 540 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 541 |
|
|
for (addr = start; addr < end; addr += 0x1000)
|
| 542 |
|
|
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 543 |
|
|
}
|
| 544 |
|
|
|
| 545 |
|
|
static inline void blast_scache128_page(unsigned long page)
|
| 546 |
|
|
{
|
| 547 |
|
|
unsigned long start = page;
|
| 548 |
|
|
unsigned long end = page + PAGE_SIZE;
|
| 549 |
|
|
|
| 550 |
|
|
do {
|
| 551 |
|
|
cache128_unroll32(start,Hit_Writeback_Inv_SD);
|
| 552 |
|
|
start += 0x1000;
|
| 553 |
|
|
} while (start < end);
|
| 554 |
|
|
}
|
| 555 |
|
|
|
| 556 |
|
|
static inline void blast_scache128_page_indexed(unsigned long page)
|
| 557 |
|
|
{
|
| 558 |
|
|
unsigned long start = page;
|
| 559 |
|
|
unsigned long end = start + PAGE_SIZE;
|
| 560 |
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
| 561 |
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
| 562 |
|
|
current_cpu_data.scache.waybit;
|
| 563 |
|
|
unsigned long ws, addr;
|
| 564 |
|
|
|
| 565 |
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
| 566 |
|
|
for (addr = start; addr < end; addr += 0x1000)
|
| 567 |
|
|
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
| 568 |
|
|
}
|
| 569 |
|
|
|
| 570 |
|
|
#endif /* __ASM_R4KCACHE_H */
|
