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phoenix |
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_SN_INTR_PUBLIC_H
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#define __ASM_SN_INTR_PUBLIC_H
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/* REMEMBER: If you change these, the whole world needs to be recompiled.
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* It would also require changing the hubspl.s code and SN0/intr.c
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* Currently, the spl code has no support for multiple INTPEND1 masks.
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*/
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#define N_INTPEND0_MASKS 1
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#define N_INTPEND1_MASKS 1
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#define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1)
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#define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1)
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#ifndef __ASSEMBLY__
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#include <asm/sn/arch.h>
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struct intr_vecblk_s; /* defined in asm/sn/intr.h */
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/*
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* The following are necessary to create the illusion of a CEL
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* on the SN0 hub. We'll add more priority levels soon, but for
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* now, any interrupt in a particular band effectively does an spl.
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* These must be in the PDA since they're different for each processor.
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* Users of this structure must hold the vector_lock in the appropriate vector
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* block before modifying the mask arrays. There's only one vector block
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* for each Hub so a lock in the PDA wouldn't be adequate.
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*/
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typedef struct hub_intmasks_s {
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/*
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* The masks are stored with the lowest-priority (most inclusive)
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* in the lowest-numbered masks (i.e., 0, 1, 2...).
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*/
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/* INT_PEND0: */
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hubreg_t intpend0_masks[N_INTPEND0_MASKS];
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/* INT_PEND1: */
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hubreg_t intpend1_masks[N_INTPEND1_MASKS];
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/* INT_PEND0: */
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struct intr_vecblk_s *dispatch0;
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/* INT_PEND1: */
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struct intr_vecblk_s *dispatch1;
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} hub_intmasks_t;
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_SN_INTR_PUBLIC_H */
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