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#ifndef _ASM_PARISC_ATOMIC_H_
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/config.h>
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#include <asm/system.h>
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/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>. */
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* And probably incredibly slow on parisc. OTOH, we don't
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* have to write any serious assembly. prumpf
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*/
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#ifdef CONFIG_SMP
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#include <asm/spinlock_t.h>
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/* Use an array of spinlocks for our atomic_ts.
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** Hash function to index into a different SPINLOCK.
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** Since "a" is usually an address, ">>8" makes one spinlock per 64-bytes.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&__atomic_hash[(((unsigned long) a)>>8)&(ATOMIC_HASH_SIZE-1)])
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extern spinlock_t __atomic_hash[ATOMIC_HASH_SIZE];
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/* copied from <asm/spinlock.h> and modified.
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* No CONFIG_DEBUG_SPINLOCK support.
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*
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* XXX REVISIT these could be renamed and moved to spinlock_t.h as well
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*/
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#define SPIN_LOCK(x) do { while(__ldcw(&(x)->lock) == 0); } while(0)
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#define SPIN_UNLOCK(x) do { (x)->lock = 1; } while(0)
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#else /* CONFIG_SMP */
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#define ATOMIC_HASH_SIZE 1
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#define ATOMIC_HASH(a) (0)
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#define SPIN_LOCK(x) (void)(x)
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#define SPIN_UNLOCK(x) do { } while(0)
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#endif /* CONFIG_SMP */
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/* copied from <linux/spinlock.h> and modified */
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#define SPIN_LOCK_IRQSAVE(lock, flags) do { \
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local_irq_save(flags); SPIN_LOCK(lock); \
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} while (0)
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#define SPIN_UNLOCK_IRQRESTORE(lock, flags) do { \
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SPIN_UNLOCK(lock); local_irq_restore(flags); \
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} while (0)
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/* Note that we need not lock read accesses - aligned word writes/reads
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* are atomic, so a reader never sees unconsistent values.
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*
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* Cache-line alignment would conflict with, for example, linux/module.h
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*/
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typedef struct {
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volatile int counter;
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} atomic_t;
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/* This should get optimized out since it's never called.
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** Or get a link error if xchg is used "wrong".
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*/
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extern void __xchg_called_with_bad_pointer(void);
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/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __xchg8(char, char *);
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extern unsigned long __xchg32(int, int *);
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#ifdef __LP64__
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extern unsigned long __xchg64(unsigned long, unsigned long *);
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#endif
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/* optimizer better get rid of switch since size is a constant */
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static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
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int size)
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{
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switch(size) {
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#ifdef __LP64__
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case 8: return __xchg64(x,(unsigned long *) ptr);
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#endif
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case 4: return __xchg32((int) x, (int *) ptr);
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case 1: return __xchg8((char) x, (char *) ptr);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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/*
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** REVISIT - Abandoned use of LDCW in xchg() for now:
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** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
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** o and while we are at it, could 64-bit code use LDCD too?
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**
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** if (__builtin_constant_p(x) && (x == NULL))
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** if (((unsigned long)p & 0xf) == 0)
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** return __ldcw(p);
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*/
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define __HAVE_ARCH_CMPXCHG 1
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/* bug catcher for when unsupported size is used - won't link */
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extern void __cmpxchg_called_with_bad_pointer(void);
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/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
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extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
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/* don't worry...optimizer will get rid of most of this */
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch(size) {
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#ifdef __LP64__
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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/* It's possible to reduce all atomic operations to either
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* __atomic_add_return, __atomic_set and __atomic_ret (the latter
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* is there only for consistency). */
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static __inline__ int __atomic_add_return(int i, atomic_t *v)
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{
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int ret;
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unsigned long flags;
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SPIN_LOCK_IRQSAVE(ATOMIC_HASH(v), flags);
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ret = (v->counter += i);
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SPIN_UNLOCK_IRQRESTORE(ATOMIC_HASH(v), flags);
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return ret;
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}
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static __inline__ void __atomic_set(atomic_t *v, int i)
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{
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unsigned long flags;
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SPIN_LOCK_IRQSAVE(ATOMIC_HASH(v), flags);
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v->counter = i;
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SPIN_UNLOCK_IRQRESTORE(ATOMIC_HASH(v), flags);
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}
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static __inline__ int __atomic_read(atomic_t *v)
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{
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return v->counter;
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}
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/* exported interface */
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#define atomic_add(i,v) ((void)(__atomic_add_return( (i),(v))))
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#define atomic_sub(i,v) ((void)(__atomic_add_return(-(i),(v))))
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#define atomic_inc(v) ((void)(__atomic_add_return( 1,(v))))
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#define atomic_dec(v) ((void)(__atomic_add_return( -1,(v))))
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#define atomic_add_return(i,v) (__atomic_add_return( (i),(v)))
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#define atomic_sub_return(i,v) (__atomic_add_return(-(i),(v)))
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#define atomic_inc_return(v) (__atomic_add_return( 1,(v)))
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#define atomic_dec_return(v) (__atomic_add_return( -1,(v)))
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_set(v,i) (__atomic_set((v),i))
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#define atomic_read(v) (__atomic_read(v))
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#define ATOMIC_INIT(i) { (i) }
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#endif
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