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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-ppc/] [commproc.h] - Blame information for rev 1765

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1 1276 phoenix 
/*
2 
 * MPC8xx Communication Processor Module.
3 
 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 
 *
5 
 * This file contains structures and information for the communication
6 
 * processor channels.  Some CPM control and status is available
7 
 * throught the MPC8xx internal memory map.  See immap.h for details.
8 
 * This file only contains what I need for the moment, not the total
9 
 * CPM capabilities.  I (or someone else) will add definitions as they
10 
 * are needed.  -- Dan
11 
 *
12 
 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 
 * bytes of the DP RAM and relocates the I2C parameter area to the
14 
 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
15 
 * or other use.
16 
 */
17 
#ifndef __CPM_8XX__
18 
#define __CPM_8XX__
19 
 
20 
#include <linux/config.h>
21 
#include <asm/8xx_immap.h>
22 
 
23 
/* CPM Command register.
24 
*/
25 
#define CPM_CR_RST      ((ushort)0x8000)
26 
#define CPM_CR_OPCODE   ((ushort)0x0f00)
27 
#define CPM_CR_CHAN     ((ushort)0x00f0)
28 
#define CPM_CR_FLG      ((ushort)0x0001)
29 
 
30 
/* Some commands (there are more...later)
31 
*/
32 
#define CPM_CR_INIT_TRX         ((ushort)0x0000)
33 
#define CPM_CR_INIT_RX          ((ushort)0x0001)
34 
#define CPM_CR_INIT_TX          ((ushort)0x0002)
35 
#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
36 
#define CPM_CR_STOP_TX          ((ushort)0x0004)
37 
#define CPM_CR_RESTART_TX       ((ushort)0x0006)
38 
#define CPM_CR_SET_GADDR        ((ushort)0x0008)
39 
 
40 
/* Channel numbers.
41 
*/
42 
#define CPM_CR_CH_SCC1  ((ushort)0x0000)
43 
#define CPM_CR_CH_I2C   ((ushort)0x0001)        /* I2C and IDMA1 */
44 
#define CPM_CR_CH_SCC2  ((ushort)0x0004)
45 
#define CPM_CR_CH_SPI   ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
46 
#define CPM_CR_CH_SCC3  ((ushort)0x0008)
47 
#define CPM_CR_CH_SMC1  ((ushort)0x0009)        /* SMC1 / DSP1 */
48 
#define CPM_CR_CH_SCC4  ((ushort)0x000c)
49 
#define CPM_CR_CH_SMC2  ((ushort)0x000d)        /* SMC2 / DSP2 */
50 
 
51 
#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
52 
 
53 
/* The dual ported RAM is multi-functional.  Some areas can be (and are
54 
 * being) used for microcode.  There is an area that can only be used
55 
 * as data ram for buffer descriptors, which is all we use right now.
56 
 * Currently the first 512 and last 256 bytes are used for microcode.
57 
 */
58 
#define CPM_DATAONLY_BASE       ((uint)0x0800)
59 
#define CPM_DATAONLY_SIZE       ((uint)0x0700)
60 
#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
61 
 
62 
/* Export the base address of the communication processor registers
63 
 * and dual port ram.
64 
 */
65 
extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
66 
uint            m8xx_cpm_dpalloc(uint size);
67 
uint            m8xx_cpm_hostalloc(uint size);
68 
void            m8xx_cpm_setbrg(uint brg, uint rate);
69 
 
70 
/* Buffer descriptors used by many of the CPM protocols.
71 
*/
72 
typedef struct cpm_buf_desc {
73 
        ushort  cbd_sc;         /* Status and Control */
74 
        ushort  cbd_datlen;     /* Data length in buffer */
75 
        uint    cbd_bufaddr;    /* Buffer address in host memory */
76 
} cbd_t;
77 
 
78 
#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
79 
#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
80 
#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
81 
#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
82 
#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
83 
#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
84 
#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
85 
#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
86 
#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
87 
#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
88 
#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
89 
#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
90 
#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
91 
 
92 
/* Parameter RAM offsets.
93 
*/
94 
#define PROFF_SCC1      ((uint)0x0000)
95 
#define PROFF_IIC       ((uint)0x0080)
96 
#define PROFF_SCC2      ((uint)0x0100)
97 
#define PROFF_SCC3      ((uint)0x0200)
98 
#define PROFF_SMC1      ((uint)0x0280)
99 
#define PROFF_SCC4      ((uint)0x0300)
100 
#define PROFF_SMC2      ((uint)0x0380)
101 
 
102 
/* Define enough so I can at least use the serial port as a UART.
103 
 * The MBX uses SMC1 as the host serial port.
104 
 */
105 
typedef struct smc_uart {
106 
        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
107 
        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
108 
        u_char  smc_rfcr;       /* Rx function code */
109 
        u_char  smc_tfcr;       /* Tx function code */
110 
        ushort  smc_mrblr;      /* Max receive buffer length */
111 
        uint    smc_rstate;     /* Internal */
112 
        uint    smc_idp;        /* Internal */
113 
        ushort  smc_rbptr;      /* Internal */
114 
        ushort  smc_ibc;        /* Internal */
115 
        uint    smc_rxtmp;      /* Internal */
116 
        uint    smc_tstate;     /* Internal */
117 
        uint    smc_tdp;        /* Internal */
118 
        ushort  smc_tbptr;      /* Internal */
119 
        ushort  smc_tbc;        /* Internal */
120 
        uint    smc_txtmp;      /* Internal */
121 
        ushort  smc_maxidl;     /* Maximum idle characters */
122 
        ushort  smc_tmpidl;     /* Temporary idle counter */
123 
        ushort  smc_brklen;     /* Last received break length */
124 
        ushort  smc_brkec;      /* rcv'd break condition counter */
125 
        ushort  smc_brkcr;      /* xmt break count register */
126 
        ushort  smc_rmask;      /* Temporary bit mask */
127 
} smc_uart_t;
128 
 
129 
/* Function code bits.
130 
*/
131 
#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
132 
 
133 
/* SMC uart mode register.
134 
*/
135 
#define SMCMR_REN       ((ushort)0x0001)
136 
#define SMCMR_TEN       ((ushort)0x0002)
137 
#define SMCMR_DM        ((ushort)0x000c)
138 
#define SMCMR_SM_GCI    ((ushort)0x0000)
139 
#define SMCMR_SM_UART   ((ushort)0x0020)
140 
#define SMCMR_SM_TRANS  ((ushort)0x0030)
141 
#define SMCMR_SM_MASK   ((ushort)0x0030)
142 
#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
143 
#define SMCMR_REVD      SMCMR_PM_EVEN
144 
#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
145 
#define SMCMR_BS        SMCMR_PEN
146 
#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
147 
#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
148 
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
149 
 
150 
/* SMC2 as Centronics parallel printer.  It is half duplex, in that
151 
 * it can only receive or transmit.  The parameter ram values for
152 
 * each direction are either unique or properly overlap, so we can
153 
 * include them in one structure.
154 
 */
155 
typedef struct smc_centronics {
156 
        ushort  scent_rbase;
157 
        ushort  scent_tbase;
158 
        u_char  scent_cfcr;
159 
        u_char  scent_smask;
160 
        ushort  scent_mrblr;
161 
        uint    scent_rstate;
162 
        uint    scent_r_ptr;
163 
        ushort  scent_rbptr;
164 
        ushort  scent_r_cnt;
165 
        uint    scent_rtemp;
166 
        uint    scent_tstate;
167 
        uint    scent_t_ptr;
168 
        ushort  scent_tbptr;
169 
        ushort  scent_t_cnt;
170 
        uint    scent_ttemp;
171 
        ushort  scent_max_sl;
172 
        ushort  scent_sl_cnt;
173 
        ushort  scent_character1;
174 
        ushort  scent_character2;
175 
        ushort  scent_character3;
176 
        ushort  scent_character4;
177 
        ushort  scent_character5;
178 
        ushort  scent_character6;
179 
        ushort  scent_character7;
180 
        ushort  scent_character8;
181 
        ushort  scent_rccm;
182 
        ushort  scent_rccr;
183 
} smc_cent_t;
184 
 
185 
/* Centronics Status Mask Register.
186 
*/
187 
#define SMC_CENT_F      ((u_char)0x08)
188 
#define SMC_CENT_PE     ((u_char)0x04)
189 
#define SMC_CENT_S      ((u_char)0x02)
190 
 
191 
/* SMC Event and Mask register.
192 
*/
193 
#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
194 
#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
195 
#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
196 
#define SMCM_BSY        ((unsigned char)0x04)
197 
#define SMCM_TX         ((unsigned char)0x02)
198 
#define SMCM_RX         ((unsigned char)0x01)
199 
 
200 
/* Baud rate generators.
201 
*/
202 
#define CPM_BRG_RST             ((uint)0x00020000)
203 
#define CPM_BRG_EN              ((uint)0x00010000)
204 
#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
205 
#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
206 
#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
207 
#define CPM_BRG_ATB             ((uint)0x00002000)
208 
#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
209 
#define CPM_BRG_DIV16           ((uint)0x00000001)
210 
 
211 
/* SCCs.
212 
*/
213 
#define SCC_GSMRH_IRP           ((uint)0x00040000)
214 
#define SCC_GSMRH_GDE           ((uint)0x00010000)
215 
#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
216 
#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
217 
#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
218 
#define SCC_GSMRH_REVD          ((uint)0x00002000)
219 
#define SCC_GSMRH_TRX           ((uint)0x00001000)
220 
#define SCC_GSMRH_TTX           ((uint)0x00000800)
221 
#define SCC_GSMRH_CDP           ((uint)0x00000400)
222 
#define SCC_GSMRH_CTSP          ((uint)0x00000200)
223 
#define SCC_GSMRH_CDS           ((uint)0x00000100)
224 
#define SCC_GSMRH_CTSS          ((uint)0x00000080)
225 
#define SCC_GSMRH_TFL           ((uint)0x00000040)
226 
#define SCC_GSMRH_RFW           ((uint)0x00000020)
227 
#define SCC_GSMRH_TXSY          ((uint)0x00000010)
228 
#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
229 
#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
230 
#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
231 
#define SCC_GSMRH_RTSM          ((uint)0x00000002)
232 
#define SCC_GSMRH_RSYN          ((uint)0x00000001)
233 
 
234 
#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
235 
#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
236 
#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
237 
#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
238 
#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
239 
#define SCC_GSMRL_TCI           ((uint)0x10000000)
240 
#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
241 
#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
242 
#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
243 
#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
244 
#define SCC_GSMRL_RINV          ((uint)0x02000000)
245 
#define SCC_GSMRL_TINV          ((uint)0x01000000)
246 
#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
247 
#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
248 
#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
249 
#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
250 
#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
251 
#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
252 
#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
253 
#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
254 
#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
255 
#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
256 
#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
257 
#define SCC_GSMRL_TEND          ((uint)0x00040000)
258 
#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
259 
#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
260 
#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
261 
#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
262 
#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
263 
#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
264 
#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
265 
#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
266 
#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
267 
#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
268 
#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
269 
#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
270 
#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
271 
#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
272 
#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
273 
#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
274 
#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
275 
#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
276 
#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
277 
#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
278 
#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
279 
#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
280 
#define SCC_GSMRL_ENR           ((uint)0x00000020)
281 
#define SCC_GSMRL_ENT           ((uint)0x00000010)
282 
#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
283 
#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
284 
#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
285 
#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
286 
#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
287 
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
288 
#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
289 
#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
290 
#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
291 
#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
292 
 
293 
#define SCC_TODR_TOD            ((ushort)0x8000)
294 
 
295 
/* SCC Event and Mask register.
296 
*/
297 
#define SCCM_TXE        ((unsigned char)0x10)
298 
#define SCCM_BSY        ((unsigned char)0x04)
299 
#define SCCM_TX         ((unsigned char)0x02)
300 
#define SCCM_RX         ((unsigned char)0x01)
301 
 
302 
typedef struct scc_param {
303 
        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
304 
        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
305 
        u_char  scc_rfcr;       /* Rx function code */
306 
        u_char  scc_tfcr;       /* Tx function code */
307 
        ushort  scc_mrblr;      /* Max receive buffer length */
308 
        uint    scc_rstate;     /* Internal */
309 
        uint    scc_idp;        /* Internal */
310 
        ushort  scc_rbptr;      /* Internal */
311 
        ushort  scc_ibc;        /* Internal */
312 
        uint    scc_rxtmp;      /* Internal */
313 
        uint    scc_tstate;     /* Internal */
314 
        uint    scc_tdp;        /* Internal */
315 
        ushort  scc_tbptr;      /* Internal */
316 
        ushort  scc_tbc;        /* Internal */
317 
        uint    scc_txtmp;      /* Internal */
318 
        uint    scc_rcrc;       /* Internal */
319 
        uint    scc_tcrc;       /* Internal */
320 
} sccp_t;
321 
 
322 
/* Function code bits.
323 
*/
324 
#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
325 
 
326 
/* CPM Ethernet through SCCx.
327 
 */
328 
typedef struct scc_enet {
329 
        sccp_t  sen_genscc;
330 
        uint    sen_cpres;      /* Preset CRC */
331 
        uint    sen_cmask;      /* Constant mask for CRC */
332 
        uint    sen_crcec;      /* CRC Error counter */
333 
        uint    sen_alec;       /* alignment error counter */
334 
        uint    sen_disfc;      /* discard frame counter */
335 
        ushort  sen_pads;       /* Tx short frame pad character */
336 
        ushort  sen_retlim;     /* Retry limit threshold */
337 
        ushort  sen_retcnt;     /* Retry limit counter */
338 
        ushort  sen_maxflr;     /* maximum frame length register */
339 
        ushort  sen_minflr;     /* minimum frame length register */
340 
        ushort  sen_maxd1;      /* maximum DMA1 length */
341 
        ushort  sen_maxd2;      /* maximum DMA2 length */
342 
        ushort  sen_maxd;       /* Rx max DMA */
343 
        ushort  sen_dmacnt;     /* Rx DMA counter */
344 
        ushort  sen_maxb;       /* Max BD byte count */
345 
        ushort  sen_gaddr1;     /* Group address filter */
346 
        ushort  sen_gaddr2;
347 
        ushort  sen_gaddr3;
348 
        ushort  sen_gaddr4;
349 
        uint    sen_tbuf0data0; /* Save area 0 - current frame */
350 
        uint    sen_tbuf0data1; /* Save area 1 - current frame */
351 
        uint    sen_tbuf0rba;   /* Internal */
352 
        uint    sen_tbuf0crc;   /* Internal */
353 
        ushort  sen_tbuf0bcnt;  /* Internal */
354 
        ushort  sen_paddrh;     /* physical address (MSB) */
355 
        ushort  sen_paddrm;
356 
        ushort  sen_paddrl;     /* physical address (LSB) */
357 
        ushort  sen_pper;       /* persistence */
358 
        ushort  sen_rfbdptr;    /* Rx first BD pointer */
359 
        ushort  sen_tfbdptr;    /* Tx first BD pointer */
360 
        ushort  sen_tlbdptr;    /* Tx last BD pointer */
361 
        uint    sen_tbuf1data0; /* Save area 0 - current frame */
362 
        uint    sen_tbuf1data1; /* Save area 1 - current frame */
363 
        uint    sen_tbuf1rba;   /* Internal */
364 
        uint    sen_tbuf1crc;   /* Internal */
365 
        ushort  sen_tbuf1bcnt;  /* Internal */
366 
        ushort  sen_txlen;      /* Tx Frame length counter */
367 
        ushort  sen_iaddr1;     /* Individual address filter */
368 
        ushort  sen_iaddr2;
369 
        ushort  sen_iaddr3;
370 
        ushort  sen_iaddr4;
371 
        ushort  sen_boffcnt;    /* Backoff counter */
372 
 
373 
        /* NOTE: Some versions of the manual have the following items
374 
         * incorrectly documented.  Below is the proper order.
375 
         */
376 
        ushort  sen_taddrh;     /* temp address (MSB) */
377 
        ushort  sen_taddrm;
378 
        ushort  sen_taddrl;     /* temp address (LSB) */
379 
} scc_enet_t;
380 
 
381 
/***  MBX  ************************************************************/
382 
 
383 
#ifdef CONFIG_MBX
384 
/* Bits in parallel I/O port registers that have to be set/cleared
385 
 * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
386 
 * to the MBX860 board.  Any two of the four available clocks could be
387 
 * used, and the MPC860 cookbook manual has an example using different
388 
 * clock pins.
389 
 */
390 
#define PA_ENET_RXD     ((ushort)0x0001)
391 
#define PA_ENET_TXD     ((ushort)0x0002)
392 
#define PA_ENET_TCLK    ((ushort)0x0200)
393 
#define PA_ENET_RCLK    ((ushort)0x0800)
394 
#define PC_ENET_TENA    ((ushort)0x0001)
395 
#define PC_ENET_CLSN    ((ushort)0x0010)
396 
#define PC_ENET_RENA    ((ushort)0x0020)
397 
 
398 
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
399 
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
400 
 */
401 
#define SICR_ENET_MASK  ((uint)0x000000ff)
402 
#define SICR_ENET_CLKRT ((uint)0x0000003d)
403 
#endif  /* CONFIG_MBX */
404 
 
405 
/***  RPXLITE  ********************************************************/
406 
 
407 
#ifdef CONFIG_RPXLITE
408 
/* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
409 
 * this may be unique to the RPX-Lite configuration.
410 
 * Note TENA is on Port B.
411 
 */
412 
#define PA_ENET_RXD     ((ushort)0x0004)
413 
#define PA_ENET_TXD     ((ushort)0x0008)
414 
#define PA_ENET_TCLK    ((ushort)0x0200)
415 
#define PA_ENET_RCLK    ((ushort)0x0800)
416 
#define PB_ENET_TENA    ((uint)0x00002000)
417 
#define PC_ENET_CLSN    ((ushort)0x0040)
418 
#define PC_ENET_RENA    ((ushort)0x0080)
419 
 
420 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
421 
#define SICR_ENET_CLKRT ((uint)0x00003d00)
422 
#endif  /* CONFIG_RPXLITE */
423 
 
424 
/***  BSEIP  **********************************************************/
425 
 
426 
#ifdef CONFIG_BSEIP
427 
/* This ENET stuff is for the MPC823 with ethernet on SCC2.
428 
 * This is unique to the BSE ip-Engine board.
429 
 */
430 
#define PA_ENET_RXD     ((ushort)0x0004)
431 
#define PA_ENET_TXD     ((ushort)0x0008)
432 
#define PA_ENET_TCLK    ((ushort)0x0100)
433 
#define PA_ENET_RCLK    ((ushort)0x0200)
434 
#define PB_ENET_TENA    ((uint)0x00002000)
435 
#define PC_ENET_CLSN    ((ushort)0x0040)
436 
#define PC_ENET_RENA    ((ushort)0x0080)
437 
 
438 
/* BSE uses port B and C bits for PHY control also.
439 
*/
440 
#define PB_BSE_POWERUP  ((uint)0x00000004)
441 
#define PB_BSE_FDXDIS   ((uint)0x00008000)
442 
#define PC_BSE_LOOPBACK ((ushort)0x0800)
443 
 
444 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
445 
#define SICR_ENET_CLKRT ((uint)0x00002c00)
446 
#endif  /* CONFIG_BSEIP */
447 
 
448 
/***  RPXCLASSIC  *****************************************************/
449 
 
450 
#ifdef CONFIG_RPXCLASSIC
451 
/* Bits in parallel I/O port registers that have to be set/cleared
452 
 * to configure the pins for SCC1 use.
453 
 */
454 
#define PA_ENET_RXD     ((ushort)0x0001)
455 
#define PA_ENET_TXD     ((ushort)0x0002)
456 
#define PA_ENET_TCLK    ((ushort)0x0200)
457 
#define PA_ENET_RCLK    ((ushort)0x0800)
458 
#define PB_ENET_TENA    ((uint)0x00001000)
459 
#define PC_ENET_CLSN    ((ushort)0x0010)
460 
#define PC_ENET_RENA    ((ushort)0x0020)
461 
 
462 
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
463 
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
464 
 */
465 
#define SICR_ENET_MASK  ((uint)0x000000ff)
466 
#define SICR_ENET_CLKRT ((uint)0x0000003d)
467 
#endif  /* CONFIG_RPXCLASSIC */
468 
 
469 
/***  D-BOX2  ***********************************************/
470 
 
471 
#ifdef CONFIG_DBOX2
472 
 
473 
#define PA_ENET_RXD     ((ushort)0x0004)
474 
#define PA_ENET_TXD     ((ushort)0x0008)
475 
#define PA_ENET_RCLK    ((ushort)0x0200)
476 
#define PA_ENET_TCLK    ((ushort)0x0800)
477 
 
478 
#define PC_ENET_TENA    ((ushort)0x0002)
479 
#define PC_ENET_CLSN    ((ushort)0x0040)
480 
#define PC_ENET_RENA    ((ushort)0x0080)
481 
 
482 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
483 
#define SICR_ENET_CLKRT ((uint)0x00003d00)
484 
#endif  /* CONFIG_DBOX2 */
485 
 
486 
/***  TQM823L, TQM850L  ***********************************************/
487 
 
488 
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
489 
/* Bits in parallel I/O port registers that have to be set/cleared
490 
 * to configure the pins for SCC1 use.
491 
 */
492 
#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
493 
#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
494 
#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
495 
#define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
496 
 
497 
#define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
498 
 
499 
#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
500 
#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
501 
 
502 
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
503 
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
504 
 */
505 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
506 
#define SICR_ENET_CLKRT ((uint)0x00002600)
507 
#endif  /* CONFIG_TQM823L, CONFIG_TQM850L */
508 
 
509 
/***  FPS850L  *********************************************************/
510 
 
511 
#ifdef CONFIG_FPS850L
512 
/* Bits in parallel I/O port registers that have to be set/cleared
513 
 * to configure the pins for SCC1 use.
514 
 */
515 
#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
516 
#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
517 
#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
518 
#define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
519 
 
520 
#define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
521 
#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
522 
#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
523 
 
524 
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
525 
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
526 
 */
527 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
528 
#define SICR_ENET_CLKRT ((uint)0x00002600)
529 
#endif  /* CONFIG_FPS850L */
530 
 
531 
/***  TQM860L  ********************************************************/
532 
 
533 
#ifdef CONFIG_TQM860L
534 
/* Bits in parallel I/O port registers that have to be set/cleared
535 
 * to configure the pins for SCC1 use.
536 
 */
537 
#define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
538 
#define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
539 
#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
540 
#define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
541 
 
542 
#define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
543 
#define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
544 
#define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
545 
 
546 
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
547 
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
548 
 */
549 
#define SICR_ENET_MASK  ((uint)0x000000ff)
550 
#define SICR_ENET_CLKRT ((uint)0x00000026)
551 
#endif  /* CONFIG_TQM860L */
552 
 
553 
/***  SPD823TS  *******************************************************/
554 
 
555 
#ifdef CONFIG_SPD823TS
556 
/* Bits in parallel I/O port registers that have to be set/cleared
557 
 * to configure the pins for SCC2 use.
558 
 */
559 
#define PA_ENET_MDC     ((ushort)0x0001)        /* PA 15 !!! */
560 
#define PA_ENET_MDIO    ((ushort)0x0002)        /* PA 14 !!! */
561 
#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
562 
#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
563 
#define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
564 
#define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
565 
 
566 
#define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
567 
 
568 
#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
569 
#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
570 
#define PC_ENET_RESET   ((ushort)0x0100)        /* PC  7 !!! */
571 
 
572 
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
573 
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
574 
 */
575 
#define SICR_ENET_MASK  ((uint)0x0000ff00)
576 
#define SICR_ENET_CLKRT ((uint)0x00002E00)
577 
#endif  /* CONFIG_SPD823TS */
578 
 
579 
 
580 
/***  SM850  *********************************************************/
581 
 
582 
/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
583 
 
584 
#ifdef CONFIG_SM850
585 
#define PB_ENET_RXD     ((uint)0x00000004)      /* PB 29 */
586 
#define PB_ENET_TXD     ((uint)0x00000002)      /* PB 30 */
587 
#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
588 
#define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
589 
 
590 
#define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
591 
#define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
592 
 
593 
#define PC_ENET_RENA    ((ushort)0x0800)        /* PC  4 */
594 
#define PC_ENET_CLSN    ((ushort)0x0400)        /* PC  5 */
595 
 
596 
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
597 
 * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
598 
 */
599 
#define SICR_ENET_MASK  ((uint)0x00FF0000)
600 
#define SICR_ENET_CLKRT ((uint)0x00260000)
601 
#endif  /* CONFIG_SM850 */
602 
 
603 
/*********************************************************************/
604 
 
605 
/* SCC Event register as used by Ethernet.
606 
*/
607 
#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
608 
#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
609 
#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
610 
#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
611 
#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
612 
#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
613 
 
614 
/* SCC Mode Register (PMSR) as used by Ethernet.
615 
*/
616 
#define SCC_PMSR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
617 
#define SCC_PMSR_FC     ((ushort)0x4000)        /* Force collision */
618 
#define SCC_PMSR_RSH    ((ushort)0x2000)        /* Receive short frames */
619 
#define SCC_PMSR_IAM    ((ushort)0x1000)        /* Check individual hash */
620 
#define SCC_PMSR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
621 
#define SCC_PMSR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
622 
#define SCC_PMSR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
623 
#define SCC_PMSR_SBT    ((ushort)0x0080)        /* Special backoff timer */
624 
#define SCC_PMSR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
625 
#define SCC_PMSR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
626 
#define SCC_PMSR_LCW    ((ushort)0x0010)        /* Late collision window */
627 
#define SCC_PMSR_NIB22  ((ushort)0x000a)        /* Start frame search */
628 
#define SCC_PMSR_FDE    ((ushort)0x0001)        /* Full duplex enable */
629 
 
630 
/* Buffer descriptor control/status used by Ethernet receive.
631 
*/
632 
#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
633 
#define BD_ENET_RX_WRAP         ((ushort)0x2000)
634 
#define BD_ENET_RX_INTR         ((ushort)0x1000)
635 
#define BD_ENET_RX_LAST         ((ushort)0x0800)
636 
#define BD_ENET_RX_FIRST        ((ushort)0x0400)
637 
#define BD_ENET_RX_MISS         ((ushort)0x0100)
638 
#define BD_ENET_RX_LG           ((ushort)0x0020)
639 
#define BD_ENET_RX_NO           ((ushort)0x0010)
640 
#define BD_ENET_RX_SH           ((ushort)0x0008)
641 
#define BD_ENET_RX_CR           ((ushort)0x0004)
642 
#define BD_ENET_RX_OV           ((ushort)0x0002)
643 
#define BD_ENET_RX_CL           ((ushort)0x0001)
644 
#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
645 
 
646 
/* Buffer descriptor control/status used by Ethernet transmit.
647 
*/
648 
#define BD_ENET_TX_READY        ((ushort)0x8000)
649 
#define BD_ENET_TX_PAD          ((ushort)0x4000)
650 
#define BD_ENET_TX_WRAP         ((ushort)0x2000)
651 
#define BD_ENET_TX_INTR         ((ushort)0x1000)
652 
#define BD_ENET_TX_LAST         ((ushort)0x0800)
653 
#define BD_ENET_TX_TC           ((ushort)0x0400)
654 
#define BD_ENET_TX_DEF          ((ushort)0x0200)
655 
#define BD_ENET_TX_HB           ((ushort)0x0100)
656 
#define BD_ENET_TX_LC           ((ushort)0x0080)
657 
#define BD_ENET_TX_RL           ((ushort)0x0040)
658 
#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
659 
#define BD_ENET_TX_UN           ((ushort)0x0002)
660 
#define BD_ENET_TX_CSL          ((ushort)0x0001)
661 
#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
662 
 
663 
/* SCC as UART
664 
*/
665 
typedef struct scc_uart {
666 
        sccp_t  scc_genscc;
667 
        uint    scc_res1;       /* Reserved */
668 
        uint    scc_res2;       /* Reserved */
669 
        ushort  scc_maxidl;     /* Maximum idle chars */
670 
        ushort  scc_idlc;       /* temp idle counter */
671 
        ushort  scc_brkcr;      /* Break count register */
672 
        ushort  scc_parec;      /* receive parity error counter */
673 
        ushort  scc_frmec;      /* receive framing error counter */
674 
        ushort  scc_nosec;      /* receive noise counter */
675 
        ushort  scc_brkec;      /* receive break condition counter */
676 
        ushort  scc_brkln;      /* last received break length */
677 
        ushort  scc_uaddr1;     /* UART address character 1 */
678 
        ushort  scc_uaddr2;     /* UART address character 2 */
679 
        ushort  scc_rtemp;      /* Temp storage */
680 
        ushort  scc_toseq;      /* Transmit out of sequence char */
681 
        ushort  scc_char1;      /* control character 1 */
682 
        ushort  scc_char2;      /* control character 2 */
683 
        ushort  scc_char3;      /* control character 3 */
684 
        ushort  scc_char4;      /* control character 4 */
685 
        ushort  scc_char5;      /* control character 5 */
686 
        ushort  scc_char6;      /* control character 6 */
687 
        ushort  scc_char7;      /* control character 7 */
688 
        ushort  scc_char8;      /* control character 8 */
689 
        ushort  scc_rccm;       /* receive control character mask */
690 
        ushort  scc_rccr;       /* receive control character register */
691 
        ushort  scc_rlbc;       /* receive last break character */
692 
} scc_uart_t;
693 
 
694 
/* SCC Event and Mask registers when it is used as a UART.
695 
*/
696 
#define UART_SCCM_GLR           ((ushort)0x1000)
697 
#define UART_SCCM_GLT           ((ushort)0x0800)
698 
#define UART_SCCM_AB            ((ushort)0x0200)
699 
#define UART_SCCM_IDL           ((ushort)0x0100)
700 
#define UART_SCCM_GRA           ((ushort)0x0080)
701 
#define UART_SCCM_BRKE          ((ushort)0x0040)
702 
#define UART_SCCM_BRKS          ((ushort)0x0020)
703 
#define UART_SCCM_CCR           ((ushort)0x0008)
704 
#define UART_SCCM_BSY           ((ushort)0x0004)
705 
#define UART_SCCM_TX            ((ushort)0x0002)
706 
#define UART_SCCM_RX            ((ushort)0x0001)
707 
 
708 
/* The SCC PMSR when used as a UART.
709 
*/
710 
#define SCU_PMSR_FLC            ((ushort)0x8000)
711 
#define SCU_PMSR_SL             ((ushort)0x4000)
712 
#define SCU_PMSR_CL             ((ushort)0x3000)
713 
#define SCU_PMSR_UM             ((ushort)0x0c00)
714 
#define SCU_PMSR_FRZ            ((ushort)0x0200)
715 
#define SCU_PMSR_RZS            ((ushort)0x0100)
716 
#define SCU_PMSR_SYN            ((ushort)0x0080)
717 
#define SCU_PMSR_DRT            ((ushort)0x0040)
718 
#define SCU_PMSR_PEN            ((ushort)0x0010)
719 
#define SCU_PMSR_RPM            ((ushort)0x000c)
720 
#define SCU_PMSR_REVP           ((ushort)0x0008)
721 
#define SCU_PMSR_TPM            ((ushort)0x0003)
722 
#define SCU_PMSR_TEVP           ((ushort)0x0002)
723 
 
724 
/* CPM Transparent mode SCC.
725 
 */
726 
typedef struct scc_trans {
727 
        sccp_t  st_genscc;
728 
        uint    st_cpres;       /* Preset CRC */
729 
        uint    st_cmask;       /* Constant mask for CRC */
730 
} scc_trans_t;
731 
 
732 
#define BD_SCC_TX_LAST          ((ushort)0x0800)
733 
 
734 
/* IIC parameter RAM.
735 
*/
736 
typedef struct iic {
737 
        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
738 
        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
739 
        u_char  iic_rfcr;       /* Rx function code */
740 
        u_char  iic_tfcr;       /* Tx function code */
741 
        ushort  iic_mrblr;      /* Max receive buffer length */
742 
        uint    iic_rstate;     /* Internal */
743 
        uint    iic_rdp;        /* Internal */
744 
        ushort  iic_rbptr;      /* Internal */
745 
        ushort  iic_rbc;        /* Internal */
746 
        uint    iic_rxtmp;      /* Internal */
747 
        uint    iic_tstate;     /* Internal */
748 
        uint    iic_tdp;        /* Internal */
749 
        ushort  iic_tbptr;      /* Internal */
750 
        ushort  iic_tbc;        /* Internal */
751 
        uint    iic_txtmp;      /* Internal */
752 
        uint    iic_res;
753 
        ushort  iic_rpbase;     /* Relocation pointer */
754 
        ushort  iic_res2;
755 
 
756 
} iic_t;
757 
 
758 
#define BD_IIC_START            ((ushort)0x0400)
759 
 
760 
/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
761 
 * channels or devices.  All of these are presented to the PPC core
762 
 * as a single interrupt.  The CPM interrupt handler dispatches its
763 
 * own handlers, in a similar fashion to the PPC core handler.  We
764 
 * use the table as defined in the manuals (i.e. no special high
765 
 * priority and SCC1 == SCCa, etc...).
766 
 */
767 
#define CPMVEC_NR               32
768 
#define CPMVEC_PIO_PC15         ((ushort)0x1f)
769 
#define CPMVEC_SCC1             ((ushort)0x1e)
770 
#define CPMVEC_SCC2             ((ushort)0x1d)
771 
#define CPMVEC_SCC3             ((ushort)0x1c)
772 
#define CPMVEC_SCC4             ((ushort)0x1b)
773 
#define CPMVEC_PIO_PC14         ((ushort)0x1a)
774 
#define CPMVEC_TIMER1           ((ushort)0x19)
775 
#define CPMVEC_PIO_PC13         ((ushort)0x18)
776 
#define CPMVEC_PIO_PC12         ((ushort)0x17)
777 
#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
778 
#define CPMVEC_IDMA1            ((ushort)0x15)
779 
#define CPMVEC_IDMA2            ((ushort)0x14)
780 
#define CPMVEC_TIMER2           ((ushort)0x12)
781 
#define CPMVEC_RISCTIMER        ((ushort)0x11)
782 
#define CPMVEC_I2C              ((ushort)0x10)
783 
#define CPMVEC_PIO_PC11         ((ushort)0x0f)
784 
#define CPMVEC_PIO_PC10         ((ushort)0x0e)
785 
#define CPMVEC_TIMER3           ((ushort)0x0c)
786 
#define CPMVEC_PIO_PC9          ((ushort)0x0b)
787 
#define CPMVEC_PIO_PC8          ((ushort)0x0a)
788 
#define CPMVEC_PIO_PC7          ((ushort)0x09)
789 
#define CPMVEC_TIMER4           ((ushort)0x07)
790 
#define CPMVEC_PIO_PC6          ((ushort)0x06)
791 
#define CPMVEC_SPI              ((ushort)0x05)
792 
#define CPMVEC_SMC1             ((ushort)0x04)
793 
#define CPMVEC_SMC2             ((ushort)0x03)
794 
#define CPMVEC_PIO_PC5          ((ushort)0x02)
795 
#define CPMVEC_PIO_PC4          ((ushort)0x01)
796 
#define CPMVEC_ERROR            ((ushort)0x00)
797 
 
798 
/* CPM interrupt configuration vector.
799 
*/
800 
#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
801 
#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
802 
#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
803 
#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
804 
#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
805 
#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
806 
#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
807 
#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
808 
 
809 
extern void cpm_install_handler(int vec,
810 
                void (*handler)(void *, struct pt_regs *regs), void *dev_id);
811 
extern void cpm_free_handler(int vec);
812 
extern const char *cpm_int_name[];
813 
 
814 
#endif /* __CPM_8XX__ */

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