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phoenix |
/*
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* asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
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*
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* Copyright (C) 1997 Geert Uytterhoeven
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*
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* This file is based on the following documentation:
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*
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* The VAS96011/12 Chipset, Data Book, Edition 1.0
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* VLSI Technology, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASMPPC_GG2_H
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#define _ASMPPC_GG2_H
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/*
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* Memory Map (CHRP mode)
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*/
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#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
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#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
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#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
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#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */
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#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */
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/* special PCI cycles */
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#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
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#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
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/*
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* GG2 specific PCI Registers
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*/
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extern unsigned long gg2_pci_config_base; /* kernel virtual address */
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#define GG2_PCI_BUSNO 0x40 /* Bus number */
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#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
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#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */
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#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */
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#define GG2_PCI_ADDR_MAP 0x5c /* Address map */
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#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */
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#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */
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#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */
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#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */
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#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
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#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
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#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
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#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
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#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
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#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */
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#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */
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#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */
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#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */
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#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */
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#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */
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/* Cleared when read */
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#endif /* _ASMPPC_GG2_H */
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