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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-ppc/] [pci-bridge.h] - Blame information for rev 1774

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1 1276 phoenix
#ifdef __KERNEL__
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#ifndef _ASM_PCI_BRIDGE_H
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#define _ASM_PCI_BRIDGE_H
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#include <linux/ioport.h>
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#include <linux/pci.h>
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struct device_node;
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struct pci_controller;
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/*
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 * pci_io_base returns the memory address at which you can access
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 * the I/O space for PCI bus number `bus' (or NULL on error).
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 */
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extern void *pci_bus_io_base(unsigned int bus);
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extern unsigned long pci_bus_io_base_phys(unsigned int bus);
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extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
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/* Allocate a new PCI host bridge structure */
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extern struct pci_controller* pcibios_alloc_controller(void);
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/* Helper function for setting up resources */
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extern void pci_init_resource(struct resource *res, unsigned long start,
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                              unsigned long end, int flags, char *name);
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/*
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 * PCI <-> OF matching functions
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 */
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extern int pci_device_from_OF_node(struct device_node *node,
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                                   u8* bus, u8* devfn);
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extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
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extern void pci_create_OF_bus_map(void);
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/* Get the PCI host controller for a bus */
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extern struct pci_controller* pci_bus_to_hose(int bus);
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller*
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pci_find_hose_for_OF_device(struct device_node* node);
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/* Fill up host controller resources from the OF node */
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extern void
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pci_process_bridge_OF_ranges(struct pci_controller *hose,
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                           struct device_node *dev, int primary);
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/*
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 * Structure of a PCI controller (host bridge)
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 */
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struct pci_controller {
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        int index;                      /* used for pci_controller_num */
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        struct pci_controller *next;
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        struct pci_bus *bus;
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        void *arch_data;
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        int first_busno;
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        int last_busno;
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        int bus_offset;
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        void *io_base_virt;
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        unsigned long io_base_phys;
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        /* Some machines (PReP) have a non 1:1 mapping of
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         * the PCI memory space in the CPU bus space
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         */
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        unsigned long pci_mem_offset;
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        struct pci_ops *ops;
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        volatile unsigned int *cfg_addr;
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        volatile unsigned char *cfg_data;
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        /*
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         * If set, indirect method will set the cfg_type bit as
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         * needed to generate type 1 configuration transactions.
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         */
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        int set_cfg_type;
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        /* Currently, we limit ourselves to 1 IO range and 3 mem
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         * ranges since the common pci_bus structure can't handle more
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         */
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        struct resource io_resource;
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        struct resource mem_resources[3];
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        int mem_resource_count;
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        /* Host bridge I/O and Memory space
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         * Used for BAR placement algorithms
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         */
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        struct resource io_space;
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        struct resource mem_space;
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};
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/* These are used for config access before all the PCI probing
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   has been done. */
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int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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                           int where, u8 *val);
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int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
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                           int where, u16 *val);
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int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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                            int where, u32 *val);
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int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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                            int where, u8 val);
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int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
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                            int where, u16 val);
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int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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                             int where, u32 val);
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extern void setup_indirect_pci(struct pci_controller* hose,
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                               u32 cfg_addr, u32 cfg_data);
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extern void setup_grackle(struct pci_controller *hose);
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extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
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/*
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 *   The following code swizzles for exactly one bridge.  The routine
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 *   common_swizzle below handles multiple bridges.  But there are a
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 *   some boards that don't follow the PCI spec's suggestion so we
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 *   break this piece out separately.
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 */
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static inline unsigned char bridge_swizzle(unsigned char pin,
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                unsigned char idsel)
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{
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        return (((pin-1) + idsel) % 4) + 1;
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}
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/*
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 * The following macro is used to lookup irqs in a standard table
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 * format for those PPC systems that do not already have PCI
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 * interrupts properly routed.
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 */
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/* FIXME - double check this */
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#define PCI_IRQ_TABLE_LOOKUP                                                \
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({ long _ctl_ = -1;                                                         \
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   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
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     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];                       \
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   _ctl_; })
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/*
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 * Scan the buses below a given PCI host bridge and assign suitable
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 * resources to all devices found.
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 */
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extern int pciauto_bus_scan(struct pci_controller *, int);
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#endif
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#endif /* __KERNEL__ */

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