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phoenix |
/*
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* arch/ppc/kernel/pplus.h
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*
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* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASMPPC_PPLUS_H
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#define __ASMPPC_PPLUS_H
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#include <asm/pci-bridge.h>
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/*
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* The Falcon/Raven and HAWK have 4 sets of registers:
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* 1) PPC Registers which define the mappings from PPC bus to PCI bus,
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* etc.
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* 2) PCI Registers which define the mappings from PCI bus to PPC bus and the
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* MPIC base address.
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* 3) MPIC registers
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* 4) System Memory Controller (SMC) registers.
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*/
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#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057
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#define PPLUS_HAWK_VEND_DEV_ID 0x48031057
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#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8
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#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc
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#define PPLUS_MPIC_SIZE 0x00040000U
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#define PPLUS_SMC_SIZE 0x00001000U
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/*
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* Define PPC register offsets.
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*/
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#define PPLUS_PPC_XSADD0_OFF 0x40
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#define PPLUS_PPC_XSOFF0_OFF 0x44
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#define PPLUS_PPC_XSADD1_OFF 0x48
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#define PPLUS_PPC_XSOFF1_OFF 0x4c
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#define PPLUS_PPC_XSADD2_OFF 0x50
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#define PPLUS_PPC_XSOFF2_OFF 0x54
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#define PPLUS_PPC_XSADD3_OFF 0x58
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#define PPLUS_PPC_XSOFF3_OFF 0x5c
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/*
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* Define PCI register offsets.
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*/
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#define PPLUS_PCI_PSADD0_OFF 0x80
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#define PPLUS_PCI_PSOFF0_OFF 0x84
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#define PPLUS_PCI_PSADD1_OFF 0x88
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#define PPLUS_PCI_PSOFF1_OFF 0x8c
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#define PPLUS_PCI_PSADD2_OFF 0x90
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#define PPLUS_PCI_PSOFF2_OFF 0x94
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#define PPLUS_PCI_PSADD3_OFF 0x98
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#define PPLUS_PCI_PSOFF3_OFF 0x9c
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/*
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* Define the System Memory Controller (SMC) register offsets.
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*/
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#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10
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#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11
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#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12
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#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13
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#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
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#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
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#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
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#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
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#define PPLUS_FALCON_SMC_REG_COUNT 4
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#define PPLUS_HAWK_SMC_REG_COUNT 8
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int pplus_init(struct pci_controller *hose,
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uint ppc_reg_base,
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ulong processor_pci_mem_start,
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ulong processor_pci_mem_end,
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ulong processor_pci_io_start,
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ulong processor_pci_io_end,
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ulong processor_mpic_base);
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unsigned long pplus_get_mem_size(uint smc_base);
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int pplus_mpic_init(unsigned int pci_mem_offset);
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#endif /* __ASMPPC_PPLUS_H */
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