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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-ppc64/] [iSeries/] [iSeries_dma.h] - Blame information for rev 1774

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Line No. Rev Author Line
1 1275 phoenix
/*
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 * iSeries_dma.h
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 * Copyright (C) 2001  Mike Corrigan IBM Corporation
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
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 */
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#ifndef _ISERIES_DMA_H
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#define _ISERIES_DMA_H
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#include <asm/types.h>
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#ifndef __LINUX_SPINLOCK_H
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#include <linux/spinlock.h>
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#endif
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// NUM_TCE_LEVELS defines the largest contiguous block
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// of dma (tce) space we can get.  NUM_TCE_LEVELS = 10 
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// allows up to 2**9 pages (512 * 4096) = 2 MB
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#define NUM_TCE_LEVELS 10
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#define NO_TCE ((dma_addr_t)-1)
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// Tces come in two formats, one for the virtual bus and a different
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// format for PCI
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#define TCE_VB  0
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#define TCE_PCI 1
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union Tce {
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        u64     wholeTce;
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        struct {
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                u64     cacheBits       :6;     /* Cache hash bits - not used */
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                u64     rsvd            :6;
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                u64     rpn             :40;    /* Absolute page number */
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                u64     valid           :1;     /* Tce is valid (vb only) */
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                u64     allIo           :1;     /* Tce is valid for all lps (vb only) */
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                u64     lpIndex         :8;     /* LpIndex for user of TCE (vb only) */
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                u64     pciWrite        :1;     /* Write allowed (pci only) */
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                u64     readWrite       :1;     /* Read allowed (pci), Write allowed
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                                                   (vb) */
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        } tceBits;
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};
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struct Bitmap {
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        unsigned long   numBits;
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        unsigned long   numBytes;
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        unsigned char * map;
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};
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struct MultiLevelBitmap {
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        unsigned long   maxLevel;
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        struct Bitmap   level[NUM_TCE_LEVELS];
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};
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struct TceTable {
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        u64     busNumber;
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        u64     size;
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        u64     startOffset;
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        u64     index;
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        spinlock_t      lock;
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        struct MultiLevelBitmap mlbm;
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};
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struct HvTceTableManagerCB {
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        u64     busNumber;              /* Bus number for this tce table */
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        u64     start;                  /* Will be NULL for secondary */
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        u64     totalSize;              /* Size (in pages) of whole table */
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        u64     startOffset;            /* Index into real tce table of the
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                                           start of our section */
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        u64     size;                   /* Size (in pages) of our section */
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        u64     index;                  /* Index of this tce table (token?) */
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        u16     maxTceTableIndex;       /* Max number of tables for partition */
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        u8      virtualBusFlag;         /* Flag to indicate virtual bus */
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        u8      rsvd[5];
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};
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extern struct TceTable virtBusTceTable; /* Tce table for virtual bus */
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extern struct TceTable * build_tce_table( struct HvTceTableManagerCB *,
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                                          struct TceTable *);
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extern void              create_virtual_bus_tce_table( void );
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extern void              create_pci_bus_tce_table( unsigned busNumber );
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#endif // _ISERIES_DMA_H

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