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phoenix |
#ifndef _PPC64_PACA_H
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#define _PPC64_PACA_H
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/*============================================================================
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* Header File Id
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* Name______________: paca.h
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*
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* Description_______:
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*
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* This control block defines the PACA which defines the processor
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* specific data for each logical processor on the system.
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* There are some pointers defined that are utilized by PLIC.
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*
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* C 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/types.h>
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#define N_EXC_STACK 2
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/*-----------------------------------------------------------------------------
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* Other Includes
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*-----------------------------------------------------------------------------
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*/
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#include <asm/iSeries/ItLpPaca.h>
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#include <asm/iSeries/ItLpRegSave.h>
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#include <asm/iSeries/ItLpQueue.h>
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#include <asm/rtas.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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/* A paca entry is required for each logical processor. On systems
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* that support hardware multi-threading, this is equal to twice the
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* number of physical processors. On LPAR systems, we are required
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* to have space for the maximum number of logical processors we
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* could ever possibly have. Currently, we are limited to allocating
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* 24 processors to a partition which gives 48 logical processors on
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* an HMT box. Therefore, we reserve this many paca entries.
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*/
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#define MAX_PROCESSORS 24
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#define MAX_PACAS MAX_PROCESSORS * 2
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extern struct paca_struct paca[];
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register struct paca_struct *local_paca asm("r13");
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#define get_paca() local_paca
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/*============================================================================
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* Name_______: paca
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*
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* Description:
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*
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* Defines the layout of the paca.
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*
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* This structure is not directly accessed by PLIC or the SP except
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* for the first two pointers that point to the ItLpPaca area and the
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* ItLpRegSave area for this processor. Both the ItLpPaca and
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* ItLpRegSave objects are currently contained within the
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* PACA but they do not need to be.
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*
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*============================================================================
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*/
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struct paca_struct {
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/*=====================================================================================
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* CACHE_LINE_1 0x0000 - 0x007F
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*=====================================================================================
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*/
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struct ItLpPaca *xLpPacaPtr; /* Pointer to LpPaca for PLIC 0x00 */
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struct ItLpRegSave *xLpRegSavePtr; /* Pointer to LpRegSave for PLIC 0x08 */
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u64 xCurrent; /* Pointer to current 0x10 */
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u16 xPacaIndex; /* Logical processor number 0x18 */
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u16 xHwProcNum; /* Actual Hardware Processor Number 0x1a */
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u32 default_decr; /* Default decrementer value 0x1c */
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u64 xHrdIntStack; /* Stack for hardware interrupts 0x20 */
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u64 xKsave; /* Saved Kernel stack addr or zero 0x28 */
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u64 pvr; /* Processor version register 0x30 */
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u8 *exception_sp; /* 0x38 */
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struct ItLpQueue *lpQueuePtr; /* LpQueue handled by this processor 0x40 */
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u64 xTOC; /* Kernel TOC address 0x48 */
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STAB xStab_data; /* Segment table information 0x50,0x58,0x60 */
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u8 xSegments[STAB_CACHE_SIZE]; /* Cache of used stab entries 0x68,0x70 */
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u8 xProcEnabled; /* 1=soft enabled 0x78 */
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u8 xHrdIntCount; /* Count of active hardware interrupts 0x79 */
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u8 active; /* Is this cpu active? 0x1a */
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u8 available; /* Is this cpu available? 0x1b */
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u8 resv1[4]; /* 0x7B-0x7F */
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/*=====================================================================================
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* CACHE_LINE_2 0x0080 - 0x00FF
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*=====================================================================================
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*/
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u64 *pgd_cache; /* 0x00 */
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u64 *pmd_cache; /* 0x08 */
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u64 *pte_cache; /* 0x10 */
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u64 pgtable_cache_sz; /* 0x18 */
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u64 next_jiffy_update_tb; /* TB value for next jiffy update 0x20 */
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u32 lpEvent_count; /* lpEvents processed 0x28 */
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u8 yielded; /* 0 = this processor is running 0x2c */
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/* 1 = this processor is yielded */
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u8 rsvd2[128-5*8-1*4-1]; /* 0x68 */
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/*=====================================================================================
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* CACHE_LINE_3 0x0100 - 0x017F
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*=====================================================================================
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*/
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u8 xProcStart; /* At startup, processor spins until 0x100 */
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/* xProcStart becomes non-zero. */
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u8 rsvd3[127];
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/*=====================================================================================
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* CACHE_LINE_4-8 0x0180 - 0x03FF Contains ItLpPaca
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*=====================================================================================
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*/
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struct ItLpPaca xLpPaca; /* Space for ItLpPaca */
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/*=====================================================================================
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* CACHE_LINE_9-16 0x0400 - 0x07FF Contains ItLpRegSave
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*=====================================================================================
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*/
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struct ItLpRegSave xRegSav; /* Register save for proc */
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/*=====================================================================================
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* CACHE_LINE_17-18 0x0800 - 0x0EFF Reserved
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*=====================================================================================
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*/
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struct rtas_args xRtas; /* Per processor RTAS struct */
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u64 xR1; /* r1 save for RTAS calls */
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u64 xSavedMsr; /* Old msr saved here by HvCall */
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u8 rsvd5[256-16-sizeof(struct rtas_args)];
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/*=====================================================================================
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* CACHE_LINE_19 - 20 Profile Data
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*=====================================================================================
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*/
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u64 pmc[12]; /* Default pmc value */
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u64 pmcc[8]; /* Cumulative pmc counts */
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u32 prof_multiplier; /* */
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u32 prof_shift; /* iSeries shift for profile bucket size */
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u32 *prof_buffer; /* iSeries profiling buffer */
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u32 *prof_stext; /* iSeries start of kernel text */
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u32 *prof_etext; /* iSeries start of kernel text */
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u32 prof_len; /* iSeries length of profile buffer -1 */
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u8 prof_mode; /* */
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u8 rsvv5b[3];
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u64 prof_counter; /* */
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u8 rsvd5c[256-8*26];
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/*=====================================================================================
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* CACHE_LINE_20-30
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*=====================================================================================
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*/
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u64 slb_shadow[0x20];
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u64 dispatch_log;
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u8 rsvd6[0x400 - 0x8];
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/*=====================================================================================
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* CACHE_LINE_31 0x0F00 - 0x0F7F Exception stack
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*=====================================================================================
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*/
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u8 exception_stack[N_EXC_STACK*EXC_FRAME_SIZE];
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/*=====================================================================================
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* CACHE_LINE_32 0x0F80 - 0x0FFF Reserved
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*=====================================================================================
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*/
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u8 rsvd7[0x80]; /* Give the stack some rope ... */
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/*=====================================================================================
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* Page 2 Reserved for guard page. Also used as a stack early in SMP boots before
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* relocation is enabled.
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*=====================================================================================
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*/
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u8 guard[0x1000]; /* ... and then hang 'em */
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};
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#define get_hard_smp_processor_id(CPU) (paca[(CPU)].xHwProcNum)
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#endif /* _PPC64_PACA_H */
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