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1275 |
phoenix |
/*
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* include/asm-s390/spinlock.h
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*
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* S390 version
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* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/spinlock.h"
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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/*
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* Grmph, take care of %&#! user space programs that include
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* asm/spinlock.h. The diagnose is only available in kernel
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* context.
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*/
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#ifdef __KERNEL__
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#include <asm/lowcore.h>
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#define __DIAG44_INSN "ex"
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#define __DIAG44_OPERAND __LC_DIAG44_OPCODE
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#else
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#define __DIAG44_INSN "#"
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#define __DIAG44_OPERAND 0
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#endif
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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typedef struct {
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volatile unsigned int lock;
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} __attribute__ ((aligned (4))) spinlock_t;
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#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
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#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
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#define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
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#define spin_is_locked(x) ((x)->lock != 0)
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extern inline void spin_lock(spinlock_t *lp)
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{
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unsigned long reg1, reg2;
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__asm__ __volatile(" bras %1,1f\n"
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"0: " __DIAG44_INSN " 0,%3\n"
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"1: slr %0,%0\n"
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" cs %0,%1,0(%2)\n"
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" jl 0b\n"
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: "=&d" (reg1), "=&d" (reg2)
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: "a" (&lp->lock), "i" (__DIAG44_OPERAND)
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: "cc", "memory" );
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}
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extern inline int spin_trylock(spinlock_t *lp)
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{
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unsigned int result, reg;
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__asm__ __volatile(" slr %0,%0\n"
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" basr %1,0\n"
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"0: cs %0,%1,0(%2)"
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: "=&d" (result), "=&d" (reg)
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: "a" (&lp->lock) : "cc", "memory" );
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return !result;
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}
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extern inline void spin_unlock(spinlock_t *lp)
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{
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__asm__ __volatile(" xc 0(4,%0),0(%0)\n"
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" bcr 15,0"
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: : "a" (&lp->lock) : "memory", "cc" );
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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typedef struct {
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volatile unsigned long lock;
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volatile unsigned long owner_pc;
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} rwlock_t;
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#define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
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#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
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#define read_lock(rw) \
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asm volatile(" lg 2,0(%0)\n" \
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" j 1f\n" \
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"0: " __DIAG44_INSN " 0,%1\n" \
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"1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \
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" la 3,1(2)\n" /* one more reader */ \
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" csg 2,3,0(%0)\n" /* try to write new value */ \
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" jl 0b" \
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: : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND) \
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: "2", "3", "cc", "memory" )
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#define read_unlock(rw) \
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asm volatile(" lg 2,0(%0)\n" \
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" j 1f\n" \
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"0: " __DIAG44_INSN " 0,%1\n" \
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"1: lgr 3,2\n" \
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" bctgr 3,0\n" /* one less reader */ \
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" csg 2,3,0(%0)\n" \
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" jl 0b" \
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: : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND) \
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: "2", "3", "cc", "memory" )
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#define write_lock(rw) \
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asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
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" j 1f\n" \
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"0: " __DIAG44_INSN " 0,%1\n" \
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"1: slgr 2,2\n" /* old lock value must be 0 */ \
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" csg 2,3,0(%0)\n" \
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" jl 0b" \
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: : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND) \
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: "2", "3", "cc", "memory" )
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#define write_unlock(rw) \
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asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \
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" j 1f\n" \
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"0: " __DIAG44_INSN " 0,%1\n" \
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"1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
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" csg 2,3,0(%0)\n" \
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" jl 0b" \
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: : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND) \
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: "2", "3", "cc", "memory" )
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#endif /* __ASM_SPINLOCK_H */
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