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#ifndef __ASM_SH_HITACHI_HS7729PCI_H
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#define __ASM_SH_HITACHI_HS7729PCI_H
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/*
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* linux/include/asm-sh/hitachi_hs7729pci.h
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Hitachi Semiconductor and Devices HS7729PCI support
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*/
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/* Box specific addresses. */
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#define PA_SUPERIO 0xa8000000 /* SMC37C935A super io chip */
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#define PA_DIPSW0 0xa8c00000 /* Dip switch 5,6 */
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#define PA_DIPSW1 0xa8c00002 /* Dip switch 7,8 */
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#define PA_LED 0xa8c40000 /* LED */
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#define PA_7SEG 0xa8c40002 /* 7 segment LED */
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#define PA_BCR 0xa8c80000 /* FPGA */
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#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
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#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 0x06)
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#define MRSHPC_CSR (PA_MRSHPC + 0x08)
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#define MRSHPC_ISR (PA_MRSHPC + 0x0a)
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#define MRSHPC_ICR (PA_MRSHPC + 0x0c)
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#define MRSHPC_CPWCR (PA_MRSHPC + 0x0e)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 0x10)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 0x12)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 0x14)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 0x16)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 0x18)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 0x1a)
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#define MRSHPC_CDCR (PA_MRSHPC + 0x1c)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 0x1e)
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#define BCR_ILCRA (PA_BCR + 0)
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#define BCR_ILCRB (PA_BCR + 2)
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#define BCR_ILCRC (PA_BCR + 4)
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#define BCR_ILCRD (PA_BCR + 6)
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#define BCR_ILCRE (PA_BCR + 8)
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#define BCR_ILCRF (PA_BCR + 10)
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#define BCR_ILCRG (PA_BCR + 12)
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#define SH7729PCI_PCI_HOST_BRIDGE 0xb0000000 /* SD0001 Register */
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#define SH7729PCI_PCI_AREA 0xb0800000 /* PCI I/O Window */
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#define SH7729PCI_PCI_MEM_START CONFIG_MEMORY_START
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#define SH7729PCI_PCI_MEM_SIZE CONFIG_MEMORY_SIZE
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#define SH7729PCI_PCI_IRQ 0 /* SD0001 Interrupt Number */
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#endif /* __ASM_SH_HITACHI_HS7729PCI_H */
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