OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-sparc/] [mostek.h] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1275 phoenix
/* $Id: mostek.h,v 1.1.1.1 2004-04-15 02:40:29 phoenix Exp $
2
 * mostek.h:  Describes the various Mostek time of day clock registers.
3
 *
4
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5
 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
6
 * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
7
 */
8
 
9
#ifndef _SPARC_MOSTEK_H
10
#define _SPARC_MOSTEK_H
11
 
12
#include <linux/config.h>
13
#include <asm/idprom.h>
14
 
15
/*       M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
16
 *
17
 *                             Data
18
 * Address                                                 Function
19
 *        Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
20
 *   7ff  -     -     -     -    -     -     -     -       Year 00-99
21
 *   7fe  0     0     0     -    -     -     -     -      Month 01-12
22
 *   7fd  0     0     -     -    -     -     -     -       Date 01-31
23
 *   7fc  0     FT    0     0    0     -     -     -        Day 01-07
24
 *   7fb  KS    0     -     -    -     -     -     -      Hours 00-23
25
 *   7fa  0     -     -     -    -     -     -     -    Minutes 00-59
26
 *   7f9  ST    -     -     -    -     -     -     -    Seconds 00-59
27
 *   7f8  W     R     S     -    -     -     -     -    Control
28
 *
29
 *   * ST is STOP BIT
30
 *   * W is WRITE BIT
31
 *   * R is READ BIT
32
 *   * S is SIGN BIT
33
 *   * FT is FREQ TEST BIT
34
 *   * KS is KICK START BIT
35
 */
36
 
37
/* The Mostek 48t02 real time clock and NVRAM chip. The registers
38
 * other than the control register are in binary coded decimal. Some
39
 * control bits also live outside the control register.
40
 */
41
#define mostek_read(_addr)              (*((volatile u8 *)(_addr)))
42
#define mostek_write(_addr,_val)        ((*((volatile u8 *)(_addr))) = (_val))
43
#define MOSTEK_EEPROM           0x0000UL
44
#define MOSTEK_IDPROM           0x07d8UL
45
#define MOSTEK_CREG             0x07f8UL
46
#define MOSTEK_SEC              0x07f9UL
47
#define MOSTEK_MIN              0x07faUL
48
#define MOSTEK_HOUR             0x07fbUL
49
#define MOSTEK_DOW              0x07fcUL
50
#define MOSTEK_DOM              0x07fdUL
51
#define MOSTEK_MONTH            0x07feUL
52
#define MOSTEK_YEAR             0x07ffUL
53
 
54
struct mostek48t02 {
55
        volatile char eeprom[2008];     /* This is the eeprom, don't touch! */
56
        struct idprom idprom;           /* The idprom lives here. */
57
        volatile unsigned char creg;    /* Control register */
58
        volatile unsigned char sec;     /* Seconds (0-59) */
59
        volatile unsigned char min;     /* Minutes (0-59) */
60
        volatile unsigned char hour;    /* Hour (0-23) */
61
        volatile unsigned char dow;     /* Day of the week (1-7) */
62
        volatile unsigned char dom;     /* Day of the month (1-31) */
63
        volatile unsigned char month;   /* Month of year (1-12) */
64
        volatile unsigned char year;    /* Year (0-99) */
65
};
66
 
67
extern spinlock_t mostek_lock;
68
extern unsigned long mstk48t02_regs;
69
 
70
/* Control register values. */
71
#define MSTK_CREG_WRITE 0x80    /* Must set this before placing values. */
72
#define MSTK_CREG_READ  0x40    /* Stop updates to allow a clean read. */
73
#define MSTK_CREG_SIGN  0x20    /* Slow/speed clock in calibration mode. */
74
 
75
/* Control bits that live in the other registers. */
76
#define MSTK_STOP       0x80    /* Stop the clock oscillator. (sec) */
77
#define MSTK_KICK_START 0x80    /* Kick start the clock chip. (hour) */
78
#define MSTK_FREQ_TEST  0x40    /* Frequency test mode. (day) */
79
 
80
#define MSTK_YEAR_ZERO       1968   /* If year reg has zero, it is 1968. */
81
#define MSTK_CVT_YEAR(yr)  ((yr) + MSTK_YEAR_ZERO)
82
 
83
/* Masks that define how much space each value takes up. */
84
#define MSTK_SEC_MASK   0x7f
85
#define MSTK_MIN_MASK   0x7f
86
#define MSTK_HOUR_MASK  0x3f
87
#define MSTK_DOW_MASK   0x07
88
#define MSTK_DOM_MASK   0x3f
89
#define MSTK_MONTH_MASK 0x1f
90
#define MSTK_YEAR_MASK  0xff
91
 
92
/* Binary coded decimal conversion macros. */
93
#define MSTK_REGVAL_TO_DECIMAL(x)  (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
94
#define MSTK_DECIMAL_TO_REGVAL(x)  ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
95
 
96
/* Generic register set and get macros for internal use. */
97
#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
98
#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
99
 
100
/* Macros to make register access easier on our fingers. These give you
101
 * the decimal value of the register requested if applicable. You pass
102
 * the a pointer to a 'struct mostek48t02'.
103
 */
104
#define MSTK_REG_CREG(regs)     (((struct mostek48t02 *)regs)->creg)
105
#define MSTK_REG_SEC(regs)      MSTK_GET(regs,sec,SEC)
106
#define MSTK_REG_MIN(regs)      MSTK_GET(regs,min,MIN)
107
#define MSTK_REG_HOUR(regs)     MSTK_GET(regs,hour,HOUR)
108
#define MSTK_REG_DOW(regs)      MSTK_GET(regs,dow,DOW)
109
#define MSTK_REG_DOM(regs)      MSTK_GET(regs,dom,DOM)
110
#define MSTK_REG_MONTH(regs)    MSTK_GET(regs,month,MONTH)
111
#define MSTK_REG_YEAR(regs)     MSTK_GET(regs,year,YEAR)
112
 
113
#define MSTK_SET_REG_SEC(regs,value)    MSTK_SET(regs,sec,value,SEC)
114
#define MSTK_SET_REG_MIN(regs,value)    MSTK_SET(regs,min,value,MIN)
115
#define MSTK_SET_REG_HOUR(regs,value)   MSTK_SET(regs,hour,value,HOUR)
116
#define MSTK_SET_REG_DOW(regs,value)    MSTK_SET(regs,dow,value,DOW)
117
#define MSTK_SET_REG_DOM(regs,value)    MSTK_SET(regs,dom,value,DOM)
118
#define MSTK_SET_REG_MONTH(regs,value)  MSTK_SET(regs,month,value,MONTH)
119
#define MSTK_SET_REG_YEAR(regs,value)   MSTK_SET(regs,year,value,YEAR)
120
 
121
 
122
/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
123
 * same (basically) layout of the 48t02 chip except for the extra
124
 * NVRAM on board (8 KB against the 48t02's 2 KB).
125
 */
126
struct mostek48t08 {
127
        char offset[6*1024];         /* Magic things may be here, who knows? */
128
        struct mostek48t02 regs;     /* Here is what we are interested in.   */
129
};
130
extern struct mostek48t08 *mstk48t08_regs;
131
 
132
extern enum sparc_clock_type sp_clock_typ;
133
 
134
#ifdef CONFIG_SUN4
135
enum sparc_clock_type { MSTK48T02, MSTK48T08, \
136
INTERSIL, MSTK_INVALID };
137
#else
138
enum sparc_clock_type { MSTK48T02, MSTK48T08, \
139
MSTK_INVALID };
140
#endif
141
 
142
#ifdef CONFIG_SUN4
143
/* intersil on a sun 4/260 code  data from harris doc */
144
struct intersil_dt {
145
        volatile unsigned char int_csec;
146
        volatile unsigned char int_hour;
147
        volatile unsigned char int_min;
148
        volatile unsigned char int_sec;
149
        volatile unsigned char int_month;
150
        volatile unsigned char int_day;
151
        volatile unsigned char int_year;
152
        volatile unsigned char int_dow;
153
};
154
 
155
struct intersil {
156
        struct intersil_dt clk;
157
        struct intersil_dt cmp;
158
        volatile unsigned char int_intr_reg;
159
        volatile unsigned char int_cmd_reg;
160
};
161
 
162
#define INTERSIL_STOP        0x0
163
#define INTERSIL_START       0x8
164
#define INTERSIL_INTR_DISABLE   0x0
165
#define INTERSIL_INTR_ENABLE   0x10
166
#define INTERSIL_32K            0x0
167
#define INTERSIL_NORMAL         0x0
168
#define INTERSIL_24H            0x4 
169
#define INTERSIL_INT_100HZ      0x2
170
 
171
/* end of intersil info */
172
#endif
173
 
174
#endif /* !(_SPARC_MOSTEK_H) */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.